From 3a843f924ba0a80da6b929e74f59842a6f27662b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fin=20Maa=C3=9F?= Date: Tue, 11 Jun 2024 09:46:03 +0200 Subject: [PATCH] dts: riscv: litex: remove atomic extention MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit remove atomic extention, as the standard vexriscv has no A. Signed-off-by: Fin Maaß --- dts/riscv/riscv32-litex-vexriscv.dtsi | 2 +- soc/litex/litex_vexriscv/Kconfig | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/dts/riscv/riscv32-litex-vexriscv.dtsi b/dts/riscv/riscv32-litex-vexriscv.dtsi index 6ae55a82016..3f98f9053e6 100644 --- a/dts/riscv/riscv32-litex-vexriscv.dtsi +++ b/dts/riscv/riscv32-litex-vexriscv.dtsi @@ -25,7 +25,7 @@ compatible = "litex,vexriscv-standard", "riscv"; device_type = "cpu"; reg = <0>; - riscv,isa = "rv32ima_zicsr_zifencei"; + riscv,isa = "rv32im_zicsr_zifencei"; status = "okay"; }; }; diff --git a/soc/litex/litex_vexriscv/Kconfig b/soc/litex/litex_vexriscv/Kconfig index b13181f0177..b841a1dcb41 100644 --- a/soc/litex/litex_vexriscv/Kconfig +++ b/soc/litex/litex_vexriscv/Kconfig @@ -7,7 +7,6 @@ config SOC_LITEX_VEXRISCV select INCLUDE_RESET_VECTOR select RISCV_ISA_RV32I select RISCV_ISA_EXT_M - select RISCV_ISA_EXT_A select RISCV_ISA_EXT_ZICSR select RISCV_ISA_EXT_ZIFENCEI