michaelh/zephyr
1
0
Fork 0
Code Releases Activity

riscv: isr.S: fix a missing lw to LR conversion

Browse source 
This loads a pointer and therefore has to use LR to be 64-bit
compatible.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
This commit is contained in:
Nicolas Pitre 2019-08-04 22:38:34 -04:00 • committed by Carles Cufí
commit 39ada71688
1 changed files with 1 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

2
arch/riscv/core/isr.S
View file

@ -253,7 +253,7 @@ call_irq:
LR a0, 0x00(t0) LR a0, 0x00(t0)
/* Load ISR function address in register t1 */ /* Load ISR function address in register t1 */
lw t1, RV_REGSIZE(t0) LR t1, RV_REGSIZE(t0)
#ifdef CONFIG_EXECUTION_BENCHMARKING #ifdef CONFIG_EXECUTION_BENCHMARKING
addi sp, sp, -16 addi sp, sp, -16