From 39ada716887111fa36a3581ef8fe0ef367161fb3 Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Sun, 4 Aug 2019 22:38:34 -0400 Subject: [PATCH] riscv: isr.S: fix a missing lw to LR conversion This loads a pointer and therefore has to use LR to be 64-bit compatible. Signed-off-by: Nicolas Pitre --- arch/riscv/core/isr.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/core/isr.S b/arch/riscv/core/isr.S index bd2936514ef..f617d03bca8 100644 --- a/arch/riscv/core/isr.S +++ b/arch/riscv/core/isr.S @@ -253,7 +253,7 @@ call_irq: LR a0, 0x00(t0) /* Load ISR function address in register t1 */ - lw t1, RV_REGSIZE(t0) + LR t1, RV_REGSIZE(t0) #ifdef CONFIG_EXECUTION_BENCHMARKING addi sp, sp, -16