diff --git a/dts/arm/nordic/nrf52833.dtsi b/dts/arm/nordic/nrf52833.dtsi new file mode 100644 index 00000000000..0c6029bd304 --- /dev/null +++ b/dts/arm/nordic/nrf52833.dtsi @@ -0,0 +1,392 @@ +/* + * Copyright (c) 2019 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include "nrf5_common.dtsi" + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m4f"; + reg = <0>; + }; + }; + + aliases { + i2c-0 = &i2c0; + i2c-1 = &i2c1; + spi-0 = &spi0; + spi-1 = &spi1; + spi-2 = &spi2; + spi-3 = &spi3; + uart-0 = &uart0; + uart-1 = &uart1; + adc-0 = &adc; + gpio-0 = &gpio0; + gpio-1 = &gpio1; + gpiote-0 = &gpiote; + wdt-0 = &wdt; + usbd-0 = &usbd; + pwm-0 = &pwm0; + pwm-1 = &pwm1; + pwm-2 = &pwm2; + pwm-3 = &pwm3; + qdec-0 = &qdec; + rtc-0 = &rtc0; + rtc-1 = &rtc1; + rtc-2 = &rtc2; + timer-0 = &timer0; + timer-1 = &timer1; + timer-2 = &timer2; + timer-3 = &timer3; + timer-4 = &timer4; + }; + + soc { + + flash-controller@4001e000 { + compatible = "nordic,nrf52-flash-controller"; + reg = <0x4001e000 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + + label="NRF_FLASH_DRV_NAME"; + + flash0: flash@0 { + compatible = "soc-nv-flash"; + label = "NRF_FLASH"; + erase-block-size = <4096>; + write-block-size = <4>; + }; + }; + + sram0: memory@20000000 { + compatible = "mmio-sram"; + }; + + adc: adc@40007000 { + compatible = "nordic,nrf-saadc"; + reg = <0x40007000 0x1000>; + interrupts = <7 1>; + status = "disabled"; + label = "ADC_0"; + #io-channel-cells = <1>; + }; + + clock: clock@40000000 { + compatible = "nordic,nrf-clock"; + reg = <0x40000000 0x1000>; + interrupts = <0 1>; + status = "okay"; + label = "CLOCK"; + }; + + uart0: uart@40002000 { + /* uart can be either UART or UARTE, for the user to pick */ + /* compatible = "nordic,nrf-uarte" or "nordic,nrf-uart"; */ + reg = <0x40002000 0x1000>; + interrupts = <2 1>; + status = "disabled"; + label = "UART_0"; + }; + + uart1: uart@40028000 { + compatible = "nordic,nrf-uarte"; + reg = <0x40028000 0x1000>; + interrupts = <40 1>; + status = "disabled"; + label = "UART_1"; + }; + + gpiote: gpiote@40006000 { + compatible = "nordic,nrf-gpiote"; + reg = <0x40006000 0x1000>; + interrupts = <6 5>; + status = "disabled"; + label = "GPIOTE_0"; + }; + + gpio0: gpio@50000000 { + compatible = "nordic,nrf-gpio"; + gpio-controller; + reg = <0x50000000 0x200 + 0x50000500 0x300>; + #gpio-cells = <2>; + label = "GPIO_0"; + status = "disabled"; + }; + + gpio1: gpio@50000300 { + compatible = "nordic,nrf-gpio"; + gpio-controller; + reg = <0x50000300 0x200 + 0x50000800 0x300>; + #gpio-cells = <2>; + label = "GPIO_1"; + status = "disabled"; + }; + + i2c0: i2c@40003000 { + /* + * This i2c node can be TWI, TWIM, or TWIS, + * for the user to pick: + * compatible = "nordic,nrf-twi" or + * "nordic,nrf-twim" or + * "nordic,nrf-twis". + */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40003000 0x1000>; + clock-frequency = ; + interrupts = <3 1>; + status = "disabled"; + label = "I2C_0"; + }; + + i2c1: i2c@40004000 { + /* + * This i2c node can be TWI, TWIM, or TWIS, + * for the user to pick: + * compatible = "nordic,nrf-twi" or + * "nordic,nrf-twim" or + * "nordic,nrf-twis". + */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40004000 0x1000>; + clock-frequency = ; + interrupts = <4 1>; + status = "disabled"; + label = "I2C_1"; + }; + + pwm0: pwm@4001c000 { + compatible = "nordic,nrf-pwm"; + reg = <0x4001c000 0x1000>; + interrupts = <28 1>; + status = "disabled"; + label = "PWM_0"; + #pwm-cells = <1>; + }; + + pwm1: pwm@40021000 { + compatible = "nordic,nrf-pwm"; + reg = <0x40021000 0x1000>; + interrupts = <33 1>; + status = "disabled"; + label = "PWM_1"; + #pwm-cells = <1>; + }; + + pwm2: pwm@40022000 { + compatible = "nordic,nrf-pwm"; + reg = <0x40022000 0x1000>; + interrupts = <34 1>; + status = "disabled"; + label = "PWM_2"; + #pwm-cells = <1>; + }; + + pwm3: pwm@4002d000 { + compatible = "nordic,nrf-pwm"; + reg = <0x4002d000 0x1000>; + interrupts = <45 1>; + status = "disabled"; + label = "PWM_3"; + #pwm-cells = <1>; + }; + + qdec: qdec@40012000 { + compatible = "nordic,nrf-qdec"; + reg = <0x40012000 0x1000>; + interrupts = <18 1>; + status = "disabled"; + label = "QDEC"; + }; + + spi0: spi@40003000 { + /* + * This spi node can be SPI, SPIM, or SPIS, + * for the user to pick: + * compatible = "nordic,nrf-spi" or + * "nordic,nrf-spim" or + * "nordic,nrf-spis". + */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40003000 0x1000>; + interrupts = <3 1>; + status = "disabled"; + label = "SPI_0"; + }; + + spi1: spi@40004000 { + /* + * This spi node can be SPI, SPIM, or SPIS, + * for the user to pick: + * compatible = "nordic,nrf-spi" or + * "nordic,nrf-spim" or + * "nordic,nrf-spis". + */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40004000 0x1000>; + interrupts = <4 1>; + status = "disabled"; + label = "SPI_1"; + }; + + spi2: spi@40023000 { + /* + * This spi node can be SPI, SPIM, or SPIS, + * for the user to pick: + * compatible = "nordic,nrf-spi" or + * "nordic,nrf-spim" or + * "nordic,nrf-spis". + */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40023000 0x1000>; + interrupts = <35 1>; + status = "disabled"; + label = "SPI_2"; + }; + + spi3: spi@4002f000 { + compatible = "nordic,nrf-spim"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4002f000 0x1000>; + interrupts = <47 1>; + status = "disabled"; + label = "SPI_3"; + }; + + rtc0: rtc@4000b000 { + compatible = "nordic,nrf-rtc"; + reg = <0x4000b000 0x1000>; + interrupts = <11 1>; + status = "okay"; + clock-frequency = <32768>; + prescaler = <1>; + label = "RTC_0"; + }; + + rtc1: rtc@40011000 { + compatible = "nordic,nrf-rtc"; + reg = <0x40011000 0x1000>; + interrupts = <17 1>; + status = "okay"; + clock-frequency = <32768>; + prescaler = <1>; + label = "RTC_1"; + }; + + rtc2: rtc@40024000 { + compatible = "nordic,nrf-rtc"; + reg = <0x40024000 0x1000>; + interrupts = <36 1>; + status = "okay"; + clock-frequency = <32768>; + prescaler = <1>; + label = "RTC_2"; + }; + + timer0: timer@40008000 { + compatible = "nordic,nrf-timer"; + status = "okay"; + reg = <0x40008000 0x1000>; + interrupts = <8 1>; + prescaler = <0>; + label = "TIMER_0"; + }; + + timer1: timer@40009000 { + compatible = "nordic,nrf-timer"; + status = "okay"; + reg = <0x40009000 0x1000>; + interrupts = <9 1>; + prescaler = <0>; + label = "TIMER_1"; + }; + + timer2: timer@4000a000 { + compatible = "nordic,nrf-timer"; + status = "okay"; + reg = <0x4000a000 0x1000>; + interrupts = <10 1>; + prescaler = <0>; + label = "TIMER_2"; + }; + + timer3: timer@4001a000 { + compatible = "nordic,nrf-timer"; + status = "okay"; + reg = <0x4001a000 0x1000>; + interrupts = <26 1>; + prescaler = <0>; + label = "TIMER_3"; + }; + + timer4: timer@4001b000 { + compatible = "nordic,nrf-timer"; + status = "okay"; + reg = <0x4001b000 0x1000>; + interrupts = <27 1>; + prescaler = <0>; + label = "TIMER_4"; + }; + + temp: temp@4000c000 { + compatible = "nordic,nrf-temp"; + reg = <0x4000c000 0x1000>; + interrupts = <12 1>; + status = "okay"; + label = "TEMP_0"; + }; + + usbd: usbd@40027000 { + compatible = "nordic,nrf-usbd"; + reg = <0x40027000 0x1000>; + interrupts = <39 1>; + num-bidir-endpoints = <1>; + num-in-endpoints = <7>; + num-out-endpoints = <7>; + num-isoin-endpoints = <1>; + num-isoout-endpoints = <1>; + status = "disabled"; + label = "USBD"; + }; + + wdt: watchdog@40010000 { + compatible = "nordic,nrf-watchdog"; + reg = <0x40010000 0x1000>; + interrupts = <16 1>; + status = "okay"; + label = "WDT"; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <3>; +}; + +&sw_pwm { + timer-instance = <2>; + channel-count = <3>; + clock-prescaler = <0>; + ppi-base = <14>; + gpiote-base = <0>; + #pwm-cells = <1>; +}; diff --git a/dts/arm/nordic/nrf52833_qiaa.dtsi b/dts/arm/nordic/nrf52833_qiaa.dtsi new file mode 100644 index 00000000000..71efb1cad5e --- /dev/null +++ b/dts/arm/nordic/nrf52833_qiaa.dtsi @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2019 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +&flash0 { + reg = <0x00000000 DT_SIZE_K(512)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(128)>; +}; + +/ { + soc { + compatible = "nordic,nRF52833-QIAA", "nordic,nRF52833", "nordic,nRF52", "simple-bus"; + }; +}; diff --git a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52833_QIAA b/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52833_QIAA new file mode 100644 index 00000000000..db805dfca61 --- /dev/null +++ b/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52833_QIAA @@ -0,0 +1,22 @@ +# Kconfig.defconfig.nrf52833 - Nordic Semiconductor nRF52833 MCU +# +# Copyright (c) 2019 Nordic Semiconductor ASA +# +# SPDX-License-Identifier: Apache-2.0 +# + + +if SOC_NRF52833_QIAA + +config SOC + string + default "nRF52833_QIAA" + +config NUM_IRQS + int + default 48 + +config NET_CONFIG_IEEE802154_DEV_NAME + default IEEE802154_NRF5_DRV_NAME + +endif # SOC_NRF52833_QIAA diff --git a/soc/arm/nordic_nrf/nrf52/Kconfig.soc b/soc/arm/nordic_nrf/nrf52/Kconfig.soc index 744c893cd40..0dc946c51a7 100644 --- a/soc/arm/nordic_nrf/nrf52/Kconfig.soc +++ b/soc/arm/nordic_nrf/nrf52/Kconfig.soc @@ -155,6 +155,77 @@ config SOC_NRF52832 select HAS_HW_NRF_UARTE0 select HAS_HW_NRF_WDT +config SOC_NRF52833 + depends on SOC_SERIES_NRF52X + bool + select CPU_HAS_FPU + select HAS_HW_NRF_ACL + select HAS_HW_NRF_CCM + select HAS_HW_NRF_CLOCK + select HAS_HW_NRF_COMP + select HAS_HW_NRF_ECB + select HAS_HW_NRF_EGU0 + select HAS_HW_NRF_EGU1 + select HAS_HW_NRF_EGU2 + select HAS_HW_NRF_EGU3 + select HAS_HW_NRF_EGU4 + select HAS_HW_NRF_EGU5 + select HAS_HW_NRF_GPIO0 + select HAS_HW_NRF_GPIO1 + select HAS_HW_NRF_GPIOTE + select HAS_HW_NRF_I2S + select HAS_HW_NRF_LPCOMP + select HAS_HW_NRF_MWU + select HAS_HW_NRF_NFCT + select HAS_HW_NRF_PDM + select HAS_HW_NRF_POWER + select HAS_HW_NRF_PPI + select HAS_HW_NRF_PWM0 + select HAS_HW_NRF_PWM1 + select HAS_HW_NRF_PWM2 + select HAS_HW_NRF_PWM3 + select HAS_HW_NRF_QDEC + select HAS_HW_NRF_RADIO_BLE_CODED + select HAS_HW_NRF_RADIO_IEEE802154 + select HAS_HW_NRF_RNG + select HAS_HW_NRF_RTC0 + select HAS_HW_NRF_RTC1 + select HAS_HW_NRF_RTC2 + select HAS_HW_NRF_SAADC + select HAS_HW_NRF_SPI0 + select HAS_HW_NRF_SPI1 + select HAS_HW_NRF_SPI2 + select HAS_HW_NRF_SPIM0 + select HAS_HW_NRF_SPIM1 + select HAS_HW_NRF_SPIM2 + select HAS_HW_NRF_SPIM3 + select HAS_HW_NRF_SPIS0 + select HAS_HW_NRF_SPIS1 + select HAS_HW_NRF_SPIS2 + select HAS_HW_NRF_SWI0 + select HAS_HW_NRF_SWI1 + select HAS_HW_NRF_SWI2 + select HAS_HW_NRF_SWI3 + select HAS_HW_NRF_SWI4 + select HAS_HW_NRF_SWI5 + select HAS_HW_NRF_TEMP + select HAS_HW_NRF_TIMER0 + select HAS_HW_NRF_TIMER1 + select HAS_HW_NRF_TIMER2 + select HAS_HW_NRF_TIMER3 + select HAS_HW_NRF_TIMER4 + select HAS_HW_NRF_TWI0 + select HAS_HW_NRF_TWI1 + select HAS_HW_NRF_TWIM0 + select HAS_HW_NRF_TWIM1 + select HAS_HW_NRF_TWIS0 + select HAS_HW_NRF_TWIS1 + select HAS_HW_NRF_UART0 + select HAS_HW_NRF_UARTE0 + select HAS_HW_NRF_UARTE1 + select HAS_HW_NRF_USBD + select HAS_HW_NRF_WDT + config SOC_NRF52840 depends on SOC_SERIES_NRF52X bool @@ -252,6 +323,10 @@ config SOC_NRF52832_QFAB bool "NRF52832_QFAB" select SOC_NRF52832 +config SOC_NRF52833_QIAA + bool "NRF52833_QIAA" + select SOC_NRF52833 + config SOC_NRF52840_QIAA bool "NRF52840_QIAA" select SOC_NRF52840 @@ -265,7 +340,7 @@ config SOC_DCDC_NRF52X config NFCT_PINS_AS_GPIOS bool "NFCT pins as GPIOs" - depends on SOC_NRF52832 || SOC_NRF52840 + depends on HAS_HW_NRF_NFCT help P0.9 and P0.10 are usually reserved for NFC. This option switch them to normal GPIO mode. HW enabling happens once in the device @@ -281,5 +356,5 @@ config GPIO_AS_PINRESET config NRF_ENABLE_ICACHE bool "Enable the instruction cache (I-Cache)" - depends on SOC_NRF52832 || SOC_NRF52840 + depends on SOC_NRF52832 || SOC_NRF52833 || SOC_NRF52840 default y diff --git a/soc/arm/nordic_nrf/nrf52/soc.c b/soc/arm/nordic_nrf/nrf52/soc.c index 739087767f8..b32a45e69c0 100644 --- a/soc/arm/nordic_nrf/nrf52/soc.c +++ b/soc/arm/nordic_nrf/nrf52/soc.c @@ -32,6 +32,8 @@ extern void z_arm_nmi_init(void); #include #elif defined(CONFIG_SOC_NRF52832) #include +#elif defined(CONFIG_SOC_NRF52833) +#include #elif defined(CONFIG_SOC_NRF52840) #include #else