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dts: bindings: clock: Change clock control binding for Renesas RA

Browse source 
Background of this modification is to make clock control
driver code provided by Renesas vendor to support for Renesas MCU
on Zephyr.

Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
This commit is contained in:
Quy Tran 2024-06-20 09:49:31 +00:00 • committed by Anas Nashif
commit 370bd31d2a
47 changed files with 115 additions and 112 deletions
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2
boards/renesas/ek_ra6e2/doc/index.rst
View file

@ -96,6 +96,8 @@ The below features are currently supported on Zephyr OS for EK-RA6E2 board:
+-----------+------------+----------------------+
| UART | on-chip | serial |
+-----------+------------+----------------------+
| CLOCK | on-chip | clock control |
+-----------+------------+----------------------+
Other hardware features are currently not supported by the port.

1
boards/renesas/ek_ra6e2/ek_ra6e2.dts
View file

@ -97,6 +97,5 @@
source = <RA_PLL_SOURCE_MAIN_OSC>;
div = <RA_PLL_DIV_1>;
mul = <10 0>;
freq = <DT_FREQ_M(200)>;
status = "okay";
};

1
boards/renesas/ek_ra6e2/ek_ra6e2_defconfig
View file

@ -15,3 +15,4 @@ CONFIG_CONSOLE=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_BUILD_NO_GAP_FILL=y
CONFIG_CLOCK_CONTROL=y

2
boards/renesas/ek_ra6m1/doc/index.rst
View file

@ -92,6 +92,8 @@ The below features are currently supported on Zephyr OS for EK-RA6M1 board:
+-----------+------------+----------------------+
| UART | on-chip | serial |
+-----------+------------+----------------------+
| CLOCK | on-chip | clock control |
+-----------+------------+----------------------+
Other hardware features are currently not supported by the port.

1
boards/renesas/ek_ra6m1/ek_ra6m1_defconfig
View file

@ -9,6 +9,7 @@ CONFIG_PINCTRL=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_BUILD_NO_GAP_FILL=y
CONFIG_CLOCK_CONTROL=y
# Enable Console
CONFIG_SERIAL=y

2
boards/renesas/ek_ra6m2/doc/index.rst
View file

@ -86,6 +86,8 @@ The below features are currently supported on Zephyr OS for EK-RA6M2 board:
+-----------+------------+----------------------+
| UART | on-chip | serial |
+-----------+------------+----------------------+
| CLOCK | on-chip | clock control |
+-----------+------------+----------------------+
Other hardware features are currently not supported by the port.

6
boards/renesas/ek_ra6m2/ek_ra6m2.dts
View file

@ -65,9 +65,3 @@
mul = <20 0>;
status = "okay";
};
&pclka {
clk_src = <RA_CLOCK_SOURCE_PLL>;
clk_div = <RA_SCI_CLOCK_DIV_2>;
status = "okay";
};

1
boards/renesas/ek_ra6m2/ek_ra6m2_defconfig
View file

@ -9,6 +9,7 @@ CONFIG_PINCTRL=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_BUILD_NO_GAP_FILL=y
CONFIG_CLOCK_CONTROL=y
# Enable Console
CONFIG_SERIAL=y

2
boards/renesas/ek_ra6m3/doc/index.rst
View file

@ -94,6 +94,8 @@ The below features are currently supported on Zephyr OS for EK-RA6M3 board:
+-----------+------------+----------------------+
| UART | on-chip | serial |
+-----------+------------+----------------------+
| CLOCK | on-chip | clock control |
+-----------+------------+----------------------+
Other hardware features are currently not supported by the port.

1
boards/renesas/ek_ra6m3/ek_ra6m3.dts
View file

@ -75,6 +75,5 @@
source = <RA_PLL_SOURCE_MAIN_OSC>;
div = <RA_PLL_DIV_2>;
mul = <20 0>;
freq = <DT_FREQ_M(240)>;
status = "okay";
};

1
boards/renesas/ek_ra6m3/ek_ra6m3_defconfig
View file

@ -15,3 +15,4 @@ CONFIG_UART_CONSOLE=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_BUILD_NO_GAP_FILL=y
CONFIG_CLOCK_CONTROL=y

2
boards/renesas/ek_ra6m4/doc/index.rst
View file

@ -99,6 +99,8 @@ The below features are currently supported on Zephyr OS for EK-RA6M4 board:
+-----------+------------+----------------------+
| UART | on-chip | serial |
+-----------+------------+----------------------+
| CLOCK | on-chip | clock control |
+-----------+------------+----------------------+
Other hardware features are currently not supported by the port.

1
boards/renesas/ek_ra6m4/ek_ra6m4.dts
View file

@ -71,7 +71,6 @@
source = <RA_PLL_SOURCE_MAIN_OSC>;
div = <RA_PLL_DIV_3>;
mul = <25 0>;
freq = <DT_FREQ_M(200)>;
status = "okay";
};

1
boards/renesas/ek_ra6m4/ek_ra6m4_defconfig
View file

@ -15,3 +15,4 @@ CONFIG_UART_CONSOLE=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_BUILD_NO_GAP_FILL=y
CONFIG_CLOCK_CONTROL=y

2
boards/renesas/ek_ra6m5/doc/index.rst
View file

@ -97,6 +97,8 @@ The below features are currently supported on Zephyr OS for EK-RA6M5 board:
+-----------+------------+----------------------+
| UART | on-chip | serial |
+-----------+------------+----------------------+
| CLOCK | on-chip | clock control |
+-----------+------------+----------------------+
Other hardware features are currently not supported by the port.

1
boards/renesas/ek_ra6m5/ek_ra6m5.dts
View file

@ -71,6 +71,5 @@
source = <RA_PLL_SOURCE_MAIN_OSC>;
div = <RA_PLL_DIV_3>;
mul = <25 0>;
freq = <DT_FREQ_M(200)>;
status = "okay";
};

1
boards/renesas/ek_ra6m5/ek_ra6m5_defconfig
View file

@ -9,6 +9,7 @@ CONFIG_PINCTRL=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_BUILD_NO_GAP_FILL=y
CONFIG_CLOCK_CONTROL=y
# Enable Console
CONFIG_SERIAL=y

1
boards/renesas/fpb_ra6e1/fpb_ra6e1.dts
View file

@ -60,7 +60,6 @@
source = <RA_PLL_SOURCE_HOCO>;
div = <RA_PLL_DIV_2>;
mul = <20 0>;
freq = <DT_FREQ_M(200)>;
status = "okay";
};

2
boards/renesas/fpb_ra6e1/fpb_ra6e1_defconfig
View file

@ -15,3 +15,5 @@ CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_UART_CONSOLE=y
CONFIG_CONSOLE=y
CONFIG_CLOCK_CONTROL=y

6
boards/renesas/fpb_ra6e2/fpb_ra6e2.dts
View file

@ -81,9 +81,3 @@
mul = <10 0>;
status = "okay";
};
&pclka {
clk_src = <RA_CLOCK_SOURCE_PLL>;
clk_div = <RA_SCI_CLOCK_DIV_2>;
status = "okay";
};

1
boards/renesas/fpb_ra6e2/fpb_ra6e2_defconfig
View file

@ -15,3 +15,4 @@ CONFIG_CONSOLE=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_BUILD_NO_GAP_FILL=y
CONFIG_CLOCK_CONTROL=y