diff --git a/boards/renesas/ek_ra6e2/doc/index.rst b/boards/renesas/ek_ra6e2/doc/index.rst index 46c95b52801..aad21a93ea4 100644 --- a/boards/renesas/ek_ra6e2/doc/index.rst +++ b/boards/renesas/ek_ra6e2/doc/index.rst @@ -96,6 +96,8 @@ The below features are currently supported on Zephyr OS for EK-RA6E2 board: +-----------+------------+----------------------+ | UART | on-chip | serial | +-----------+------------+----------------------+ +| CLOCK | on-chip | clock control | ++-----------+------------+----------------------+ Other hardware features are currently not supported by the port. diff --git a/boards/renesas/ek_ra6e2/ek_ra6e2.dts b/boards/renesas/ek_ra6e2/ek_ra6e2.dts index d58feb122fc..682aafcd006 100644 --- a/boards/renesas/ek_ra6e2/ek_ra6e2.dts +++ b/boards/renesas/ek_ra6e2/ek_ra6e2.dts @@ -97,6 +97,5 @@ source = ; div = ; mul = <10 0>; - freq = ; status = "okay"; }; diff --git a/boards/renesas/ek_ra6e2/ek_ra6e2_defconfig b/boards/renesas/ek_ra6e2/ek_ra6e2_defconfig index fd980602204..92bb425cfa8 100644 --- a/boards/renesas/ek_ra6e2/ek_ra6e2_defconfig +++ b/boards/renesas/ek_ra6e2/ek_ra6e2_defconfig @@ -15,3 +15,4 @@ CONFIG_CONSOLE=y CONFIG_BUILD_OUTPUT_HEX=y CONFIG_BUILD_NO_GAP_FILL=y +CONFIG_CLOCK_CONTROL=y diff --git a/boards/renesas/ek_ra6m1/doc/index.rst b/boards/renesas/ek_ra6m1/doc/index.rst index 454e77352ac..955c87ac32b 100644 --- a/boards/renesas/ek_ra6m1/doc/index.rst +++ b/boards/renesas/ek_ra6m1/doc/index.rst @@ -92,6 +92,8 @@ The below features are currently supported on Zephyr OS for EK-RA6M1 board: +-----------+------------+----------------------+ | UART | on-chip | serial | +-----------+------------+----------------------+ +| CLOCK | on-chip | clock control | ++-----------+------------+----------------------+ Other hardware features are currently not supported by the port. diff --git a/boards/renesas/ek_ra6m1/ek_ra6m1_defconfig b/boards/renesas/ek_ra6m1/ek_ra6m1_defconfig index 8a9dda7f22e..00adc77146e 100644 --- a/boards/renesas/ek_ra6m1/ek_ra6m1_defconfig +++ b/boards/renesas/ek_ra6m1/ek_ra6m1_defconfig @@ -9,6 +9,7 @@ CONFIG_PINCTRL=y CONFIG_BUILD_OUTPUT_HEX=y CONFIG_BUILD_NO_GAP_FILL=y +CONFIG_CLOCK_CONTROL=y # Enable Console CONFIG_SERIAL=y diff --git a/boards/renesas/ek_ra6m2/doc/index.rst b/boards/renesas/ek_ra6m2/doc/index.rst index 2f43fb0b41e..a3cb9f0e887 100644 --- a/boards/renesas/ek_ra6m2/doc/index.rst +++ b/boards/renesas/ek_ra6m2/doc/index.rst @@ -86,6 +86,8 @@ The below features are currently supported on Zephyr OS for EK-RA6M2 board: +-----------+------------+----------------------+ | UART | on-chip | serial | +-----------+------------+----------------------+ +| CLOCK | on-chip | clock control | ++-----------+------------+----------------------+ Other hardware features are currently not supported by the port. diff --git a/boards/renesas/ek_ra6m2/ek_ra6m2.dts b/boards/renesas/ek_ra6m2/ek_ra6m2.dts index 0f06aa0f098..78407352e72 100644 --- a/boards/renesas/ek_ra6m2/ek_ra6m2.dts +++ b/boards/renesas/ek_ra6m2/ek_ra6m2.dts @@ -65,9 +65,3 @@ mul = <20 0>; status = "okay"; }; - -&pclka { - clk_src = ; - clk_div = ; - status = "okay"; -}; diff --git a/boards/renesas/ek_ra6m2/ek_ra6m2_defconfig b/boards/renesas/ek_ra6m2/ek_ra6m2_defconfig index 8a9dda7f22e..00adc77146e 100644 --- a/boards/renesas/ek_ra6m2/ek_ra6m2_defconfig +++ b/boards/renesas/ek_ra6m2/ek_ra6m2_defconfig @@ -9,6 +9,7 @@ CONFIG_PINCTRL=y CONFIG_BUILD_OUTPUT_HEX=y CONFIG_BUILD_NO_GAP_FILL=y +CONFIG_CLOCK_CONTROL=y # Enable Console CONFIG_SERIAL=y diff --git a/boards/renesas/ek_ra6m3/doc/index.rst b/boards/renesas/ek_ra6m3/doc/index.rst index 163dea98463..bb468d9d1f5 100644 --- a/boards/renesas/ek_ra6m3/doc/index.rst +++ b/boards/renesas/ek_ra6m3/doc/index.rst @@ -94,6 +94,8 @@ The below features are currently supported on Zephyr OS for EK-RA6M3 board: +-----------+------------+----------------------+ | UART | on-chip | serial | +-----------+------------+----------------------+ +| CLOCK | on-chip | clock control | ++-----------+------------+----------------------+ Other hardware features are currently not supported by the port. diff --git a/boards/renesas/ek_ra6m3/ek_ra6m3.dts b/boards/renesas/ek_ra6m3/ek_ra6m3.dts index c87f2951017..0cd4de22aa1 100644 --- a/boards/renesas/ek_ra6m3/ek_ra6m3.dts +++ b/boards/renesas/ek_ra6m3/ek_ra6m3.dts @@ -75,6 +75,5 @@ source = ; div = ; mul = <20 0>; - freq = ; status = "okay"; }; diff --git a/boards/renesas/ek_ra6m3/ek_ra6m3_defconfig b/boards/renesas/ek_ra6m3/ek_ra6m3_defconfig index 0c3698276ae..31c2fa759e4 100644 --- a/boards/renesas/ek_ra6m3/ek_ra6m3_defconfig +++ b/boards/renesas/ek_ra6m3/ek_ra6m3_defconfig @@ -15,3 +15,4 @@ CONFIG_UART_CONSOLE=y CONFIG_BUILD_OUTPUT_HEX=y CONFIG_BUILD_NO_GAP_FILL=y +CONFIG_CLOCK_CONTROL=y diff --git a/boards/renesas/ek_ra6m4/doc/index.rst b/boards/renesas/ek_ra6m4/doc/index.rst index 990f6c3289d..82549000d63 100644 --- a/boards/renesas/ek_ra6m4/doc/index.rst +++ b/boards/renesas/ek_ra6m4/doc/index.rst @@ -99,6 +99,8 @@ The below features are currently supported on Zephyr OS for EK-RA6M4 board: +-----------+------------+----------------------+ | UART | on-chip | serial | +-----------+------------+----------------------+ +| CLOCK | on-chip | clock control | ++-----------+------------+----------------------+ Other hardware features are currently not supported by the port. diff --git a/boards/renesas/ek_ra6m4/ek_ra6m4.dts b/boards/renesas/ek_ra6m4/ek_ra6m4.dts index d07f685d7c9..5fcb92a2b93 100644 --- a/boards/renesas/ek_ra6m4/ek_ra6m4.dts +++ b/boards/renesas/ek_ra6m4/ek_ra6m4.dts @@ -71,7 +71,6 @@ source = ; div = ; mul = <25 0>; - freq = ; status = "okay"; }; diff --git a/boards/renesas/ek_ra6m4/ek_ra6m4_defconfig b/boards/renesas/ek_ra6m4/ek_ra6m4_defconfig index 1bf2405eb28..45a5a73366a 100644 --- a/boards/renesas/ek_ra6m4/ek_ra6m4_defconfig +++ b/boards/renesas/ek_ra6m4/ek_ra6m4_defconfig @@ -15,3 +15,4 @@ CONFIG_UART_CONSOLE=y CONFIG_BUILD_OUTPUT_HEX=y CONFIG_BUILD_NO_GAP_FILL=y +CONFIG_CLOCK_CONTROL=y diff --git a/boards/renesas/ek_ra6m5/doc/index.rst b/boards/renesas/ek_ra6m5/doc/index.rst index cf2db4c2131..bc94a155e11 100644 --- a/boards/renesas/ek_ra6m5/doc/index.rst +++ b/boards/renesas/ek_ra6m5/doc/index.rst @@ -97,6 +97,8 @@ The below features are currently supported on Zephyr OS for EK-RA6M5 board: +-----------+------------+----------------------+ | UART | on-chip | serial | +-----------+------------+----------------------+ +| CLOCK | on-chip | clock control | ++-----------+------------+----------------------+ Other hardware features are currently not supported by the port. diff --git a/boards/renesas/ek_ra6m5/ek_ra6m5.dts b/boards/renesas/ek_ra6m5/ek_ra6m5.dts index ed608414b78..ad84e26a167 100644 --- a/boards/renesas/ek_ra6m5/ek_ra6m5.dts +++ b/boards/renesas/ek_ra6m5/ek_ra6m5.dts @@ -71,6 +71,5 @@ source = ; div = ; mul = <25 0>; - freq = ; status = "okay"; }; diff --git a/boards/renesas/ek_ra6m5/ek_ra6m5_defconfig b/boards/renesas/ek_ra6m5/ek_ra6m5_defconfig index 4e0bcc095eb..4b5534eb1ff 100644 --- a/boards/renesas/ek_ra6m5/ek_ra6m5_defconfig +++ b/boards/renesas/ek_ra6m5/ek_ra6m5_defconfig @@ -9,6 +9,7 @@ CONFIG_PINCTRL=y CONFIG_BUILD_OUTPUT_HEX=y CONFIG_BUILD_NO_GAP_FILL=y +CONFIG_CLOCK_CONTROL=y # Enable Console CONFIG_SERIAL=y diff --git a/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts b/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts index 6ed03f77aa4..6f734989539 100644 --- a/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts +++ b/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts @@ -60,7 +60,6 @@ source = ; div = ; mul = <20 0>; - freq = ; status = "okay"; }; diff --git a/boards/renesas/fpb_ra6e1/fpb_ra6e1_defconfig b/boards/renesas/fpb_ra6e1/fpb_ra6e1_defconfig index 2d149225b32..fa7ef716d3f 100644 --- a/boards/renesas/fpb_ra6e1/fpb_ra6e1_defconfig +++ b/boards/renesas/fpb_ra6e1/fpb_ra6e1_defconfig @@ -15,3 +15,5 @@ CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_UART_CONSOLE=y CONFIG_CONSOLE=y + +CONFIG_CLOCK_CONTROL=y diff --git a/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts b/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts index a02a58aaf72..bc7baa6c5ce 100644 --- a/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts +++ b/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts @@ -81,9 +81,3 @@ mul = <10 0>; status = "okay"; }; - -&pclka { - clk_src = ; - clk_div = ; - status = "okay"; -}; diff --git a/boards/renesas/fpb_ra6e2/fpb_ra6e2_defconfig b/boards/renesas/fpb_ra6e2/fpb_ra6e2_defconfig index fd980602204..92bb425cfa8 100644 --- a/boards/renesas/fpb_ra6e2/fpb_ra6e2_defconfig +++ b/boards/renesas/fpb_ra6e2/fpb_ra6e2_defconfig @@ -15,3 +15,4 @@ CONFIG_CONSOLE=y CONFIG_BUILD_OUTPUT_HEX=y CONFIG_BUILD_NO_GAP_FILL=y +CONFIG_CLOCK_CONTROL=y diff --git a/drivers/clock_control/Kconfig b/drivers/clock_control/Kconfig index 4c03ce49d56..c7f4493ac0a 100644 --- a/drivers/clock_control/Kconfig +++ b/drivers/clock_control/Kconfig @@ -82,7 +82,7 @@ source "drivers/clock_control/Kconfig.agilex5" source "drivers/clock_control/Kconfig.renesas_ra" -source "drivers/clock_control/Kconfig.renesas_ra8" +source "drivers/clock_control/Kconfig.renesas_ra_cgc" source "drivers/clock_control/Kconfig.max32" diff --git a/drivers/clock_control/Kconfig.renesas_ra8 b/drivers/clock_control/Kconfig.renesas_ra_cgc similarity index 100% rename from drivers/clock_control/Kconfig.renesas_ra8 rename to drivers/clock_control/Kconfig.renesas_ra_cgc diff --git a/drivers/clock_control/clock_control_renesas_ra_cgc.c b/drivers/clock_control/clock_control_renesas_ra_cgc.c index e68c657bfd6..ebbae6ec816 100644 --- a/drivers/clock_control/clock_control_renesas_ra_cgc.c +++ b/drivers/clock_control/clock_control_renesas_ra_cgc.c @@ -77,7 +77,7 @@ static const struct clock_control_driver_api clock_control_reneas_ra_api = { }; #define INIT_PCLK(node_id) \ - IF_ENABLED(DT_NODE_HAS_COMPAT(node_id, renesas_ra8_cgc_pclk), \ + IF_ENABLED(DT_NODE_HAS_COMPAT(node_id, renesas_ra_cgc_pclk), \ (static const struct clock_control_ra_pclk_cfg node_id##_cfg = \ {.clk_src = DT_PROP_OR(node_id, clk_src, RA_CLOCK_SOURCE_DISABLE), \ .clk_div = DT_PROP_OR(node_id, clk_div, RA_SYS_CLOCK_DIV_1)}; \ diff --git a/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi index dd393243085..f281d5199fb 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi @@ -67,7 +67,6 @@ source = ; div = ; mul = <20 0>; - freq = ; status = "disabled"; }; diff --git a/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi index 9ab9d8e8676..2097c1f322a 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi @@ -228,7 +228,6 @@ source = ; div = ; mul = <25 0>; - freq = ; status = "disabled"; }; diff --git a/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi b/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi index 1933e2ff3ba..ed1b5506419 100644 --- a/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi +++ b/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi @@ -10,7 +10,7 @@ / { clocks: clocks { xtal: clock-xtal { - compatible = "renesas,ra8-cgc-external-clock"; + compatible = "renesas,ra-cgc-external-clock"; clock-frequency = ; #clock-cells = <0>; status = "disabled"; @@ -35,14 +35,14 @@ }; subclk: clock-subclk { - compatible = "renesas,ra8-cgc-subclk"; + compatible = "renesas,ra-cgc-subclk"; clock-frequency = <32768>; #clock-cells = <0>; status = "disabled"; }; pll: pll { - compatible = "renesas,ra8-cgc-pll"; + compatible = "renesas,ra-cgc-pll"; #clock-cells = <0>; /* PLL */ @@ -59,7 +59,7 @@ }; pll2: pll2 { - compatible = "renesas,ra8-cgc-pll"; + compatible = "renesas,ra-cgc-pll"; #clock-cells = <0>; /* PLL2 */ @@ -76,65 +76,65 @@ }; pclkblock: pclkblock { - compatible = "renesas,ra8-cgc-pclk-block"; + compatible = "renesas,ra-cgc-pclk-block"; #clock-cells = <0>; sysclock-src = ; status = "okay"; cpuclk: cpuclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; #clock-cells = <2>; status = "okay"; }; iclk: iclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; #clock-cells = <2>; status = "okay"; }; pclka: pclka { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; #clock-cells = <2>; status = "okay"; }; pclke: pclke { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; #clock-cells = <2>; status = "okay"; }; bclk: bclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; bclkout: bclkout { - compatible = "renesas,ra8-cgc-busclk"; + compatible = "renesas,ra-cgc-busclk"; clk_out_div = <2>; sdclk = <1>; #clock-cells = <0>; @@ -144,62 +144,62 @@ }; fclk: fclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; #clock-cells = <2>; status = "okay"; }; clkout: clkout { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; sciclk: sciclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; spiclk: spiclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; canfdclk: canfdclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; i3cclk: i3cclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; uclk: uclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; u60clk: u60clk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; octaspiclk: octaspiclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; lcdclk: lcdclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; diff --git a/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi b/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi index 53393b24942..21c2468dd82 100644 --- a/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi +++ b/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi @@ -10,7 +10,7 @@ / { clocks: clocks { xtal: clock-xtal { - compatible = "renesas,ra8-cgc-external-clock"; + compatible = "renesas,ra-cgc-external-clock"; clock-frequency = ; #clock-cells = <0>; status = "disabled"; @@ -35,14 +35,14 @@ }; subclk: clock-subclk { - compatible = "renesas,ra8-cgc-subclk"; + compatible = "renesas,ra-cgc-subclk"; clock-frequency = <32768>; #clock-cells = <0>; status = "disabled"; }; pll: pll { - compatible = "renesas,ra8-cgc-pll"; + compatible = "renesas,ra-cgc-pll"; #clock-cells = <0>; /* PLL */ @@ -59,7 +59,7 @@ }; pll2: pll2 { - compatible = "renesas,ra8-cgc-pll"; + compatible = "renesas,ra-cgc-pll"; #clock-cells = <0>; /* PLL2 */ @@ -76,65 +76,65 @@ }; pclkblock: pclkblock { - compatible = "renesas,ra8-cgc-pclk-block"; + compatible = "renesas,ra-cgc-pclk-block"; #clock-cells = <0>; sysclock-src = ; status = "okay"; cpuclk: cpuclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; #clock-cells = <2>; status = "okay"; }; iclk: iclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; #clock-cells = <2>; status = "okay"; }; pclka: pclka { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; #clock-cells = <2>; status = "okay"; }; pclke: pclke { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; #clock-cells = <2>; status = "okay"; }; bclk: bclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; bclkout: bclkout { - compatible = "renesas,ra8-cgc-busclk"; + compatible = "renesas,ra-cgc-busclk"; clk_out_div = <2>; sdclk = <1>; #clock-cells = <0>; @@ -144,56 +144,56 @@ }; fclk: fclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; #clock-cells = <2>; status = "okay"; }; clkout: clkout { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; sciclk: sciclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; spiclk: spiclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; canfdclk: canfdclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; i3cclk: i3cclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; uclk: uclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; u60clk: u60clk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; octaspiclk: octaspiclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; diff --git a/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi b/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi index 7005dc22bf6..59bda1f704c 100644 --- a/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi +++ b/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi @@ -10,7 +10,7 @@ / { clocks: clocks { xtal: clock-xtal { - compatible = "renesas,ra8-cgc-external-clock"; + compatible = "renesas,ra-cgc-external-clock"; clock-frequency = ; #clock-cells = <0>; status = "disabled"; @@ -35,14 +35,14 @@ }; subclk: clock-subclk { - compatible = "renesas,ra8-cgc-subclk"; + compatible = "renesas,ra-cgc-subclk"; clock-frequency = <32768>; #clock-cells = <0>; status = "disabled"; }; pll: pll { - compatible = "renesas,ra8-cgc-pll"; + compatible = "renesas,ra-cgc-pll"; #clock-cells = <0>; /* PLL */ @@ -59,7 +59,7 @@ }; pll2: pll2 { - compatible = "renesas,ra8-cgc-pll"; + compatible = "renesas,ra-cgc-pll"; #clock-cells = <0>; /* PLL2 */ @@ -76,65 +76,65 @@ }; pclkblock: pclkblock { - compatible = "renesas,ra8-cgc-pclk-block"; + compatible = "renesas,ra-cgc-pclk-block"; #clock-cells = <0>; sysclock-src = ; status = "okay"; cpuclk: cpuclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; #clock-cells = <2>; status = "okay"; }; iclk: iclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; #clock-cells = <2>; status = "okay"; }; pclka: pclka { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; #clock-cells = <2>; status = "okay"; }; pclke: pclke { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; #clock-cells = <2>; status = "okay"; }; bclk: bclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; bclkout: bclkout { - compatible = "renesas,ra8-cgc-busclk"; + compatible = "renesas,ra-cgc-busclk"; clk_out_div = <2>; sdclk = <1>; #clock-cells = <0>; @@ -144,62 +144,62 @@ }; fclk: fclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; clk_div = ; #clock-cells = <2>; status = "okay"; }; clkout: clkout { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; sciclk: sciclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; spiclk: spiclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; canfdclk: canfdclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; i3cclk: i3cclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; uclk: uclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; u60clk: u60clk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; octaspiclk: octaspiclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; lcdclk: lcdclk { - compatible = "renesas,ra8-cgc-pclk"; + compatible = "renesas,ra-cgc-pclk"; #clock-cells = <2>; status = "disabled"; }; diff --git a/dts/bindings/clock/renesas,ra8-cgc-busclk.yaml b/dts/bindings/clock/renesas,ra-cgc-busclk.yaml similarity index 85% rename from dts/bindings/clock/renesas,ra8-cgc-busclk.yaml rename to dts/bindings/clock/renesas,ra-cgc-busclk.yaml index 1d2ae985d4c..949a739f2d4 100644 --- a/dts/bindings/clock/renesas,ra8-cgc-busclk.yaml +++ b/dts/bindings/clock/renesas,ra-cgc-busclk.yaml @@ -1,9 +1,9 @@ # Copyright (c) 2024 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 -description: Renesas RA8 External Bus Clock +description: Renesas RA External Bus Clock -compatible: "renesas,ra8-cgc-busclk" +compatible: "renesas,ra-cgc-busclk" include: [clock-controller.yaml, base.yaml] diff --git a/dts/bindings/clock/renesas,ra8-cgc-external-clock.yaml b/dts/bindings/clock/renesas,ra-cgc-external-clock.yaml similarity index 73% rename from dts/bindings/clock/renesas,ra8-cgc-external-clock.yaml rename to dts/bindings/clock/renesas,ra-cgc-external-clock.yaml index cdbefd91b69..3981894c860 100644 --- a/dts/bindings/clock/renesas,ra8-cgc-external-clock.yaml +++ b/dts/bindings/clock/renesas,ra-cgc-external-clock.yaml @@ -1,9 +1,9 @@ # Copyright (c) 2024 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 -description: Renesas RA8 Clock Generation Circuit external clock configuration +description: Renesas RA Clock Generation Circuit external clock configuration -compatible: "renesas,ra8-cgc-external-clock" +compatible: "renesas,ra-cgc-external-clock" include: [fixed-clock.yaml, base.yaml] diff --git a/dts/bindings/clock/renesas,ra8-cgc-pclk-block.yaml b/dts/bindings/clock/renesas,ra-cgc-pclk-block.yaml similarity index 67% rename from dts/bindings/clock/renesas,ra8-cgc-pclk-block.yaml rename to dts/bindings/clock/renesas,ra-cgc-pclk-block.yaml index 9ad2542ba21..6380b712984 100644 --- a/dts/bindings/clock/renesas,ra8-cgc-pclk-block.yaml +++ b/dts/bindings/clock/renesas,ra-cgc-pclk-block.yaml @@ -1,9 +1,9 @@ # Copyright (c) 2024 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 -description: Renesas RA8 clock control node pclk block +description: Renesas RA Clock Control node pclk block -compatible: "renesas,ra8-cgc-pclk-block" +compatible: "renesas,ra-cgc-pclk-block" include: [clock-controller.yaml, base.yaml] diff --git a/dts/bindings/clock/renesas,ra8-cgc-pclk.yaml b/dts/bindings/clock/renesas,ra-cgc-pclk.yaml similarity index 81% rename from dts/bindings/clock/renesas,ra8-cgc-pclk.yaml rename to dts/bindings/clock/renesas,ra-cgc-pclk.yaml index aece92b2570..cc001c17175 100644 --- a/dts/bindings/clock/renesas,ra8-cgc-pclk.yaml +++ b/dts/bindings/clock/renesas,ra-cgc-pclk.yaml @@ -1,9 +1,9 @@ # Copyright (c) 2024 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 -description: Renesas RA8 Clock Control Peripheral Clock +description: Renesas RA Clock Control Peripheral Clock -compatible: "renesas,ra8-cgc-pclk" +compatible: "renesas,ra-cgc-pclk" include: [clock-controller.yaml, base.yaml] diff --git a/dts/bindings/clock/renesas,ra8-cgc-pll.yaml b/dts/bindings/clock/renesas,ra-cgc-pll.yaml similarity index 77% rename from dts/bindings/clock/renesas,ra8-cgc-pll.yaml rename to dts/bindings/clock/renesas,ra-cgc-pll.yaml index a18f6cf15d9..a974f54c075 100644 --- a/dts/bindings/clock/renesas,ra8-cgc-pll.yaml +++ b/dts/bindings/clock/renesas,ra-cgc-pll.yaml @@ -1,9 +1,9 @@ # Copyright (c) 2024 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 -description: Renesas RA8 Clock Generation Circuit PLL Clock +description: Renesas RA Clock Generation Circuit PLL Clock -compatible: "renesas,ra8-cgc-pll" +compatible: "renesas,ra-cgc-pll" include: [clock-controller.yaml, base.yaml] @@ -18,10 +18,8 @@ properties: required: true type: array divp: - required: true type: int freqp: - required: true type: int divq: type: int diff --git a/dts/bindings/clock/renesas,ra8-cgc-subclk.yaml b/dts/bindings/clock/renesas,ra-cgc-subclk.yaml similarity index 88% rename from dts/bindings/clock/renesas,ra8-cgc-subclk.yaml rename to dts/bindings/clock/renesas,ra-cgc-subclk.yaml index 7ed083be7c1..afb98c5fea1 100644 --- a/dts/bindings/clock/renesas,ra8-cgc-subclk.yaml +++ b/dts/bindings/clock/renesas,ra-cgc-subclk.yaml @@ -1,9 +1,9 @@ # Copyright (c) 2024 Renesas Electronics Corporation # SPDX-License-Identifier: Apache-2.0 -description: Renesas RA8 Sub-Clock +description: Renesas RA Sub-Clock -compatible: "renesas,ra8-cgc-subclk" +compatible: "renesas,ra-cgc-subclk" include: fixed-clock.yaml diff --git a/soc/renesas/ra/ra6e1/Kconfig b/soc/renesas/ra/ra6e1/Kconfig index bc1ec71acc6..e67c9f66dc2 100644 --- a/soc/renesas/ra/ra6e1/Kconfig +++ b/soc/renesas/ra/ra6e1/Kconfig @@ -6,6 +6,7 @@ config SOC_SERIES_RA6E1 select CPU_CORTEX_M33 select CPU_HAS_ARM_MPU select HAS_RENESAS_RA_FSP + select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL select CPU_CORTEX_M_HAS_DWT select CPU_HAS_FPU select ARMV8_M_DSP diff --git a/soc/renesas/ra/ra6e1/soc.c b/soc/renesas/ra/ra6e1/soc.c index 700d108965b..5ca796f5bbe 100644 --- a/soc/renesas/ra/ra6e1/soc.c +++ b/soc/renesas/ra/ra6e1/soc.c @@ -38,6 +38,7 @@ static int renesas_ra6e1_init(void) uint32_t key; extern volatile uint16_t g_protect_counters[]; + for (uint32_t i = 0; i < 4; i++) { g_protect_counters[i] = 0; } @@ -64,7 +65,6 @@ static int renesas_ra6e1_init(void) SystemCoreClock = BSP_MOCO_HZ; g_protect_pfswe_counter = 0; - bsp_clock_init(); irq_unlock(key); diff --git a/soc/renesas/ra/ra6e2/Kconfig b/soc/renesas/ra/ra6e2/Kconfig index a662cf605e6..9ac1ba7dd42 100644 --- a/soc/renesas/ra/ra6e2/Kconfig +++ b/soc/renesas/ra/ra6e2/Kconfig @@ -6,6 +6,7 @@ config SOC_SERIES_RA6E2 select CPU_CORTEX_M33 select CPU_HAS_ARM_MPU select HAS_RENESAS_RA_FSP + select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL select CPU_CORTEX_M_HAS_DWT select CPU_HAS_FPU select ARMV8_M_DSP diff --git a/soc/renesas/ra/ra6e2/soc.c b/soc/renesas/ra/ra6e2/soc.c index 554cd63760c..2249db628e4 100644 --- a/soc/renesas/ra/ra6e2/soc.c +++ b/soc/renesas/ra/ra6e2/soc.c @@ -40,6 +40,7 @@ static int renesas_ra6e2_init(void) key = irq_lock(); extern volatile uint16_t g_protect_counters[]; + for (uint32_t i = 0; i < 4; i++) { g_protect_counters[i] = 0; } @@ -64,7 +65,6 @@ static int renesas_ra6e2_init(void) SystemCoreClock = BSP_MOCO_HZ; g_protect_pfswe_counter = 0; - bsp_clock_init(); irq_unlock(key); diff --git a/soc/renesas/ra/ra6m1/Kconfig b/soc/renesas/ra/ra6m1/Kconfig index c781d7751af..e2520fc4569 100644 --- a/soc/renesas/ra/ra6m1/Kconfig +++ b/soc/renesas/ra/ra6m1/Kconfig @@ -6,6 +6,7 @@ config SOC_SERIES_RA6M1 select CPU_CORTEX_M4 select CPU_HAS_ARM_MPU select HAS_RENESAS_RA_FSP + select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL select CPU_CORTEX_M_HAS_DWT select CPU_HAS_FPU select FPU diff --git a/soc/renesas/ra/ra6m1/soc.c b/soc/renesas/ra/ra6m1/soc.c index 9e9645b517c..d56bde197e6 100644 --- a/soc/renesas/ra/ra6m1/soc.c +++ b/soc/renesas/ra/ra6m1/soc.c @@ -41,7 +41,6 @@ static int renesas_ra6m1_init(void) SystemCoreClock = BSP_MOCO_HZ; g_protect_pfswe_counter = 0; - bsp_clock_init(); irq_unlock(key); diff --git a/soc/renesas/ra/ra6m2/Kconfig b/soc/renesas/ra/ra6m2/Kconfig index 44562acbf90..89c951a9db9 100644 --- a/soc/renesas/ra/ra6m2/Kconfig +++ b/soc/renesas/ra/ra6m2/Kconfig @@ -6,6 +6,7 @@ config SOC_SERIES_RA6M2 select CPU_CORTEX_M4 select CPU_HAS_ARM_MPU select HAS_RENESAS_RA_FSP + select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL select CPU_CORTEX_M_HAS_DWT select CPU_HAS_FPU select FPU diff --git a/soc/renesas/ra/ra6m2/soc.c b/soc/renesas/ra/ra6m2/soc.c index 85e5742ebfd..4b10f2123e6 100644 --- a/soc/renesas/ra/ra6m2/soc.c +++ b/soc/renesas/ra/ra6m2/soc.c @@ -41,7 +41,6 @@ static int renesas_ra6m2_init(void) SystemCoreClock = BSP_MOCO_HZ; g_protect_pfswe_counter = 0; - bsp_clock_init(); irq_unlock(key); diff --git a/soc/renesas/ra/ra6m3/Kconfig b/soc/renesas/ra/ra6m3/Kconfig index 061d7c5816c..c91e5284022 100644 --- a/soc/renesas/ra/ra6m3/Kconfig +++ b/soc/renesas/ra/ra6m3/Kconfig @@ -6,6 +6,7 @@ config SOC_SERIES_RA6M3 select CPU_CORTEX_M4 select CPU_HAS_ARM_MPU select HAS_RENESAS_RA_FSP + select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL select CPU_CORTEX_M_HAS_DWT select CPU_HAS_FPU select FPU diff --git a/soc/renesas/ra/ra6m3/soc.c b/soc/renesas/ra/ra6m3/soc.c index 13aadea27c7..b2d87b50f0a 100644 --- a/soc/renesas/ra/ra6m3/soc.c +++ b/soc/renesas/ra/ra6m3/soc.c @@ -41,7 +41,6 @@ static int renesas_ra6m3_init(void) SystemCoreClock = BSP_MOCO_HZ; g_protect_pfswe_counter = 0; - bsp_clock_init(); irq_unlock(key); diff --git a/soc/renesas/ra/ra6m5/Kconfig b/soc/renesas/ra/ra6m5/Kconfig index a02a4dba1e3..f7fdc083bc2 100644 --- a/soc/renesas/ra/ra6m5/Kconfig +++ b/soc/renesas/ra/ra6m5/Kconfig @@ -6,6 +6,7 @@ config SOC_SERIES_RA6M5 select CPU_CORTEX_M33 select CPU_HAS_ARM_MPU select HAS_RENESAS_RA_FSP + select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL select CPU_CORTEX_M_HAS_DWT select CPU_HAS_FPU select ARMV8_M_DSP diff --git a/soc/renesas/ra/ra6m5/soc.c b/soc/renesas/ra/ra6m5/soc.c index 4f9cab5d9f1..fda381f0f0d 100644 --- a/soc/renesas/ra/ra6m5/soc.c +++ b/soc/renesas/ra/ra6m5/soc.c @@ -40,6 +40,7 @@ static int renesas_ra6m5_init(void) key = irq_lock(); extern volatile uint16_t g_protect_counters[]; + for (uint32_t i = 0; i < 4; i++) { g_protect_counters[i] = 0; } @@ -64,7 +65,6 @@ static int renesas_ra6m5_init(void) SystemCoreClock = BSP_MOCO_HZ; g_protect_pfswe_counter = 0; - bsp_clock_init(); irq_unlock(key);