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drivers: timer: Move Dual Timer API to unified interface

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The CMSDK Dual Timer can be used as a timer or as a counter.
The unified interface proposed in #8340 unifies counter.h and rtc.h to
provide a common interface.

This patch modifies the timer implementation of the dual timer to
make it compliant with the new proposed interface.

Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2019-02-01 10:59:03 -06:00 • committed by Anas Nashif
commit 36427f8bbb
7 changed files with 68 additions and 250 deletions
Download patch file Download diff file Expand all files Collapse all files

7
boards/arm/mps2_an385/Kconfig.defconfig
View file

@ -57,13 +57,6 @@ config TIMER_TMR_CMSDK_APB_1
endif # TIMER_TMR_CMSDK_APB endif # TIMER_TMR_CMSDK_APB
if COUNTER_DTMR_CMSDK_APB
config COUNTER_DTMR_CMSDK_APB_0
default y
endif # COUNTER_DTMR_CMSDK_APB
if TIMER_DTMR_CMSDK_APB if TIMER_DTMR_CMSDK_APB
config TIMER_DTMR_CMSDK_APB_0 config TIMER_DTMR_CMSDK_APB_0

7
boards/arm/v2m_beetle/Kconfig.defconfig
View file

@ -66,13 +66,6 @@ config TIMER_TMR_CMSDK_APB_1
endif # TIMER_TMR_CMSDK_APB endif # TIMER_TMR_CMSDK_APB
if COUNTER_DTMR_CMSDK_APB
config COUNTER_DTMR_CMSDK_APB_0
default y
endif # COUNTER_DTMR_CMSDK_APB
if TIMER_DTMR_CMSDK_APB if TIMER_DTMR_CMSDK_APB
config TIMER_DTMR_CMSDK_APB_0 config TIMER_DTMR_CMSDK_APB_0

7
boards/arm/v2m_musca/Kconfig.defconfig
View file

@ -50,13 +50,6 @@ config TIMER_TMR_CMSDK_APB_1
endif # TIMER_TMR_CMSDK_APB endif # TIMER_TMR_CMSDK_APB
if COUNTER_DTMR_CMSDK_APB
config COUNTER_DTMR_CMSDK_APB_0
def_bool y
endif # COUNTER_DTMR_CMSDK_APB
if TIMER_DTMR_CMSDK_APB if TIMER_DTMR_CMSDK_APB
config TIMER_DTMR_CMSDK_APB_0 config TIMER_DTMR_CMSDK_APB_0

1
drivers/counter/CMakeLists.txt
View file

@ -3,7 +3,6 @@ zephyr_library()
zephyr_library_sources_ifdef(CONFIG_AON_COUNTER_QMSI counter_qmsi_aon.c) zephyr_library_sources_ifdef(CONFIG_AON_COUNTER_QMSI counter_qmsi_aon.c)
zephyr_library_sources_ifdef(CONFIG_AON_TIMER_QMSI counter_qmsi_aonpt.c) zephyr_library_sources_ifdef(CONFIG_AON_TIMER_QMSI counter_qmsi_aonpt.c)
zephyr_library_sources_ifdef(CONFIG_TIMER_TMR_CMSDK_APB timer_tmr_cmsdk_apb.c) zephyr_library_sources_ifdef(CONFIG_TIMER_TMR_CMSDK_APB timer_tmr_cmsdk_apb.c)
zephyr_library_sources_ifdef(CONFIG_COUNTER_DTMR_CMSDK_APB counter_dtmr_cmsdk_apb.c)
zephyr_library_sources_ifdef(CONFIG_TIMER_DTMR_CMSDK_APB timer_dtmr_cmsdk_apb.c) zephyr_library_sources_ifdef(CONFIG_TIMER_DTMR_CMSDK_APB timer_dtmr_cmsdk_apb.c)
zephyr_library_sources_ifdef(CONFIG_COUNTER_IMX_EPIT counter_imx_epit.c) zephyr_library_sources_ifdef(CONFIG_COUNTER_IMX_EPIT counter_imx_epit.c)
zephyr_library_sources_ifdef(CONFIG_COUNTER_MCUX_RTC counter_mcux_rtc.c) zephyr_library_sources_ifdef(CONFIG_COUNTER_MCUX_RTC counter_mcux_rtc.c)

32
drivers/counter/Kconfig.dtmr_cmsdk_apb
View file

@ -23,13 +23,6 @@ config TIMER_DTMR_CMSDK_APB_0
help help
Enable support for Timer 0. Enable support for Timer 0.
config TIMER_DTMR_CMSDK_APB_0_DEV_NAME
string "Timer 0 Device Name"
depends on TIMER_DTMR_CMSDK_APB_0
default "TIMER_0"
help
Specify the device name for Timer 0 driver.
config TIMER_DTMR_CMSDK_APB_0_IRQ_PRI config TIMER_DTMR_CMSDK_APB_0_IRQ_PRI
int "Interrupt Priority for Timer 0" int "Interrupt Priority for Timer 0"
depends on TIMER_DTMR_CMSDK_APB_0 depends on TIMER_DTMR_CMSDK_APB_0
@ -39,29 +32,4 @@ config TIMER_DTMR_CMSDK_APB_0_IRQ_PRI
endif # TIMER_DTMR_CMSDK_APB endif # TIMER_DTMR_CMSDK_APB
config COUNTER_DTMR_CMSDK_APB
bool "ARM CMSDK (Cortex-M System Design Kit) DTMR Counter driver"
help
The dualtimer (DTMR) present in the platform is used as a counter.
This option enables the support for the counter.
if COUNTER_DTMR_CMSDK_APB
# ---------- Counter 0 ----------
config COUNTER_DTMR_CMSDK_APB_0
bool "Counter 0 driver"
depends on !TIMER_DTMR_CMSDK_APB_0
help
Enable support for Counter 0.
config COUNTER_DTMR_CMSDK_APB_0_DEV_NAME
string "Counter 0 Device Name"
depends on COUNTER_DTMR_CMSDK_APB_0
default "COUNTER_0"
help
Specify the device name for Counter 0 driver.
endif # COUNTER_DTMR_CMSDK_APB
endif # SOC_FAMILY_ARM endif # SOC_FAMILY_ARM

120
drivers/counter/counter_dtmr_cmsdk_apb.c
View file

@ -1,120 +0,0 @@
/*
* Copyright (c) 2016 Linaro Limited.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <counter.h>
#include <device.h>
#include <errno.h>
#include <init.h>
#include <soc.h>
#include <clock_control/arm_clock_control.h>
#include "dualtimer_cmsdk_apb.h"
#define DUALTIMER_MAX_RELOAD 0xFFFFFFFF
struct counter_dtmr_cmsdk_apb_cfg {
volatile struct dualtimer_cmsdk_apb *dtimer;
/* Dualtimer Clock control in Active State */
const struct arm_clock_control_t dtimer_cc_as;
/* Dualtimer Clock control in Sleep State */
const struct arm_clock_control_t dtimer_cc_ss;
/* Dualtimer Clock control in Deep Sleep State */
const struct arm_clock_control_t dtimer_cc_dss;
};
static int counter_dtmr_cmsdk_apb_start(struct device *dev)
{
const struct counter_dtmr_cmsdk_apb_cfg * const cfg =
dev->config->config_info;
/* Set the dualtimer to Max reload */
cfg->dtimer->timer1load = DUALTIMER_MAX_RELOAD;
/* Enable the dualtimer in 32 bit mode */
cfg->dtimer->timer1ctrl = (DUALTIMER_CTRL_EN | DUALTIMER_CTRL_SIZE_32);
return 0;
}
static int counter_dtmr_cmsdk_apb_stop(struct device *dev)
{
const struct counter_dtmr_cmsdk_apb_cfg * const cfg =
dev->config->config_info;
/* Disable the dualtimer */
cfg->dtimer->timer1ctrl = 0x0;
return 0;
}
static u32_t counter_dtmr_cmsdk_apb_read(struct device *dev)
{
const struct counter_dtmr_cmsdk_apb_cfg * const cfg =
dev->config->config_info;
/* Return Counter Value */
u32_t value = 0U;
value = DUALTIMER_MAX_RELOAD - cfg->dtimer->timer1value;
return value;
}
static int counter_dtmr_cmsdk_apb_set_alarm(struct device *dev,
counter_callback_t callback,
u32_t count, void *user_data)
{
return -ENODEV;
}
static const struct counter_driver_api counter_dtmr_cmsdk_apb_api = {
.start = counter_dtmr_cmsdk_apb_start,
.stop = counter_dtmr_cmsdk_apb_stop,
.read = counter_dtmr_cmsdk_apb_read,
.set_alarm = counter_dtmr_cmsdk_apb_set_alarm,
};
static int counter_dtmr_cmsdk_apb_init(struct device *dev)
{
#ifdef CONFIG_CLOCK_CONTROL
/* Enable clock for subsystem */
struct device *clk =
device_get_binding(CONFIG_ARM_CLOCK_CONTROL_DEV_NAME);
const struct counter_dtmr_cmsdk_apb_cfg * const cfg =
dev->config->config_info;
#ifdef CONFIG_SOC_SERIES_BEETLE
clock_control_on(clk, (clock_control_subsys_t *) &cfg->dtimer_cc_as);
clock_control_on(clk, (clock_control_subsys_t *) &cfg->dtimer_cc_ss);
clock_control_on(clk, (clock_control_subsys_t *) &cfg->dtimer_cc_dss);
#endif /* CONFIG_SOC_SERIES_BEETLE */
#else
ARG_UNUSED(dev);
#endif /* CONFIG_CLOCK_CONTROL */
return 0;
}
/* COUNTER 0 */
#ifdef CONFIG_COUNTER_DTMR_CMSDK_APB_0
static const struct counter_dtmr_cmsdk_apb_cfg counter_dtmr_cmsdk_apb_cfg_0 = {
.dtimer = ((volatile struct dualtimer_cmsdk_apb *)DT_CMSDK_APB_DTIMER),
.dtimer_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE,
.device = DT_CMSDK_APB_DTIMER,},
.dtimer_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP,
.device = DT_CMSDK_APB_DTIMER,},
.dtimer_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP,
.device = DT_CMSDK_APB_DTIMER,},
};
DEVICE_AND_API_INIT(counter_dtmr_cmsdk_apb_0,
CONFIG_COUNTER_DTMR_CMSDK_APB_0_DEV_NAME,
counter_dtmr_cmsdk_apb_init, NULL,
&counter_dtmr_cmsdk_apb_cfg_0, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&counter_dtmr_cmsdk_apb_api);
#endif /* CONFIG_COUNTER_DTMR_CMSDK_APB_0 */

144
drivers/counter/timer_dtmr_cmsdk_apb.c
View file

@ -15,16 +15,8 @@
typedef void (*dtimer_config_func_t)(struct device *dev); typedef void (*dtimer_config_func_t)(struct device *dev);
static counter_callback_t user_cb; struct dtmr_cmsdk_apb_cfg {
struct counter_config_info info;
#define DUALTIMER_MAX_RELOAD 0xFFFFFFFF
enum dtimer_status_t {
DTIMER_DISABLED = 0,
DTIMER_ENABLED,
};
struct timer_dtmr_cmsdk_apb_cfg {
volatile struct dualtimer_cmsdk_apb *dtimer; volatile struct dualtimer_cmsdk_apb *dtimer;
dtimer_config_func_t dtimer_config_func; dtimer_config_func_t dtimer_config_func;
/* Dualtimer Clock control in Active State */ /* Dualtimer Clock control in Active State */
@ -35,78 +27,64 @@ struct timer_dtmr_cmsdk_apb_cfg {
const struct arm_clock_control_t dtimer_cc_dss; const struct arm_clock_control_t dtimer_cc_dss;
}; };
struct timer_dtmr_cmsdk_apb_dev_data { struct dtmr_cmsdk_apb_dev_data {
counter_top_callback_t top_callback;
void *top_user_data;
u32_t load; u32_t load;
enum dtimer_status_t status;
}; };
static int timer_dtmr_cmsdk_apb_start(struct device *dev) static int dtmr_cmsdk_apb_start(struct device *dev)
{ {
const struct timer_dtmr_cmsdk_apb_cfg * const cfg = const struct dtmr_cmsdk_apb_cfg * const cfg =
dev->config->config_info; dev->config->config_info;
struct timer_dtmr_cmsdk_apb_dev_data *data = dev->driver_data; struct dtmr_cmsdk_apb_dev_data *data = dev->driver_data;
/* Set the dualtimer to Max reload */ /* Set the timer reload to count */
cfg->dtimer->timer1load = DUALTIMER_MAX_RELOAD; cfg->dtimer->timer1load = data->load;
/* Enable the dualtimer in 32 bit mode */ /* Enable the dualtimer in 32 bit mode */
cfg->dtimer->timer1ctrl = (DUALTIMER_CTRL_EN | DUALTIMER_CTRL_SIZE_32); cfg->dtimer->timer1ctrl = (DUALTIMER_CTRL_EN | DUALTIMER_CTRL_SIZE_32);
/* Update the status */
data->status = DTIMER_ENABLED;
return 0; return 0;
} }
static int timer_dtmr_cmsdk_apb_stop(struct device *dev) static int dtmr_cmsdk_apb_stop(struct device *dev)
{ {
const struct timer_dtmr_cmsdk_apb_cfg * const cfg = const struct dtmr_cmsdk_apb_cfg * const cfg =
dev->config->config_info; dev->config->config_info;
struct timer_dtmr_cmsdk_apb_dev_data *data = dev->driver_data;
/* Disable the dualtimer */ /* Disable the dualtimer */
cfg->dtimer->timer1ctrl = 0x0; cfg->dtimer->timer1ctrl = 0x0;
/* Update the status */
data->status = DTIMER_DISABLED;
return 0; return 0;
} }
static u32_t timer_dtmr_cmsdk_apb_read(struct device *dev) static u32_t dtmr_cmsdk_apb_read(struct device *dev)
{ {
const struct timer_dtmr_cmsdk_apb_cfg * const cfg = const struct dtmr_cmsdk_apb_cfg * const cfg =
dev->config->config_info; dev->config->config_info;
struct timer_dtmr_cmsdk_apb_dev_data *data = dev->driver_data; struct dtmr_cmsdk_apb_dev_data *data = dev->driver_data;
/* Return Timer Value */ return data->load - cfg->dtimer->timer1value;
u32_t value = 0U;
value = data->load - cfg->dtimer->timer1value;
return value;
} }
static int timer_dtmr_cmsdk_apb_set_alarm(struct device *dev, static int dtmr_cmsdk_apb_set_top_value(struct device *dev,
counter_callback_t callback, u32_t ticks,
u32_t count, void *user_data) counter_top_callback_t callback,
void *user_data)
{ {
const struct timer_dtmr_cmsdk_apb_cfg * const cfg = const struct dtmr_cmsdk_apb_cfg * const cfg =
dev->config->config_info; dev->config->config_info;
struct timer_dtmr_cmsdk_apb_dev_data *data = dev->driver_data; struct dtmr_cmsdk_apb_dev_data *data = dev->driver_data;
if (data->status == DTIMER_DISABLED) { data->top_callback = callback;
return -ENOTSUP; data->top_user_data = user_data;
}
/* Set callback */
user_cb = callback;
/* Store the reload value */ /* Store the reload value */
data->load = count; data->load = ticks;
/* Set the timer to count */ /* Set the timer to count */
cfg->dtimer->timer1load = count; cfg->dtimer->timer1load = ticks;
/* Enable IRQ */ /* Enable IRQ */
cfg->dtimer->timer1ctrl |= (DUALTIMER_CTRL_INTEN cfg->dtimer->timer1ctrl |= (DUALTIMER_CTRL_INTEN
@ -115,39 +93,48 @@ static int timer_dtmr_cmsdk_apb_set_alarm(struct device *dev,
return 0; return 0;
} }
static u32_t timer_dtmr_cmsdk_apb_get_pending_int(struct device *dev) static u32_t dtmr_cmsdk_apb_get_top_value(struct device *dev)
{ {
const struct timer_dtmr_cmsdk_apb_cfg * const cfg = struct dtmr_cmsdk_apb_dev_data *data = dev->driver_data;
u32_t ticks = data->load;
return ticks;
}
static u32_t dtmr_cmsdk_apb_get_pending_int(struct device *dev)
{
const struct dtmr_cmsdk_apb_cfg * const cfg =
dev->config->config_info; dev->config->config_info;
return cfg->dtimer->timer1ris; return cfg->dtimer->timer1ris;
} }
static const struct counter_driver_api timer_dtmr_cmsdk_apb_api = { static const struct counter_driver_api dtmr_cmsdk_apb_api = {
.start = timer_dtmr_cmsdk_apb_start, .start = dtmr_cmsdk_apb_start,
.stop = timer_dtmr_cmsdk_apb_stop, .stop = dtmr_cmsdk_apb_stop,
.read = timer_dtmr_cmsdk_apb_read, .read = dtmr_cmsdk_apb_read,
.set_alarm = timer_dtmr_cmsdk_apb_set_alarm, .set_top_value = dtmr_cmsdk_apb_set_top_value,
.get_pending_int = timer_dtmr_cmsdk_apb_get_pending_int, .get_pending_int = dtmr_cmsdk_apb_get_pending_int,
.get_top_value = dtmr_cmsdk_apb_get_top_value,
}; };
static void timer_dtmr_cmsdk_apb_isr(void *arg) static void dtmr_cmsdk_apb_isr(void *arg)
{ {
struct device *dev = (struct device *)arg; struct device *dev = (struct device *)arg;
const struct timer_dtmr_cmsdk_apb_cfg * const cfg = struct dtmr_cmsdk_apb_dev_data *data = dev->driver_data;
const struct dtmr_cmsdk_apb_cfg * const cfg =
dev->config->config_info; dev->config->config_info;
cfg->dtimer->timer1intclr = DUALTIMER_INTCLR; cfg->dtimer->timer1intclr = DUALTIMER_INTCLR;
if (user_cb) { if (data->top_callback) {
/* user_data paramenter is not used by this driver */ data->top_callback(dev, data->top_user_data);
(*user_cb)(dev, NULL);
} }
} }
static int timer_dtmr_cmsdk_apb_init(struct device *dev) static int dtmr_cmsdk_apb_init(struct device *dev)
{ {
const struct timer_dtmr_cmsdk_apb_cfg * const cfg = const struct dtmr_cmsdk_apb_cfg * const cfg =
dev->config->config_info; dev->config->config_info;
#ifdef CONFIG_CLOCK_CONTROL #ifdef CONFIG_CLOCK_CONTROL
@ -171,7 +158,13 @@ static int timer_dtmr_cmsdk_apb_init(struct device *dev)
#ifdef CONFIG_TIMER_DTMR_CMSDK_APB_0 #ifdef CONFIG_TIMER_DTMR_CMSDK_APB_0
static void dtimer_cmsdk_apb_config_0(struct device *dev); static void dtimer_cmsdk_apb_config_0(struct device *dev);
static const struct timer_dtmr_cmsdk_apb_cfg timer_dtmr_cmsdk_apb_cfg_0 = { static const struct dtmr_cmsdk_apb_cfg dtmr_cmsdk_apb_cfg_0 = {
.info = {
.max_top_value = UINT32_MAX,
.freq = 24000000U,
.count_up = false,
.channels = 0U,
},
.dtimer = ((volatile struct dualtimer_cmsdk_apb *)DT_CMSDK_APB_DTIMER), .dtimer = ((volatile struct dualtimer_cmsdk_apb *)DT_CMSDK_APB_DTIMER),
.dtimer_config_func = dtimer_cmsdk_apb_config_0, .dtimer_config_func = dtimer_cmsdk_apb_config_0,
.dtimer_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE, .dtimer_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE,
@ -182,25 +175,24 @@ static const struct timer_dtmr_cmsdk_apb_cfg timer_dtmr_cmsdk_apb_cfg_0 = {
.device = DT_CMSDK_APB_DTIMER,}, .device = DT_CMSDK_APB_DTIMER,},
}; };
static struct timer_dtmr_cmsdk_apb_dev_data timer_dtmr_cmsdk_apb_dev_data_0 = { static struct dtmr_cmsdk_apb_dev_data dtmr_cmsdk_apb_dev_data_0 = {
.load = DUALTIMER_MAX_RELOAD, .load = UINT_MAX,
.status = DTIMER_DISABLED,
}; };
DEVICE_AND_API_INIT(timer_dtmr_cmsdk_apb_0, DEVICE_AND_API_INIT(dtmr_cmsdk_apb_0,
CONFIG_TIMER_DTMR_CMSDK_APB_0_DEV_NAME, DT_CMSDK_APB_DTIMER0_LABEL,
timer_dtmr_cmsdk_apb_init, dtmr_cmsdk_apb_init,
&timer_dtmr_cmsdk_apb_dev_data_0, &dtmr_cmsdk_apb_dev_data_0,
&timer_dtmr_cmsdk_apb_cfg_0, POST_KERNEL, &dtmr_cmsdk_apb_cfg_0, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&timer_dtmr_cmsdk_apb_api); &dtmr_cmsdk_apb_api);
static void dtimer_cmsdk_apb_config_0(struct device *dev) static void dtimer_cmsdk_apb_config_0(struct device *dev)
{ {
IRQ_CONNECT(DT_CMSDK_APB_DUALTIMER_IRQ, IRQ_CONNECT(DT_CMSDK_APB_DUALTIMER_IRQ,
CONFIG_TIMER_DTMR_CMSDK_APB_0_IRQ_PRI, CONFIG_TIMER_DTMR_CMSDK_APB_0_IRQ_PRI,
timer_dtmr_cmsdk_apb_isr, dtmr_cmsdk_apb_isr,
DEVICE_GET(timer_dtmr_cmsdk_apb_0), 0); DEVICE_GET(dtmr_cmsdk_apb_0), 0);
irq_enable(DT_CMSDK_APB_DUALTIMER_IRQ); irq_enable(DT_CMSDK_APB_DUALTIMER_IRQ);
} }
#endif /* CONFIG_TIMER_DTMR_CMSDK_APB_0 */ #endif /* CONFIG_TIMER_DTMR_CMSDK_APB_0 */