drivers: timer: Move Timer API to unified interface
The CMSDK Timer can be used as a timer or as a counter. The unified interface proposed in #8340 unifies counter.h and rtc.h to provide a common interface. This patch modifies the timer implementation of the single timer to make it compliant with the new proposed interface. Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org> Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
parent
3edafc2517
commit
6fca18de60
8 changed files with 87 additions and 314 deletions
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@ -47,16 +47,6 @@ endif # WATCHDOG
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if COUNTER
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if COUNTER_TMR_CMSDK_APB
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config COUNTER_TMR_CMSDK_APB_0
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default y
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config COUNTER_TMR_CMSDK_APB_1
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default y
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endif # COUNTER_TMR_CMSDK_APB
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if TIMER_TMR_CMSDK_APB
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config TIMER_TMR_CMSDK_APB_0
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@ -56,16 +56,6 @@ endif # WATCHDOG
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if COUNTER
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if COUNTER_TMR_CMSDK_APB
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config COUNTER_TMR_CMSDK_APB_0
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default y
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config COUNTER_TMR_CMSDK_APB_1
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default y
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endif # COUNTER_TMR_CMSDK_APB
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if TIMER_TMR_CMSDK_APB
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config TIMER_TMR_CMSDK_APB_0
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@ -40,16 +40,6 @@ endif # SERIAL
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if COUNTER
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if COUNTER_TMR_CMSDK_APB
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config COUNTER_TMR_CMSDK_APB_0
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def_bool y
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config COUNTER_TMR_CMSDK_APB_1
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def_bool y
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endif # COUNTER_TMR_CMSDK_APB
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if TIMER_TMR_CMSDK_APB
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config TIMER_TMR_CMSDK_APB_0
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@ -2,7 +2,6 @@ zephyr_library()
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zephyr_library_sources_ifdef(CONFIG_AON_COUNTER_QMSI counter_qmsi_aon.c)
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zephyr_library_sources_ifdef(CONFIG_AON_TIMER_QMSI counter_qmsi_aonpt.c)
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zephyr_library_sources_ifdef(CONFIG_COUNTER_TMR_CMSDK_APB counter_tmr_cmsdk_apb.c)
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zephyr_library_sources_ifdef(CONFIG_TIMER_TMR_CMSDK_APB timer_tmr_cmsdk_apb.c)
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zephyr_library_sources_ifdef(CONFIG_COUNTER_DTMR_CMSDK_APB counter_dtmr_cmsdk_apb.c)
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zephyr_library_sources_ifdef(CONFIG_TIMER_DTMR_CMSDK_APB timer_dtmr_cmsdk_apb.c)
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@ -23,13 +23,6 @@ config TIMER_TMR_CMSDK_APB_0
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help
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Enable support for Timer 0.
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config TIMER_TMR_CMSDK_APB_0_DEV_NAME
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string "Timer 0 Device Name"
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depends on TIMER_TMR_CMSDK_APB_0
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default "TIMER_0"
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help
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Specify the device name for Timer 0 driver.
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config TIMER_TMR_CMSDK_APB_0_IRQ_PRI
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int "Interrupt Priority for Timer 0"
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depends on TIMER_TMR_CMSDK_APB_0
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@ -44,13 +37,6 @@ config TIMER_TMR_CMSDK_APB_1
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help
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Enable support for Timer 1.
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config TIMER_TMR_CMSDK_APB_1_DEV_NAME
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string "Timer 1 Device Name"
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depends on TIMER_TMR_CMSDK_APB_1
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default "TIMER_1"
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help
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Specify the device name for Timer 1 driver.
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config TIMER_TMR_CMSDK_APB_1_IRQ_PRI
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int "Interrupt Priority for Timer 1"
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depends on TIMER_TMR_CMSDK_APB_1
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@ -60,44 +46,4 @@ config TIMER_TMR_CMSDK_APB_1_IRQ_PRI
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endif # TIMER_TMR_CMSDK_APB
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config COUNTER_TMR_CMSDK_APB
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bool "ARM CMSDK (Cortex-M System Design Kit) Counter driver"
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help
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The timers (TMR) present in the platform are used as counters.
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This option enables the support for the counters.
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if COUNTER_TMR_CMSDK_APB
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# ---------- Counter 0 ----------
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config COUNTER_TMR_CMSDK_APB_0
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bool "Counter 0 driver"
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depends on !TIMER_TMR_CMSDK_APB_0
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help
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Enable support for Counter 0.
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config COUNTER_TMR_CMSDK_APB_0_DEV_NAME
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string "Counter 0 Device Name"
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depends on COUNTER_TMR_CMSDK_APB_0
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default "COUNTER_0"
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help
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Specify the device name for Counter 0 driver.
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# ---------- Counter 1 ----------
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config COUNTER_TMR_CMSDK_APB_1
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bool "Counter 1 driver"
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depends on !TIMER_TMR_CMSDK_APB_1
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help
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Enable support for Counter 1.
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config COUNTER_TMR_CMSDK_APB_1_DEV_NAME
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string "Counter 1 Device Name"
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depends on COUNTER_TMR_CMSDK_APB_1
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default "COUNTER_1"
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help
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Specify the device name for Counter 1 driver.
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endif # COUNTER_TMR_CMSDK_APB
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endif # SOC_FAMILY_ARM
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@ -1,140 +0,0 @@
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/*
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* Copyright (c) 2016 Linaro Limited.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <counter.h>
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#include <device.h>
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#include <errno.h>
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#include <init.h>
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#include <soc.h>
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#include <clock_control/arm_clock_control.h>
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#include "timer_cmsdk_apb.h"
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#define TIMER_MAX_RELOAD 0xFFFFFFFF
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struct counter_tmr_cmsdk_apb_cfg {
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volatile struct timer_cmsdk_apb *timer;
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/* Timer Clock control in Active State */
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const struct arm_clock_control_t timer_cc_as;
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/* Timer Clock control in Sleep State */
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const struct arm_clock_control_t timer_cc_ss;
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/* Timer Clock control in Deep Sleep State */
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const struct arm_clock_control_t timer_cc_dss;
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};
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static int counter_tmr_cmsdk_apb_start(struct device *dev)
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{
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const struct counter_tmr_cmsdk_apb_cfg * const cfg =
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dev->config->config_info;
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/* Set the timer to Max reload */
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cfg->timer->reload = TIMER_MAX_RELOAD;
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/* Enable the timer */
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cfg->timer->ctrl = TIMER_CTRL_EN;
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return 0;
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}
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static int counter_tmr_cmsdk_apb_stop(struct device *dev)
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{
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const struct counter_tmr_cmsdk_apb_cfg * const cfg =
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dev->config->config_info;
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/* Disable the timer */
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cfg->timer->ctrl = 0x0;
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return 0;
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}
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static u32_t counter_tmr_cmsdk_apb_read(struct device *dev)
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{
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const struct counter_tmr_cmsdk_apb_cfg * const cfg =
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dev->config->config_info;
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/* Return Counter Value */
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u32_t value = 0U;
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value = TIMER_MAX_RELOAD - cfg->timer->value;
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return value;
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}
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static int counter_tmr_cmsdk_apb_set_alarm(struct device *dev,
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counter_callback_t callback,
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u32_t count, void *user_data)
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{
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return -ENODEV;
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}
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static const struct counter_driver_api counter_tmr_cmsdk_apb_api = {
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.start = counter_tmr_cmsdk_apb_start,
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.stop = counter_tmr_cmsdk_apb_stop,
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.read = counter_tmr_cmsdk_apb_read,
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.set_alarm = counter_tmr_cmsdk_apb_set_alarm,
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};
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static int counter_tmr_cmsdk_apb_init(struct device *dev)
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{
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#ifdef CONFIG_CLOCK_CONTROL
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/* Enable clock for subsystem */
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struct device *clk =
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device_get_binding(CONFIG_ARM_CLOCK_CONTROL_DEV_NAME);
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const struct counter_tmr_cmsdk_apb_cfg * const cfg =
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dev->config->config_info;
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#ifdef CONFIG_SOC_SERIES_BEETLE
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clock_control_on(clk, (clock_control_subsys_t *) &cfg->timer_cc_as);
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clock_control_on(clk, (clock_control_subsys_t *) &cfg->timer_cc_ss);
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clock_control_on(clk, (clock_control_subsys_t *) &cfg->timer_cc_dss);
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#endif /* CONFIG_SOC_SERIES_BEETLE */
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#else
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ARG_UNUSED(dev);
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#endif /* CONFIG_CLOCK_CONTROL */
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return 0;
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}
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/* COUNTER 0 */
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#ifdef CONFIG_COUNTER_TMR_CMSDK_APB_0
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static const struct counter_tmr_cmsdk_apb_cfg counter_tmr_cmsdk_apb_cfg_0 = {
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.timer = ((volatile struct timer_cmsdk_apb *)DT_CMSDK_APB_TIMER0),
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.timer_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE,
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.device = DT_CMSDK_APB_TIMER0,},
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.timer_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP,
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.device = DT_CMSDK_APB_TIMER0,},
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.timer_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP,
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.device = DT_CMSDK_APB_TIMER0,},
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};
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DEVICE_AND_API_INIT(counter_tmr_cmsdk_apb_0,
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CONFIG_COUNTER_TMR_CMSDK_APB_0_DEV_NAME,
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counter_tmr_cmsdk_apb_init, NULL,
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&counter_tmr_cmsdk_apb_cfg_0, POST_KERNEL,
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&counter_tmr_cmsdk_apb_api);
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#endif /* CONFIG_COUNTER_TMR_CMSDK_APB_0 */
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/* COUNTER 1 */
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#ifdef CONFIG_COUNTER_TMR_CMSDK_APB_1
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static const struct counter_tmr_cmsdk_apb_cfg counter_tmr_cmsdk_apb_cfg_1 = {
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.timer = ((volatile struct timer_cmsdk_apb *)DT_CMSDK_APB_TIMER1),
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.timer_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE,
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.device = DT_CMSDK_APB_TIMER1,},
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.timer_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP,
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.device = DT_CMSDK_APB_TIMER1,},
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.timer_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP,
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.device = DT_CMSDK_APB_TIMER1,},
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};
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DEVICE_AND_API_INIT(counter_tmr_cmsdk_apb_1,
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CONFIG_COUNTER_TMR_CMSDK_APB_1_DEV_NAME,
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counter_tmr_cmsdk_apb_init, NULL,
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&counter_tmr_cmsdk_apb_cfg_1, POST_KERNEL,
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&counter_tmr_cmsdk_apb_api);
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#endif /* CONFIG_COUNTER_TMR_CMSDK_APB_1 */
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@ -15,16 +15,8 @@
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typedef void (*timer_config_func_t)(struct device *dev);
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static counter_callback_t user_cb;
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#define TIMER_MAX_RELOAD 0xFFFFFFFF
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enum timer_status_t {
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TIMER_DISABLED = 0,
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TIMER_ENABLED,
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};
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struct timer_tmr_cmsdk_apb_cfg {
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struct tmr_cmsdk_apb_cfg {
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struct counter_config_info info;
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volatile struct timer_cmsdk_apb *timer;
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timer_config_func_t timer_config_func;
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/* Timer Clock control in Active State */
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const struct arm_clock_control_t timer_cc_dss;
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};
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struct timer_tmr_cmsdk_apb_dev_data {
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struct tmr_cmsdk_apb_dev_data {
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counter_top_callback_t top_callback;
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void *top_user_data;
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u32_t load;
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enum timer_status_t status;
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};
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static int timer_tmr_cmsdk_apb_start(struct device *dev)
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static int tmr_cmsdk_apb_start(struct device *dev)
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{
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const struct timer_tmr_cmsdk_apb_cfg * const cfg =
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const struct tmr_cmsdk_apb_cfg * const cfg =
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dev->config->config_info;
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struct timer_tmr_cmsdk_apb_dev_data *data = dev->driver_data;
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struct tmr_cmsdk_apb_dev_data *data = dev->driver_data;
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/* Set the timer to Max reload */
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cfg->timer->reload = TIMER_MAX_RELOAD;
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/* Set the timer reload to count */
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cfg->timer->reload = data->load;
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/* Enable the timer */
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cfg->timer->ctrl = TIMER_CTRL_EN;
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/* Update the status */
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data->status = TIMER_ENABLED;
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return 0;
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}
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static int timer_tmr_cmsdk_apb_stop(struct device *dev)
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static int tmr_cmsdk_apb_stop(struct device *dev)
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{
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const struct timer_tmr_cmsdk_apb_cfg * const cfg =
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const struct tmr_cmsdk_apb_cfg * const cfg =
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dev->config->config_info;
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struct timer_tmr_cmsdk_apb_dev_data *data = dev->driver_data;
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/* Disable the timer */
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cfg->timer->ctrl = 0x0;
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/* Update the status */
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data->status = TIMER_DISABLED;
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return 0;
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}
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static u32_t timer_tmr_cmsdk_apb_read(struct device *dev)
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static u32_t tmr_cmsdk_apb_read(struct device *dev)
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{
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const struct timer_tmr_cmsdk_apb_cfg * const cfg =
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const struct tmr_cmsdk_apb_cfg * const cfg =
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dev->config->config_info;
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struct timer_tmr_cmsdk_apb_dev_data *data = dev->driver_data;
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struct tmr_cmsdk_apb_dev_data *data = dev->driver_data;
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/* Return Counter Value */
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u32_t value = 0U;
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value = data->load - cfg->timer->value;
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return value;
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return data->load - cfg->timer->value;
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}
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static int timer_tmr_cmsdk_apb_set_alarm(struct device *dev,
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counter_callback_t callback,
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u32_t count, void *user_data)
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static int tmr_cmsdk_apb_set_top_value(struct device *dev,
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u32_t ticks,
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counter_top_callback_t callback,
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void *user_data)
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{
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const struct timer_tmr_cmsdk_apb_cfg * const cfg =
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const struct tmr_cmsdk_apb_cfg * const cfg =
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dev->config->config_info;
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struct timer_tmr_cmsdk_apb_dev_data *data = dev->driver_data;
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struct tmr_cmsdk_apb_dev_data *data = dev->driver_data;
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if (data->status == TIMER_DISABLED) {
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return -ENOTSUP;
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}
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/* Set callback */
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user_cb = callback;
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data->top_callback = callback;
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data->top_user_data = user_data;
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/* Store the reload value */
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data->load = count;
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data->load = ticks;
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/* Set value register to count */
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cfg->timer->value = count;
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cfg->timer->value = ticks;
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/* Set the timer reload to count */
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cfg->timer->reload = count;
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cfg->timer->reload = ticks;
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/* Enable IRQ */
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cfg->timer->ctrl |= TIMER_CTRL_IRQ_EN;
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@ -117,38 +95,48 @@ static int timer_tmr_cmsdk_apb_set_alarm(struct device *dev,
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return 0;
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}
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static u32_t timer_tmr_cmsdk_apb_get_pending_int(struct device *dev)
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static u32_t tmr_cmsdk_apb_get_top_value(struct device *dev)
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{
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const struct timer_tmr_cmsdk_apb_cfg * const cfg =
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struct tmr_cmsdk_apb_dev_data *data = dev->driver_data;
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u32_t ticks = data->load;
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return ticks;
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}
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static u32_t tmr_cmsdk_apb_get_pending_int(struct device *dev)
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{
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const struct tmr_cmsdk_apb_cfg * const cfg =
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dev->config->config_info;
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return cfg->timer->intstatus;
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}
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static const struct counter_driver_api timer_tmr_cmsdk_apb_api = {
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.start = timer_tmr_cmsdk_apb_start,
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.stop = timer_tmr_cmsdk_apb_stop,
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.read = timer_tmr_cmsdk_apb_read,
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.set_alarm = timer_tmr_cmsdk_apb_set_alarm,
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.get_pending_int = timer_tmr_cmsdk_apb_get_pending_int,
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static const struct counter_driver_api tmr_cmsdk_apb_api = {
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.start = tmr_cmsdk_apb_start,
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.stop = tmr_cmsdk_apb_stop,
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.read = tmr_cmsdk_apb_read,
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.set_top_value = tmr_cmsdk_apb_set_top_value,
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.get_pending_int = tmr_cmsdk_apb_get_pending_int,
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.get_top_value = tmr_cmsdk_apb_get_top_value,
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};
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static void timer_tmr_cmsdk_apb_isr(void *arg)
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static void tmr_cmsdk_apb_isr(void *arg)
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{
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struct device *dev = (struct device *)arg;
|
||||
const struct timer_tmr_cmsdk_apb_cfg * const cfg =
|
||||
struct tmr_cmsdk_apb_dev_data *data = dev->driver_data;
|
||||
const struct tmr_cmsdk_apb_cfg * const cfg =
|
||||
dev->config->config_info;
|
||||
|
||||
cfg->timer->intclear = TIMER_CTRL_INT_CLEAR;
|
||||
if (user_cb) {
|
||||
/* user_data paramenter is not used by this driver */
|
||||
(*user_cb)(dev, NULL);
|
||||
if (data->top_callback) {
|
||||
data->top_callback(dev, data->top_user_data);
|
||||
}
|
||||
}
|
||||
|
||||
static int timer_tmr_cmsdk_apb_init(struct device *dev)
|
||||
static int tmr_cmsdk_apb_init(struct device *dev)
|
||||
{
|
||||
const struct timer_tmr_cmsdk_apb_cfg * const cfg =
|
||||
const struct tmr_cmsdk_apb_cfg * const cfg =
|
||||
dev->config->config_info;
|
||||
|
||||
#ifdef CONFIG_CLOCK_CONTROL
|
||||
|
@ -172,7 +160,13 @@ static int timer_tmr_cmsdk_apb_init(struct device *dev)
|
|||
#ifdef CONFIG_TIMER_TMR_CMSDK_APB_0
|
||||
static void timer_cmsdk_apb_config_0(struct device *dev);
|
||||
|
||||
static const struct timer_tmr_cmsdk_apb_cfg timer_tmr_cmsdk_apb_cfg_0 = {
|
||||
static const struct tmr_cmsdk_apb_cfg tmr_cmsdk_apb_cfg_0 = {
|
||||
.info = {
|
||||
.max_top_value = UINT32_MAX,
|
||||
.freq = 24000000U,
|
||||
.count_up = false,
|
||||
.channels = 0U,
|
||||
},
|
||||
.timer = ((volatile struct timer_cmsdk_apb *)DT_CMSDK_APB_TIMER0),
|
||||
.timer_config_func = timer_cmsdk_apb_config_0,
|
||||
.timer_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE,
|
||||
|
@ -183,23 +177,22 @@ static const struct timer_tmr_cmsdk_apb_cfg timer_tmr_cmsdk_apb_cfg_0 = {
|
|||
.device = DT_CMSDK_APB_TIMER0,},
|
||||
};
|
||||
|
||||
static struct timer_tmr_cmsdk_apb_dev_data timer_tmr_cmsdk_apb_dev_data_0 = {
|
||||
.load = TIMER_MAX_RELOAD,
|
||||
.status = TIMER_DISABLED,
|
||||
static struct tmr_cmsdk_apb_dev_data tmr_cmsdk_apb_dev_data_0 = {
|
||||
.load = UINT32_MAX,
|
||||
};
|
||||
|
||||
DEVICE_AND_API_INIT(timer_tmr_cmsdk_apb_0,
|
||||
CONFIG_TIMER_TMR_CMSDK_APB_0_DEV_NAME,
|
||||
timer_tmr_cmsdk_apb_init, &timer_tmr_cmsdk_apb_dev_data_0,
|
||||
&timer_tmr_cmsdk_apb_cfg_0, POST_KERNEL,
|
||||
DEVICE_AND_API_INIT(tmr_cmsdk_apb_0,
|
||||
DT_CMSDK_APB_TIMER0_LABEL,
|
||||
tmr_cmsdk_apb_init, &tmr_cmsdk_apb_dev_data_0,
|
||||
&tmr_cmsdk_apb_cfg_0, POST_KERNEL,
|
||||
CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
|
||||
&timer_tmr_cmsdk_apb_api);
|
||||
&tmr_cmsdk_apb_api);
|
||||
|
||||
static void timer_cmsdk_apb_config_0(struct device *dev)
|
||||
{
|
||||
IRQ_CONNECT(DT_CMSDK_APB_TIMER_0_IRQ, CONFIG_TIMER_TMR_CMSDK_APB_0_IRQ_PRI,
|
||||
timer_tmr_cmsdk_apb_isr,
|
||||
DEVICE_GET(timer_tmr_cmsdk_apb_0), 0);
|
||||
tmr_cmsdk_apb_isr,
|
||||
DEVICE_GET(tmr_cmsdk_apb_0), 0);
|
||||
irq_enable(DT_CMSDK_APB_TIMER_0_IRQ);
|
||||
}
|
||||
#endif /* CONFIG_TIMER_TMR_CMSDK_APB_0 */
|
||||
|
@ -208,7 +201,13 @@ static void timer_cmsdk_apb_config_0(struct device *dev)
|
|||
#ifdef CONFIG_TIMER_TMR_CMSDK_APB_1
|
||||
static void timer_cmsdk_apb_config_1(struct device *dev);
|
||||
|
||||
static const struct timer_tmr_cmsdk_apb_cfg timer_tmr_cmsdk_apb_cfg_1 = {
|
||||
static const struct tmr_cmsdk_apb_cfg tmr_cmsdk_apb_cfg_1 = {
|
||||
.info = {
|
||||
.max_top_value = UINT32_MAX,
|
||||
.freq = 24000000U,
|
||||
.count_up = false,
|
||||
.channels = 0U,
|
||||
},
|
||||
.timer = ((volatile struct timer_cmsdk_apb *)DT_CMSDK_APB_TIMER1),
|
||||
.timer_config_func = timer_cmsdk_apb_config_1,
|
||||
.timer_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE,
|
||||
|
@ -219,23 +218,22 @@ static const struct timer_tmr_cmsdk_apb_cfg timer_tmr_cmsdk_apb_cfg_1 = {
|
|||
.device = DT_CMSDK_APB_TIMER1,},
|
||||
};
|
||||
|
||||
static struct timer_tmr_cmsdk_apb_dev_data timer_tmr_cmsdk_apb_dev_data_1 = {
|
||||
.load = TIMER_MAX_RELOAD,
|
||||
.status = TIMER_DISABLED,
|
||||
static struct tmr_cmsdk_apb_dev_data tmr_cmsdk_apb_dev_data_1 = {
|
||||
.load = UINT32_MAX,
|
||||
};
|
||||
|
||||
DEVICE_AND_API_INIT(timer_tmr_cmsdk_apb_1,
|
||||
CONFIG_TIMER_TMR_CMSDK_APB_1_DEV_NAME,
|
||||
timer_tmr_cmsdk_apb_init, &timer_tmr_cmsdk_apb_dev_data_1,
|
||||
&timer_tmr_cmsdk_apb_cfg_1, POST_KERNEL,
|
||||
DEVICE_AND_API_INIT(tmr_cmsdk_apb_1,
|
||||
DT_CMSDK_APB_TIMER1_LABEL,
|
||||
tmr_cmsdk_apb_init, &tmr_cmsdk_apb_dev_data_1,
|
||||
&tmr_cmsdk_apb_cfg_1, POST_KERNEL,
|
||||
CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
|
||||
&timer_tmr_cmsdk_apb_api);
|
||||
&tmr_cmsdk_apb_api);
|
||||
|
||||
static void timer_cmsdk_apb_config_1(struct device *dev)
|
||||
{
|
||||
IRQ_CONNECT(DT_CMSDK_APB_TIMER_1_IRQ, CONFIG_TIMER_TMR_CMSDK_APB_1_IRQ_PRI,
|
||||
timer_tmr_cmsdk_apb_isr,
|
||||
DEVICE_GET(timer_tmr_cmsdk_apb_0), 0);
|
||||
tmr_cmsdk_apb_isr,
|
||||
DEVICE_GET(tmr_cmsdk_apb_1), 0);
|
||||
irq_enable(DT_CMSDK_APB_TIMER_1_IRQ);
|
||||
}
|
||||
#endif /* CONFIG_TIMER_TMR_CMSDK_APB_1 */
|
||||
|
|
|
@ -25,13 +25,13 @@
|
|||
|
||||
#define AHB_CLK_BITS (CLK_BIT_GPIO0 | CLK_BIT_GPIO1)
|
||||
|
||||
#if defined(CONFIG_COUNTER_TMR_CMSDK_APB_0)
|
||||
#if defined(CONFIG_TIMER_TMR_CMSDK_APB_0)
|
||||
#define CLK_BIT_TIMER0 _BEETLE_TIMER0
|
||||
#else
|
||||
#define CLK_BIT_TIMER0 0
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_COUNTER_TMR_CMSDK_APB_1)
|
||||
#if defined(CONFIG_TIMER_TMR_CMSDK_APB_1)
|
||||
#define CLK_BIT_TIMER1 _BEETLE_TIMER1
|
||||
#else
|
||||
#define CLK_BIT_TIMER1 0
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue