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drivers: timer: Move Timer API to unified interface

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The CMSDK Timer can be used as a timer or as a counter.
The unified interface proposed in #8340 unifies counter.h and rtc.h to
provide a common interface.

This patch modifies the timer implementation of the single timer to
make it compliant with the new proposed interface.

Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2019-02-01 11:02:07 -06:00 • committed by Anas Nashif
commit 6fca18de60
8 changed files with 87 additions and 314 deletions
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10
boards/arm/mps2_an385/Kconfig.defconfig
View file

@ -47,16 +47,6 @@ endif # WATCHDOG
if COUNTER
if COUNTER_TMR_CMSDK_APB
config COUNTER_TMR_CMSDK_APB_0
default y
config COUNTER_TMR_CMSDK_APB_1
default y
endif # COUNTER_TMR_CMSDK_APB
if TIMER_TMR_CMSDK_APB
config TIMER_TMR_CMSDK_APB_0

10
boards/arm/v2m_beetle/Kconfig.defconfig
View file

@ -56,16 +56,6 @@ endif # WATCHDOG
if COUNTER
if COUNTER_TMR_CMSDK_APB
config COUNTER_TMR_CMSDK_APB_0
default y
config COUNTER_TMR_CMSDK_APB_1
default y
endif # COUNTER_TMR_CMSDK_APB
if TIMER_TMR_CMSDK_APB
config TIMER_TMR_CMSDK_APB_0

10
boards/arm/v2m_musca/Kconfig.defconfig
View file

@ -40,16 +40,6 @@ endif # SERIAL
if COUNTER
if COUNTER_TMR_CMSDK_APB
config COUNTER_TMR_CMSDK_APB_0
def_bool y
config COUNTER_TMR_CMSDK_APB_1
def_bool y
endif # COUNTER_TMR_CMSDK_APB
if TIMER_TMR_CMSDK_APB
config TIMER_TMR_CMSDK_APB_0

1
drivers/counter/CMakeLists.txt
View file

@ -2,7 +2,6 @@ zephyr_library()
zephyr_library_sources_ifdef(CONFIG_AON_COUNTER_QMSI counter_qmsi_aon.c)
zephyr_library_sources_ifdef(CONFIG_AON_TIMER_QMSI counter_qmsi_aonpt.c)
zephyr_library_sources_ifdef(CONFIG_COUNTER_TMR_CMSDK_APB counter_tmr_cmsdk_apb.c)
zephyr_library_sources_ifdef(CONFIG_TIMER_TMR_CMSDK_APB timer_tmr_cmsdk_apb.c)
zephyr_library_sources_ifdef(CONFIG_COUNTER_DTMR_CMSDK_APB counter_dtmr_cmsdk_apb.c)
zephyr_library_sources_ifdef(CONFIG_TIMER_DTMR_CMSDK_APB timer_dtmr_cmsdk_apb.c)

54
drivers/counter/Kconfig.tmr_cmsdk_apb
View file

@ -23,13 +23,6 @@ config TIMER_TMR_CMSDK_APB_0
help
Enable support for Timer 0.
config TIMER_TMR_CMSDK_APB_0_DEV_NAME
string "Timer 0 Device Name"
depends on TIMER_TMR_CMSDK_APB_0
default "TIMER_0"
help
Specify the device name for Timer 0 driver.
config TIMER_TMR_CMSDK_APB_0_IRQ_PRI
int "Interrupt Priority for Timer 0"
depends on TIMER_TMR_CMSDK_APB_0
@ -44,13 +37,6 @@ config TIMER_TMR_CMSDK_APB_1
help
Enable support for Timer 1.
config TIMER_TMR_CMSDK_APB_1_DEV_NAME
string "Timer 1 Device Name"
depends on TIMER_TMR_CMSDK_APB_1
default "TIMER_1"
help
Specify the device name for Timer 1 driver.
config TIMER_TMR_CMSDK_APB_1_IRQ_PRI
int "Interrupt Priority for Timer 1"
depends on TIMER_TMR_CMSDK_APB_1
@ -60,44 +46,4 @@ config TIMER_TMR_CMSDK_APB_1_IRQ_PRI
endif # TIMER_TMR_CMSDK_APB
config COUNTER_TMR_CMSDK_APB
bool "ARM CMSDK (Cortex-M System Design Kit) Counter driver"
help
The timers (TMR) present in the platform are used as counters.
This option enables the support for the counters.
if COUNTER_TMR_CMSDK_APB
# ---------- Counter 0 ----------
config COUNTER_TMR_CMSDK_APB_0
bool "Counter 0 driver"
depends on !TIMER_TMR_CMSDK_APB_0
help
Enable support for Counter 0.
config COUNTER_TMR_CMSDK_APB_0_DEV_NAME
string "Counter 0 Device Name"
depends on COUNTER_TMR_CMSDK_APB_0
default "COUNTER_0"
help
Specify the device name for Counter 0 driver.
# ---------- Counter 1 ----------
config COUNTER_TMR_CMSDK_APB_1
bool "Counter 1 driver"
depends on !TIMER_TMR_CMSDK_APB_1
help
Enable support for Counter 1.
config COUNTER_TMR_CMSDK_APB_1_DEV_NAME
string "Counter 1 Device Name"
depends on COUNTER_TMR_CMSDK_APB_1
default "COUNTER_1"
help
Specify the device name for Counter 1 driver.
endif # COUNTER_TMR_CMSDK_APB
endif # SOC_FAMILY_ARM

140
drivers/counter/counter_tmr_cmsdk_apb.c
View file

@ -1,140 +0,0 @@
/*
* Copyright (c) 2016 Linaro Limited.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <counter.h>
#include <device.h>
#include <errno.h>
#include <init.h>
#include <soc.h>
#include <clock_control/arm_clock_control.h>
#include "timer_cmsdk_apb.h"
#define TIMER_MAX_RELOAD 0xFFFFFFFF
struct counter_tmr_cmsdk_apb_cfg {
volatile struct timer_cmsdk_apb *timer;
/* Timer Clock control in Active State */
const struct arm_clock_control_t timer_cc_as;
/* Timer Clock control in Sleep State */
const struct arm_clock_control_t timer_cc_ss;
/* Timer Clock control in Deep Sleep State */
const struct arm_clock_control_t timer_cc_dss;
};
static int counter_tmr_cmsdk_apb_start(struct device *dev)
{
const struct counter_tmr_cmsdk_apb_cfg * const cfg =
dev->config->config_info;
/* Set the timer to Max reload */
cfg->timer->reload = TIMER_MAX_RELOAD;
/* Enable the timer */
cfg->timer->ctrl = TIMER_CTRL_EN;
return 0;
}
static int counter_tmr_cmsdk_apb_stop(struct device *dev)
{
const struct counter_tmr_cmsdk_apb_cfg * const cfg =
dev->config->config_info;
/* Disable the timer */
cfg->timer->ctrl = 0x0;
return 0;
}
static u32_t counter_tmr_cmsdk_apb_read(struct device *dev)
{
const struct counter_tmr_cmsdk_apb_cfg * const cfg =
dev->config->config_info;
/* Return Counter Value */
u32_t value = 0U;
value = TIMER_MAX_RELOAD - cfg->timer->value;
return value;
}
static int counter_tmr_cmsdk_apb_set_alarm(struct device *dev,
counter_callback_t callback,
u32_t count, void *user_data)
{
return -ENODEV;
}
static const struct counter_driver_api counter_tmr_cmsdk_apb_api = {
.start = counter_tmr_cmsdk_apb_start,
.stop = counter_tmr_cmsdk_apb_stop,
.read = counter_tmr_cmsdk_apb_read,
.set_alarm = counter_tmr_cmsdk_apb_set_alarm,
};
static int counter_tmr_cmsdk_apb_init(struct device *dev)
{
#ifdef CONFIG_CLOCK_CONTROL
/* Enable clock for subsystem */
struct device *clk =
device_get_binding(CONFIG_ARM_CLOCK_CONTROL_DEV_NAME);
const struct counter_tmr_cmsdk_apb_cfg * const cfg =
dev->config->config_info;
#ifdef CONFIG_SOC_SERIES_BEETLE
clock_control_on(clk, (clock_control_subsys_t *) &cfg->timer_cc_as);
clock_control_on(clk, (clock_control_subsys_t *) &cfg->timer_cc_ss);
clock_control_on(clk, (clock_control_subsys_t *) &cfg->timer_cc_dss);
#endif /* CONFIG_SOC_SERIES_BEETLE */
#else
ARG_UNUSED(dev);
#endif /* CONFIG_CLOCK_CONTROL */
return 0;
}
/* COUNTER 0 */
#ifdef CONFIG_COUNTER_TMR_CMSDK_APB_0
static const struct counter_tmr_cmsdk_apb_cfg counter_tmr_cmsdk_apb_cfg_0 = {
.timer = ((volatile struct timer_cmsdk_apb *)DT_CMSDK_APB_TIMER0),
.timer_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE,
.device = DT_CMSDK_APB_TIMER0,},
.timer_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP,
.device = DT_CMSDK_APB_TIMER0,},
.timer_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP,
.device = DT_CMSDK_APB_TIMER0,},
};
DEVICE_AND_API_INIT(counter_tmr_cmsdk_apb_0,
CONFIG_COUNTER_TMR_CMSDK_APB_0_DEV_NAME,
counter_tmr_cmsdk_apb_init, NULL,
&counter_tmr_cmsdk_apb_cfg_0, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&counter_tmr_cmsdk_apb_api);
#endif /* CONFIG_COUNTER_TMR_CMSDK_APB_0 */
/* COUNTER 1 */
#ifdef CONFIG_COUNTER_TMR_CMSDK_APB_1
static const struct counter_tmr_cmsdk_apb_cfg counter_tmr_cmsdk_apb_cfg_1 = {
.timer = ((volatile struct timer_cmsdk_apb *)DT_CMSDK_APB_TIMER1),
.timer_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE,
.device = DT_CMSDK_APB_TIMER1,},
.timer_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP,
.device = DT_CMSDK_APB_TIMER1,},
.timer_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP,
.device = DT_CMSDK_APB_TIMER1,},
};
DEVICE_AND_API_INIT(counter_tmr_cmsdk_apb_1,
CONFIG_COUNTER_TMR_CMSDK_APB_1_DEV_NAME,
counter_tmr_cmsdk_apb_init, NULL,
&counter_tmr_cmsdk_apb_cfg_1, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&counter_tmr_cmsdk_apb_api);
#endif /* CONFIG_COUNTER_TMR_CMSDK_APB_1 */

172
drivers/counter/timer_tmr_cmsdk_apb.c
View file

@ -15,16 +15,8 @@
typedef void (*timer_config_func_t)(struct device *dev);
static counter_callback_t user_cb;
#define TIMER_MAX_RELOAD 0xFFFFFFFF
enum timer_status_t {
TIMER_DISABLED = 0,
TIMER_ENABLED,
};
struct timer_tmr_cmsdk_apb_cfg {
struct tmr_cmsdk_apb_cfg {
struct counter_config_info info;
volatile struct timer_cmsdk_apb *timer;
timer_config_func_t timer_config_func;
/* Timer Clock control in Active State */
@ -35,81 +27,67 @@ struct timer_tmr_cmsdk_apb_cfg {
const struct arm_clock_control_t timer_cc_dss;
};
struct timer_tmr_cmsdk_apb_dev_data {
struct tmr_cmsdk_apb_dev_data {
counter_top_callback_t top_callback;
void *top_user_data;
u32_t load;
enum timer_status_t status;
};
static int timer_tmr_cmsdk_apb_start(struct device *dev)
static int tmr_cmsdk_apb_start(struct device *dev)
{
const struct timer_tmr_cmsdk_apb_cfg * const cfg =
const struct tmr_cmsdk_apb_cfg * const cfg =
dev->config->config_info;
struct timer_tmr_cmsdk_apb_dev_data *data = dev->driver_data;
struct tmr_cmsdk_apb_dev_data *data = dev->driver_data;
/* Set the timer to Max reload */
cfg->timer->reload = TIMER_MAX_RELOAD;
/* Set the timer reload to count */
cfg->timer->reload = data->load;
/* Enable the timer */
cfg->timer->ctrl = TIMER_CTRL_EN;
/* Update the status */
data->status = TIMER_ENABLED;
return 0;
}
static int timer_tmr_cmsdk_apb_stop(struct device *dev)
static int tmr_cmsdk_apb_stop(struct device *dev)
{
const struct timer_tmr_cmsdk_apb_cfg * const cfg =
const struct tmr_cmsdk_apb_cfg * const cfg =
dev->config->config_info;
struct timer_tmr_cmsdk_apb_dev_data *data = dev->driver_data;
/* Disable the timer */
cfg->timer->ctrl = 0x0;
/* Update the status */
data->status = TIMER_DISABLED;
return 0;
}
static u32_t timer_tmr_cmsdk_apb_read(struct device *dev)
static u32_t tmr_cmsdk_apb_read(struct device *dev)
{
const struct timer_tmr_cmsdk_apb_cfg * const cfg =
const struct tmr_cmsdk_apb_cfg * const cfg =
dev->config->config_info;
struct timer_tmr_cmsdk_apb_dev_data *data = dev->driver_data;
struct tmr_cmsdk_apb_dev_data *data = dev->driver_data;
/* Return Counter Value */
u32_t value = 0U;
value = data->load - cfg->timer->value;
return value;
return data->load - cfg->timer->value;
}
static int timer_tmr_cmsdk_apb_set_alarm(struct device *dev,
counter_callback_t callback,
u32_t count, void *user_data)
static int tmr_cmsdk_apb_set_top_value(struct device *dev,
u32_t ticks,
counter_top_callback_t callback,
void *user_data)
{
const struct timer_tmr_cmsdk_apb_cfg * const cfg =
const struct tmr_cmsdk_apb_cfg * const cfg =
dev->config->config_info;
struct timer_tmr_cmsdk_apb_dev_data *data = dev->driver_data;
struct tmr_cmsdk_apb_dev_data *data = dev->driver_data;
if (data->status == TIMER_DISABLED) {
return -ENOTSUP;
}
/* Set callback */
user_cb = callback;
data->top_callback = callback;
data->top_user_data = user_data;
/* Store the reload value */
data->load = count;
data->load = ticks;
/* Set value register to count */
cfg->timer->value = count;
cfg->timer->value = ticks;
/* Set the timer reload to count */
cfg->timer->reload = count;
cfg->timer->reload = ticks;
/* Enable IRQ */
cfg->timer->ctrl |= TIMER_CTRL_IRQ_EN;
@ -117,38 +95,48 @@ static int timer_tmr_cmsdk_apb_set_alarm(struct device *dev,
return 0;
}
static u32_t timer_tmr_cmsdk_apb_get_pending_int(struct device *dev)
static u32_t tmr_cmsdk_apb_get_top_value(struct device *dev)
{
const struct timer_tmr_cmsdk_apb_cfg * const cfg =
struct tmr_cmsdk_apb_dev_data *data = dev->driver_data;
u32_t ticks = data->load;
return ticks;
}
static u32_t tmr_cmsdk_apb_get_pending_int(struct device *dev)
{
const struct tmr_cmsdk_apb_cfg * const cfg =
dev->config->config_info;
return cfg->timer->intstatus;
}
static const struct counter_driver_api timer_tmr_cmsdk_apb_api = {
.start = timer_tmr_cmsdk_apb_start,
.stop = timer_tmr_cmsdk_apb_stop,
.read = timer_tmr_cmsdk_apb_read,
.set_alarm = timer_tmr_cmsdk_apb_set_alarm,
.get_pending_int = timer_tmr_cmsdk_apb_get_pending_int,
static const struct counter_driver_api tmr_cmsdk_apb_api = {
.start = tmr_cmsdk_apb_start,
.stop = tmr_cmsdk_apb_stop,
.read = tmr_cmsdk_apb_read,
.set_top_value = tmr_cmsdk_apb_set_top_value,
.get_pending_int = tmr_cmsdk_apb_get_pending_int,
.get_top_value = tmr_cmsdk_apb_get_top_value,
};
static void timer_tmr_cmsdk_apb_isr(void *arg)
static void tmr_cmsdk_apb_isr(void *arg)
{
struct device *dev = (struct device *)arg;
const struct timer_tmr_cmsdk_apb_cfg * const cfg =
struct tmr_cmsdk_apb_dev_data *data = dev->driver_data;
const struct tmr_cmsdk_apb_cfg * const cfg =
dev->config->config_info;
cfg->timer->intclear = TIMER_CTRL_INT_CLEAR;
if (user_cb) {
/* user_data paramenter is not used by this driver */
(*user_cb)(dev, NULL);
if (data->top_callback) {
data->top_callback(dev, data->top_user_data);
}
}
static int timer_tmr_cmsdk_apb_init(struct device *dev)
static int tmr_cmsdk_apb_init(struct device *dev)
{
const struct timer_tmr_cmsdk_apb_cfg * const cfg =
const struct tmr_cmsdk_apb_cfg * const cfg =
dev->config->config_info;
#ifdef CONFIG_CLOCK_CONTROL
@ -172,7 +160,13 @@ static int timer_tmr_cmsdk_apb_init(struct device *dev)
#ifdef CONFIG_TIMER_TMR_CMSDK_APB_0
static void timer_cmsdk_apb_config_0(struct device *dev);
static const struct timer_tmr_cmsdk_apb_cfg timer_tmr_cmsdk_apb_cfg_0 = {
static const struct tmr_cmsdk_apb_cfg tmr_cmsdk_apb_cfg_0 = {
.info = {
.max_top_value = UINT32_MAX,
.freq = 24000000U,
.count_up = false,
.channels = 0U,
},
.timer = ((volatile struct timer_cmsdk_apb *)DT_CMSDK_APB_TIMER0),
.timer_config_func = timer_cmsdk_apb_config_0,
.timer_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE,
@ -183,23 +177,22 @@ static const struct timer_tmr_cmsdk_apb_cfg timer_tmr_cmsdk_apb_cfg_0 = {
.device = DT_CMSDK_APB_TIMER0,},
};
static struct timer_tmr_cmsdk_apb_dev_data timer_tmr_cmsdk_apb_dev_data_0 = {
.load = TIMER_MAX_RELOAD,
.status = TIMER_DISABLED,
static struct tmr_cmsdk_apb_dev_data tmr_cmsdk_apb_dev_data_0 = {
.load = UINT32_MAX,
};
DEVICE_AND_API_INIT(timer_tmr_cmsdk_apb_0,
CONFIG_TIMER_TMR_CMSDK_APB_0_DEV_NAME,
timer_tmr_cmsdk_apb_init, &timer_tmr_cmsdk_apb_dev_data_0,
&timer_tmr_cmsdk_apb_cfg_0, POST_KERNEL,
DEVICE_AND_API_INIT(tmr_cmsdk_apb_0,
DT_CMSDK_APB_TIMER0_LABEL,
tmr_cmsdk_apb_init, &tmr_cmsdk_apb_dev_data_0,
&tmr_cmsdk_apb_cfg_0, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&timer_tmr_cmsdk_apb_api);
&tmr_cmsdk_apb_api);
static void timer_cmsdk_apb_config_0(struct device *dev)
{
IRQ_CONNECT(DT_CMSDK_APB_TIMER_0_IRQ, CONFIG_TIMER_TMR_CMSDK_APB_0_IRQ_PRI,
timer_tmr_cmsdk_apb_isr,
DEVICE_GET(timer_tmr_cmsdk_apb_0), 0);
tmr_cmsdk_apb_isr,
DEVICE_GET(tmr_cmsdk_apb_0), 0);
irq_enable(DT_CMSDK_APB_TIMER_0_IRQ);
}
#endif /* CONFIG_TIMER_TMR_CMSDK_APB_0 */
@ -208,7 +201,13 @@ static void timer_cmsdk_apb_config_0(struct device *dev)
#ifdef CONFIG_TIMER_TMR_CMSDK_APB_1
static void timer_cmsdk_apb_config_1(struct device *dev);
static const struct timer_tmr_cmsdk_apb_cfg timer_tmr_cmsdk_apb_cfg_1 = {
static const struct tmr_cmsdk_apb_cfg tmr_cmsdk_apb_cfg_1 = {
.info = {
.max_top_value = UINT32_MAX,
.freq = 24000000U,
.count_up = false,
.channels = 0U,
},
.timer = ((volatile struct timer_cmsdk_apb *)DT_CMSDK_APB_TIMER1),
.timer_config_func = timer_cmsdk_apb_config_1,
.timer_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE,
@ -219,23 +218,22 @@ static const struct timer_tmr_cmsdk_apb_cfg timer_tmr_cmsdk_apb_cfg_1 = {
.device = DT_CMSDK_APB_TIMER1,},
};
static struct timer_tmr_cmsdk_apb_dev_data timer_tmr_cmsdk_apb_dev_data_1 = {
.load = TIMER_MAX_RELOAD,
.status = TIMER_DISABLED,
static struct tmr_cmsdk_apb_dev_data tmr_cmsdk_apb_dev_data_1 = {
.load = UINT32_MAX,
};
DEVICE_AND_API_INIT(timer_tmr_cmsdk_apb_1,
CONFIG_TIMER_TMR_CMSDK_APB_1_DEV_NAME,
timer_tmr_cmsdk_apb_init, &timer_tmr_cmsdk_apb_dev_data_1,
&timer_tmr_cmsdk_apb_cfg_1, POST_KERNEL,
DEVICE_AND_API_INIT(tmr_cmsdk_apb_1,
DT_CMSDK_APB_TIMER1_LABEL,
tmr_cmsdk_apb_init, &tmr_cmsdk_apb_dev_data_1,
&tmr_cmsdk_apb_cfg_1, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&timer_tmr_cmsdk_apb_api);
&tmr_cmsdk_apb_api);
static void timer_cmsdk_apb_config_1(struct device *dev)
{
IRQ_CONNECT(DT_CMSDK_APB_TIMER_1_IRQ, CONFIG_TIMER_TMR_CMSDK_APB_1_IRQ_PRI,
timer_tmr_cmsdk_apb_isr,
DEVICE_GET(timer_tmr_cmsdk_apb_0), 0);
tmr_cmsdk_apb_isr,
DEVICE_GET(tmr_cmsdk_apb_1), 0);
irq_enable(DT_CMSDK_APB_TIMER_1_IRQ);
}
#endif /* CONFIG_TIMER_TMR_CMSDK_APB_1 */

4
soc/arm/arm/beetle/power.c
View file

@ -25,13 +25,13 @@
#define AHB_CLK_BITS (CLK_BIT_GPIO0 | CLK_BIT_GPIO1)
#if defined(CONFIG_COUNTER_TMR_CMSDK_APB_0)
#if defined(CONFIG_TIMER_TMR_CMSDK_APB_0)
#define CLK_BIT_TIMER0 _BEETLE_TIMER0
#else
#define CLK_BIT_TIMER0 0
#endif
#if defined(CONFIG_COUNTER_TMR_CMSDK_APB_1)
#if defined(CONFIG_TIMER_TMR_CMSDK_APB_1)
#define CLK_BIT_TIMER1 _BEETLE_TIMER1
#else
#define CLK_BIT_TIMER1 0