arm/arm64: Make ARM64 a standalone architecture

Split ARM and ARM64 architectures.

Details:

- CONFIG_ARM64 is decoupled from CONFIG_ARM (not a subset anymore)
- Arch and include AArch64 files are in a dedicated directory
  (arch/arm64 and include/arch/arm64)
- AArch64 boards and SoC are moved to soc/arm64 and boards/arm64
- AArch64-specific DTS files are moved to dts/arm64
- The A72 support for the bcm_vk/viper board is moved in the
  boards/bcm_vk/viper directory

Signed-off-by: Carlo Caione <ccaione@baylibre.com>

arch/Kconfig

@@ -32,11 +32,23 @@ config ARM
 	select HAS_DTS
 	# FIXME: current state of the code for all ARM requires this, but
 	# is really only necessary for Cortex-M with ARM MPU!
-	select GEN_PRIV_STACKS if !ARM64
+	select GEN_PRIV_STACKS
-	select ARCH_HAS_THREAD_LOCAL_STORAGE if ARM64 || CPU_CORTEX_R || CPU_CORTEX_M
+	select ARCH_HAS_THREAD_LOCAL_STORAGE if CPU_CORTEX_R || CPU_CORTEX_M
 	help
 	  ARM architecture
 
+config ARM64
+	bool
+	select ARCH_IS_SET
+	select 64BIT
+	select HAS_DTS
+	select HAS_ARM_SMCCC
+	select ARCH_HAS_THREAD_LOCAL_STORAGE
+	select USE_SWITCH
+	select USE_SWITCH_SUPPORTED
+	help
+	  ARM64 (AArch64) architecture
+
 config SPARC
 	bool
 	select ARCH_IS_SET
@@ -162,14 +174,14 @@ config SRAM_BASE_ADDRESS
 	  /chosen/zephyr,sram in devicetree. The user should generally avoid
 	  changing it via menuconfig or in configuration files.
 
-if ARC || ARM || NIOS2 || X86
+if ARC || ARM || ARM64 || NIOS2 || X86
 
 # Workaround for not being able to have commas in macro arguments
 DT_CHOSEN_Z_FLASH := zephyr,flash
 
 config FLASH_SIZE
 	int "Flash Size in kB"
-	default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) if (XIP && ARM) || !ARM
+	default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) if (XIP && (ARM ||ARM64)) || !ARM
 	help
 	  This option specifies the size of the flash in kB.  It is normally set by
 	  the board's defconfig file and the user should generally avoid modifying
@@ -177,13 +189,13 @@ config FLASH_SIZE
 
 config FLASH_BASE_ADDRESS
 	hex "Flash Base Address"
-	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) if (XIP && ARM) || !ARM
+	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) if (XIP && (ARM || ARM64)) || !ARM
 	help
 	  This option specifies the base address of the flash on the board. It is
 	  normally set by the board's defconfig file and the user should generally
 	  avoid modifying it via the menu configuration.
 
-endif # ARM || ARC || NIOS2 || X86
+endif # ARM || ARM64 || ARC || NIOS2 || X86
 
 if ARCH_HAS_TRUSTED_EXECUTION
 

arch/arm/CMakeLists.txt

@@ -1,11 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-if(CONFIG_ARM64)
+set_property(GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT elf32-littlearm)
-  set_property(GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT elf64-littleaarch64)
 
-  add_subdirectory(core/aarch64)
+add_subdirectory(core/aarch32)
-else()
-  set_property(GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT elf32-littlearm)
-
-  add_subdirectory(core/aarch32)
-endif()

arch/arm/Kconfig

@@ -9,10 +9,6 @@ menu "ARM Options"
 config ARCH
 	default "arm"
 
-config ARM64
-	bool
-	select 64BIT
-
 config CPU_CORTEX
 	bool
 	help
@@ -38,18 +34,6 @@ config ARM_CUSTOM_INTERRUPT_CONTROLLER
 	       family cores. The Cortex-M family cores are always equipped with
 	       the ARM Nested Vectored Interrupt Controller (NVIC).
 
-config HAS_ARM_SMCCC
-	bool
-	help
-	  Include support for the Secure Monitor Call (SMC) and Hypervisor
-	  Call (HVC) instructions on Armv7 and above architectures.
-
-if !ARM64
 rsource "core/aarch32/Kconfig"
-endif
-
-if ARM64
-rsource "core/aarch64/Kconfig"
-endif
 
 endmenu

arch/arm/core/offsets/offsets.c

@@ -6,10 +6,6 @@
 
 #include <gen_offset.h>
 
-#if defined(CONFIG_ARM64)
-#include "offsets_aarch64.c"
-#else
 #include "offsets_aarch32.c"
-#endif
 
 GEN_ABS_SYM_END

arch/arm/include/kernel_arch_data.h

@@ -30,8 +30,6 @@
 #elif defined(CONFIG_CPU_CORTEX_R)
 #include <aarch32/cortex_a_r/stack.h>
 #include <aarch32/cortex_a_r/exc.h>
-#elif defined(CONFIG_CPU_CORTEX_A)
-#include <aarch64/exc.h>
 #endif
 
 #ifndef _ASMLANGUAGE

arch/arm/include/kernel_arch_func.h

@@ -7,10 +7,6 @@
 #ifndef ZEPHYR_ARCH_ARM_INCLUDE_KERNEL_ARCH_FUNC_H_
 #define ZEPHYR_ARCH_ARM_INCLUDE_KERNEL_ARCH_FUNC_H_
 
-#if defined(CONFIG_ARM64)
-#include <aarch64/kernel_arch_func.h>
-#else
 #include <aarch32/kernel_arch_func.h>
-#endif
 
 #endif /* ZEPHYR_ARCH_ARM_INCLUDE_KERNEL_ARCH_FUNC_H_ */

arch/arm/include/offsets_short_arch.h

@@ -7,10 +7,6 @@
 #ifndef ZEPHYR_ARCH_ARM_INCLUDE_OFFSETS_SHORT_ARCH_H_
 #define ZEPHYR_ARCH_ARM_INCLUDE_OFFSETS_SHORT_ARCH_H_
 
-#if defined(CONFIG_ARM64)
-#include <aarch64/offsets_short_arch.h>
-#else
 #include <aarch32/offsets_short_arch.h>
-#endif
 
 #endif /* ZEPHYR_ARCH_ARM_INCLUDE_OFFSETS_SHORT_ARCH_H_ */

arch/arm64/CMakeLists.txt

@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: Apache-2.0
+
+set_property(GLOBAL PROPERTY PROPERTY_OUTPUT_FORMAT elf64-littleaarch64)
+
+add_subdirectory(core)

arch/arm64/Kconfig

@@ -0,0 +1,34 @@
+# ARM64 architecture configuration options
+
+# Copyright (c) 2014-2015 Wind River Systems, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+menu "ARM64 Options"
+	depends on ARM64
+
+config ARCH
+	default "arm64"
+
+config CPU_CORTEX
+	bool
+	help
+	  This option signifies the use of a CPU of the Cortex family.
+
+config ARM_CUSTOM_INTERRUPT_CONTROLLER
+	bool
+	help
+	  This option indicates that the ARM CPU is connected to a custom (i.e.
+	  non-GIC) interrupt controller.
+
+	  A number of Cortex-A and Cortex-R cores (Cortex-A5, Cortex-R4/5, ...)
+	  allow interfacing to a custom external interrupt controller and this
+	  option must be selected when such cores are connected to an interrupt
+	  controller that is not the ARM Generic Interrupt Controller (GIC).
+
+	  When this option is selected, the architecture interrupt control
+	  functions are mapped to the SoC interrupt control interface, which is
+	  implemented at the SoC level.
+
+rsource "core/Kconfig"
+
+endmenu

arch/arm64/core/CMakeLists.txt

@@ -23,7 +23,7 @@ zephyr_library_sources(
 zephyr_library_sources_ifdef(CONFIG_USERSPACE userspace.S)
 zephyr_library_sources_ifdef(CONFIG_GEN_SW_ISR_TABLE isr_wrapper.S)
 zephyr_library_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c)
-zephyr_library_sources_ifdef(CONFIG_THREAD_LOCAL_STORAGE ../common/tls.c)
+zephyr_library_sources_ifdef(CONFIG_THREAD_LOCAL_STORAGE tls.c)
 zephyr_library_sources_ifdef(CONFIG_HAS_ARM_SMCCC smccc-call.S)
 zephyr_library_sources_ifdef(CONFIG_AARCH64_IMAGE_HEADER header.S)
 

arch/arm64/core/Kconfig

@@ -7,9 +7,6 @@ config CPU_CORTEX_A
 	bool
 	select CPU_CORTEX
 	select HAS_FLASH_LOAD_OFFSET
-	select USE_SWITCH
-	select USE_SWITCH_SUPPORTED
-	select HAS_ARM_SMCCC
 	select SCHED_IPI_SUPPORTED if SMP
 	help
 	  This option signifies the use of a CPU of the Cortex-A family.
@@ -28,6 +25,12 @@ config CPU_CORTEX_A72
 	help
 	  This option signifies the use of a Cortex-A72 CPU
 
+config HAS_ARM_SMCCC
+	bool
+	help
+	  Include support for the Secure Monitor Call (SMC) and Hypervisor
+	  Call (HVC) instructions on Armv7 and above architectures.
+
 config NUM_IRQS
 	int
 

arch/arm64/core/irq_manage.c

@@ -29,7 +29,7 @@ void z_arm64_fatal_error(unsigned int reason, z_arch_esf_t *esf);
  * When a custom interrupt controller is used (i.e.
  * CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER is enabled), the architecture
  * interrupt control functions are mapped to the SoC layer in
- * `include/arch/arm/aarch64/irq.h`.
+ * `include/arch/arm64/irq.h`.
  */
 
 void arch_irq_enable(unsigned int irq)

arch/arm64/core/irq_offload.c

@@ -11,7 +11,7 @@
 
 #include <kernel.h>
 #include <irq_offload.h>
-#include <aarch64/exc.h>
+#include <exc.h>
 
 volatile irq_offload_routine_t offload_routine;
 static const void *offload_param;

arch/arm64/core/mmu/arm_mmu.c

@@ -14,9 +14,9 @@
 #include <kernel_arch_interface.h>
 #include <kernel_internal.h>
 #include <logging/log.h>
-#include <arch/arm/aarch64/cpu.h>
+#include <arch/arm64/cpu.h>
-#include <arch/arm/aarch64/lib_helpers.h>
+#include <arch/arm64/lib_helpers.h>
-#include <arch/arm/aarch64/arm_mmu.h>
+#include <arch/arm64/arm_mmu.h>
 #include <linker/linker-defs.h>
 #include <spinlock.h>
 #include <sys/util.h>

arch/arm64/core/offsets/offsets.c

@@ -25,6 +25,7 @@
 #ifndef _ARM_OFFSETS_INC_
 #define _ARM_OFFSETS_INC_
 
+#include <gen_offset.h>
 #include <kernel.h>
 #include <kernel_arch_data.h>
 #include <kernel_offsets.h>
@@ -61,7 +62,7 @@ GEN_ABSOLUTE_SYM(___esf_t_SIZEOF, sizeof(_esf_t));
 
 #ifdef CONFIG_HAS_ARM_SMCCC
 
-#include <arch/arm/arm-smccc.h>
+#include <arch/arm64/arm-smccc.h>
 
 GEN_NAMED_OFFSET_SYM(arm_smccc_res_t, a0, a0_a1);
 GEN_NAMED_OFFSET_SYM(arm_smccc_res_t, a2, a2_a3);
@@ -70,4 +71,6 @@ GEN_NAMED_OFFSET_SYM(arm_smccc_res_t, a6, a6_a7);
 
 #endif /* CONFIG_HAS_ARM_SMCCC */
 
+GEN_ABS_SYM_END
+
 #endif /* _ARM_OFFSETS_INC_ */

arch/arm64/core/smp.c

@@ -17,7 +17,7 @@
 #include <ksched.h>
 #include <soc.h>
 #include <init.h>
-#include <arch/arm/aarch64/arm_mmu.h>
+#include <arch/arm64/arm_mmu.h>
 #include <arch/cpu.h>
 #include <drivers/interrupt_controller/gic.h>
 #include <drivers/pm_cpu_ops.h>

arch/arm64/core/tls.c

@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2020 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <kernel.h>
+#include <kernel_structs.h>
+#include <kernel_internal.h>
+#include <kernel_tls.h>
+#include <app_memory/app_memdomain.h>
+#include <sys/util.h>
+
+size_t arch_tls_stack_setup(struct k_thread *new_thread, char *stack_ptr)
+{
+	/*
+	 * TLS area for ARM has some data fields following by
+	 * thread data and bss. These fields are supposed to be
+	 * used by toolchain and OS TLS code to aid in locating
+	 * the TLS data/bss. Zephyr currently has no use for
+	 * this so we can simply skip these. However, since GCC
+	 * is generating code assuming these fields are there,
+	 * we simply skip them when setting the TLS pointer.
+	 */
+
+	/*
+	 * Since we are populating things backwards,
+	 * setup the TLS data/bss area first.
+	 */
+	stack_ptr -= z_tls_data_size();
+	z_tls_copy(stack_ptr);
+
+	/* Skip two pointers due to toolchain */
+	stack_ptr -= sizeof(uintptr_t) * 2;
+
+	/*
+	 * Set thread TLS pointer which is used in
+	 * context switch to point to TLS area.
+	 */
+	new_thread->tls = POINTER_TO_UINT(stack_ptr);
+
+	return (z_tls_data_size() + (sizeof(uintptr_t) * 2));
+}

arch/arm64/include/kernel_arch_data.h

@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2013-2016 Wind River Systems, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Private kernel definitions (ARM)
+ *
+ * This file contains private kernel structures definitions and various
+ * other definitions for the ARM Cortex-A/R/M processor architecture family.
+ *
+ * This file is also included by assembly language files which must #define
+ * _ASMLANGUAGE before including this header file.  Note that kernel
+ * assembly source files obtains structure offset values via "absolute symbols"
+ * in the offsets.o module.
+ */
+
+#ifndef ZEPHYR_ARCH_ARM_INCLUDE_KERNEL_ARCH_DATA_H_
+#define ZEPHYR_ARCH_ARM_INCLUDE_KERNEL_ARCH_DATA_H_
+
+#include <toolchain.h>
+#include <linker/sections.h>
+#include <arch/cpu.h>
+
+#include <exc.h>
+
+#ifndef _ASMLANGUAGE
+#include <kernel.h>
+#include <zephyr/types.h>
+#include <sys/dlist.h>
+#include <sys/atomic.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct __esf _esf_t;
+typedef struct __basic_sf _basic_sf_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ASMLANGUAGE */
+
+#endif /* ZEPHYR_ARCH_ARM_INCLUDE_KERNEL_ARCH_DATA_H_ */

arch/common/CMakeLists.txt

@@ -35,7 +35,7 @@ zephyr_linker_sources_ifdef(CONFIG_NOCACHE_MEMORY
 )
 
 # Only ARM, X86 and OPENISA_RV32M1_RISCV32 use ROM_START_OFFSET.
-if (DEFINED CONFIG_ARM OR DEFINED CONFIG_X86
+if (DEFINED CONFIG_ARM OR DEFINED CONFIG_X86 OR DEFINED CONFIG_ARM64
     OR DEFINED CONFIG_SOC_OPENISA_RV32M1_RISCV32)
   zephyr_linker_sources(ROM_START SORT_KEY 0x0 rom_start_offset.ld)
 endif()

boards/arm64/bcm958402m2_a72/bcm958402m2_a72.yaml

@@ -1,7 +1,7 @@
 identifier: bcm958402m2_a72
 name: Broadcom BCM958402M2_A72
 type: mcu
-arch: arm
+arch: arm64
 toolchain:
   - zephyr
   - cross-compile

boards/arm64/qemu_cortex_a53/qemu_cortex_a53.dts

@@ -6,7 +6,7 @@
  */
 
 /dts-v1/;
-#include <arm/qemu-virt/qemu-virt-a53.dtsi>
+#include <arm64/qemu-virt/qemu-virt-a53.dtsi>
 
 / {
 	model = "QEMU Cortex-A53";

boards/arm64/qemu_cortex_a53/qemu_cortex_a53.yaml

@@ -2,7 +2,7 @@ identifier: qemu_cortex_a53
 name: QEMU Emulation for Cortex-A53
 type: qemu
 simulation: qemu
-arch: arm
+arch: arm64
 toolchain:
   - zephyr
   - cross-compile

boards/arm64/qemu_cortex_a53/qemu_cortex_a53_smp.yaml

@@ -2,7 +2,7 @@ identifier: qemu_cortex_a53_smp
 name: QEMU Emulation for Cortex-A53 SMP
 type: qemu
 simulation: qemu
-arch: arm
+arch: arm64
 toolchain:
   - zephyr
   - cross-compile

boards/arm64/qemu_cortex_a53/qemu_cortex_a53_xip.dts

@@ -6,7 +6,7 @@
  */
 
 /dts-v1/;
-#include <arm/qemu-virt/qemu-virt-a53.dtsi>
+#include <arm64/qemu-virt/qemu-virt-a53.dtsi>
 
 / {
 	model = "QEMU Cortex-A53";

boards/arm64/qemu_cortex_a53/qemu_cortex_a53_xip.yaml

@@ -2,7 +2,7 @@ identifier: qemu_cortex_a53_xip
 name: QEMU Emulation for Cortex-A53 (XIP)
 type: qemu
 simulation: qemu
-arch: arm
+arch: arm64
 toolchain:
   - zephyr
   - cross-compile

boards/arm64/xenvm/xenvm.dts

@@ -14,7 +14,7 @@
 /dts-v1/;
 
 #include <mem.h>
-#include <arm/armv8-a.dtsi>
+#include <arm64/armv8-a.dtsi>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
 / {

cmake/compiler/gcc/target.cmake

@@ -47,6 +47,8 @@ include(${ZEPHYR_BASE}/cmake/gcc-m-cpu.cmake)
 
 if("${ARCH}" STREQUAL "arm")
   include(${ZEPHYR_BASE}/cmake/compiler/gcc/target_arm.cmake)
+elseif("${ARCH}" STREQUAL "arm64")
+  include(${ZEPHYR_BASE}/cmake/compiler/gcc/target_arm64.cmake)
 elseif("${ARCH}" STREQUAL "arc")
   list(APPEND TOOLCHAIN_C_FLAGS
     -mcpu=${GCC_M_CPU}

cmake/compiler/gcc/target_arm.cmake

@@ -1,43 +1,35 @@
 # SPDX-License-Identifier: Apache-2.0
-if(CONFIG_ARM64)
+list(APPEND TOOLCHAIN_C_FLAGS   -mcpu=${GCC_M_CPU})
-  list(APPEND TOOLCHAIN_C_FLAGS   -mcpu=${GCC_M_CPU})
+list(APPEND TOOLCHAIN_LD_FLAGS  -mcpu=${GCC_M_CPU})
-  list(APPEND TOOLCHAIN_LD_FLAGS  -mcpu=${GCC_M_CPU})
 
-  list(APPEND TOOLCHAIN_C_FLAGS   -mabi=lp64)
+if(CONFIG_COMPILER_ISA_THUMB2)
-  list(APPEND TOOLCHAIN_LD_FLAGS  -mabi=lp64)
+  list(APPEND TOOLCHAIN_C_FLAGS   -mthumb)
+  list(APPEND TOOLCHAIN_LD_FLAGS  -mthumb)
+endif()
+
+list(APPEND TOOLCHAIN_C_FLAGS -mabi=aapcs)
+list(APPEND TOOLCHAIN_LD_FLAGS -mabi=aapcs)
+
+# Defines a mapping from GCC_M_CPU to FPU
+
+if(CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION)
+  set(PRECISION_TOKEN)
 else()
-  list(APPEND TOOLCHAIN_C_FLAGS   -mcpu=${GCC_M_CPU})
+  set(PRECISION_TOKEN sp-)
-  list(APPEND TOOLCHAIN_LD_FLAGS  -mcpu=${GCC_M_CPU})
+endif()
 
-  if(CONFIG_COMPILER_ISA_THUMB2)
+set(FPU_FOR_cortex-m4      fpv4-${PRECISION_TOKEN}d16)
-    list(APPEND TOOLCHAIN_C_FLAGS   -mthumb)
+set(FPU_FOR_cortex-m7      fpv5-${PRECISION_TOKEN}d16)
-    list(APPEND TOOLCHAIN_LD_FLAGS  -mthumb)
+set(FPU_FOR_cortex-m33     fpv5-${PRECISION_TOKEN}d16)
-  endif()
 
-  list(APPEND TOOLCHAIN_C_FLAGS -mabi=aapcs)
+if(CONFIG_FPU)
-  list(APPEND TOOLCHAIN_LD_FLAGS -mabi=aapcs)
+  list(APPEND TOOLCHAIN_C_FLAGS   -mfpu=${FPU_FOR_${GCC_M_CPU}})
-
+  list(APPEND TOOLCHAIN_LD_FLAGS  -mfpu=${FPU_FOR_${GCC_M_CPU}})
-  # Defines a mapping from GCC_M_CPU to FPU
+  if    (CONFIG_FP_SOFTABI)
-
+    list(APPEND TOOLCHAIN_C_FLAGS   -mfloat-abi=softfp)
-  if(CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION)
+    list(APPEND TOOLCHAIN_LD_FLAGS  -mfloat-abi=softfp)
-    set(PRECISION_TOKEN)
+  elseif(CONFIG_FP_HARDABI)
-  else()
+    list(APPEND TOOLCHAIN_C_FLAGS   -mfloat-abi=hard)
-    set(PRECISION_TOKEN sp-)
+    list(APPEND TOOLCHAIN_LD_FLAGS  -mfloat-abi=hard)
-  endif()
-
-  set(FPU_FOR_cortex-m4      fpv4-${PRECISION_TOKEN}d16)
-  set(FPU_FOR_cortex-m7      fpv5-${PRECISION_TOKEN}d16)
-  set(FPU_FOR_cortex-m33     fpv5-${PRECISION_TOKEN}d16)
-
-  if(CONFIG_FPU)
-    list(APPEND TOOLCHAIN_C_FLAGS   -mfpu=${FPU_FOR_${GCC_M_CPU}})
-    list(APPEND TOOLCHAIN_LD_FLAGS  -mfpu=${FPU_FOR_${GCC_M_CPU}})
-    if    (CONFIG_FP_SOFTABI)
-      list(APPEND TOOLCHAIN_C_FLAGS   -mfloat-abi=softfp)
-      list(APPEND TOOLCHAIN_LD_FLAGS  -mfloat-abi=softfp)
-    elseif(CONFIG_FP_HARDABI)
-      list(APPEND TOOLCHAIN_C_FLAGS   -mfloat-abi=hard)
-      list(APPEND TOOLCHAIN_LD_FLAGS  -mfloat-abi=hard)
-    endif()
   endif()
 endif()

cmake/compiler/gcc/target_arm64.cmake

@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: Apache-2.0
+list(APPEND TOOLCHAIN_C_FLAGS   -mcpu=${GCC_M_CPU})
+list(APPEND TOOLCHAIN_LD_FLAGS  -mcpu=${GCC_M_CPU})
+
+list(APPEND TOOLCHAIN_C_FLAGS   -mabi=lp64)
+list(APPEND TOOLCHAIN_LD_FLAGS  -mabi=lp64)

cmake/gcc-m-cpu.cmake

@@ -36,12 +36,14 @@ if("${ARCH}" STREQUAL "arm")
     set(GCC_M_CPU cortex-r5)
   elseif(CONFIG_CPU_CORTEX_R7)
     set(GCC_M_CPU cortex-r7)
-  elseif(CONFIG_CPU_CORTEX_A53)
+  else()
+    message(FATAL_ERROR "Expected CONFIG_CPU_CORTEX_x to be defined")
+  endif()
+elseif("${ARCH}" STREQUAL "arm64")
+  if(CONFIG_CPU_CORTEX_A53)
     set(GCC_M_CPU cortex-a53)
   elseif(CONFIG_CPU_CORTEX_A72)
     set(GCC_M_CPU cortex-a72)
-  else()
-    message(FATAL_ERROR "Expected CONFIG_CPU_CORTEX_x to be defined")
   endif()
 elseif("${ARCH}" STREQUAL "arc")
   if(CONFIG_CPU_EM4_FPUS)

cmake/toolchain/xtools/target.cmake

@@ -1,10 +1,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
-if(CONFIG_ARM64)
+set(CROSS_COMPILE_TARGET_arm        arm-zephyr-eabi)
-  set(CROSS_COMPILE_TARGET_arm         aarch64-zephyr-elf)
+set(CROSS_COMPILE_TARGET_arm64   aarch64-zephyr-elf)
-else()
-  set(CROSS_COMPILE_TARGET_arm         arm-zephyr-eabi)
-endif()
 set(CROSS_COMPILE_TARGET_nios2     nios2-zephyr-elf)
 set(CROSS_COMPILE_TARGET_riscv   riscv64-zephyr-elf)
 set(CROSS_COMPILE_TARGET_mips     mipsel-zephyr-elf)

cmake/toolchain/zephyr/0.11/target.cmake

@@ -1,10 +1,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
-if(CONFIG_ARM64)
+set(CROSS_COMPILE_TARGET_arm64      arm-zephyr-eabi)
-  set(CROSS_COMPILE_TARGET_arm         aarch64-zephyr-elf)
+set(CROSS_COMPILE_TARGET_arm     aarch64-zephyr-elf)
-else()
-  set(CROSS_COMPILE_TARGET_arm         arm-zephyr-eabi)
-endif()
 set(CROSS_COMPILE_TARGET_nios2     nios2-zephyr-elf)
 set(CROSS_COMPILE_TARGET_riscv   riscv64-zephyr-elf)
 set(CROSS_COMPILE_TARGET_mips     mipsel-zephyr-elf)

dts/arm64/broadcom/viper-a72.dtsi

@@ -0,0 +1,67 @@
+/*
+ * Copyright 2020 Broadcom
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm64/armv8-a.dtsi>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "viper-common.dtsi"
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72";
+			reg = <0>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL
+			      IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL
+			      IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL
+			      IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL
+			      IRQ_DEFAULT_PRIORITY>;
+		label = "arch_timer";
+	};
+
+	soc {
+		gic: interrupt-controller@42700000 {
+			compatible = "arm,gic";
+			reg = <0x42700000 0x010000>,
+			      <0x42780000 0x600000>;
+			interrupt-controller;
+			#interrupt-cells = <4>;
+			label = "GIC";
+			status = "okay";
+		};
+	};
+};
+
+&uart0 {
+	interrupt-parent = <&gic>;
+	interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL
+		      IRQ_DEFAULT_PRIORITY>;
+};
+
+&uart1 {
+	interrupt-parent = <&gic>;
+	interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL
+		      IRQ_DEFAULT_PRIORITY>;
+};
+
+&paxdma {
+	interrupt-parent = <&gic>;
+	interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL
+		      IRQ_DEFAULT_PRIORITY>;
+};

dts/arm64/broadcom/viper-common.dtsi

@@ -0,0 +1,75 @@
+/*
+ * Copyright 2020 Broadcom
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	soc {
+		sram0: memory@400000 {
+			device_type = "memory";
+			reg = <0x00400000 0x80000>;
+		};
+
+		uart0: uart@40020000 {
+			compatible = "ns16550";
+			reg = <0x40020000 0x400>;
+			clock-frequency = <25000000>;
+			label = "CRMU_UART";
+			status = "disabled";
+		};
+
+		uart1: uart@48100000 {
+			compatible = "ns16550";
+			reg = <0x48100000 0x400>;
+			clock-frequency = <100000000>;
+			label = "CCG_UART0";
+			status = "disabled";
+		};
+
+		pl330: pl330@48300000 {
+			compatible = "arm,dma-pl330";
+			reg = <0x48300000 0x2000>,
+			      <0x482f005c 0x20>;
+			reg-names = "pl330_regs",
+				    "control_regs";
+			microcode = <0x63b00000  0x1000>;
+			dma-channels = <8>;
+			#dma-cells = <1>;
+			label = "DMA_0";
+		};
+	};
+
+	pcie {
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		pcie0_ep: pcie@4e100000 {
+			compatible = "brcm,iproc-pcie-ep";
+			reg = <0x0 0x4e100000 0x0 0x2100>,
+			      <0x0 0x50000000 0x0 0x8000000>,
+			      <0x4 0x0 0x0 0x8000000>;
+			reg-names = "iproc_pcie_regs", "map_lowmem",
+				    "map_highmem";
+			label = "PCIE_0";
+			dmas = <&pl330 0>, <&pl330 1>;
+			dma-names = "txdma", "rxdma";
+		};
+
+		paxdma: paxdma@4e100800 {
+			compatible = "brcm,iproc-pax-dma-v2";
+			label = "DMA_1";
+			reg = <0x0 0x4e100800 0x0 0x2100>,
+			      <0x0 0x4f000000 0x0 0x200000>,
+			      <0x0 0x4f200000 0x0 0x10000>;
+			reg-names = "dme_regs", "rm_ring_regs",
+				    "rm_comm_regs";
+			dma-channels = <4>;
+			#dma-cells = <1>;
+			bd-memory = <0x63b00000 0x100000>;
+			scr-addr-loc = <0x200061f0>;
+			scr-size-loc = <0x200061f8>;
+			pcie-ep = <&pcie0_ep>;
+		};
+	};
+};

dts/arm64/qemu-virt/qemu-virt-a53.dtsi

@@ -14,7 +14,7 @@
  */
 
 #include <mem.h>
-#include <arm/armv8-a.dtsi>
+#include <arm64/armv8-a.dtsi>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
 / {

include/app_memory/app_memdomain.h

@@ -77,7 +77,7 @@ struct z_app_region {
  * specific: "aw" indicates section is allocatable and writable,
  * and "@progbits" indicates the section has data.
  */
-#ifdef CONFIG_ARM
+#if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
 /* ARM has a quirk in that '@' denotes a comment, so we have to send
  * %progbits to the assembler instead.
  */

include/arch/arch_inlines.h

@@ -15,7 +15,7 @@
 #if defined(CONFIG_X86) || defined(CONFIG_X86_64)
 #include <arch/x86/arch_inlines.h>
 #elif defined(CONFIG_ARM64)
-#include <arch/arm/aarch64/arch_inlines.h>
+#include <arch/arm64/arch_inlines.h>
 #elif defined(CONFIG_ARC)
 #include <arch/arc/arch_inlines.h>
 #elif defined(CONFIG_XTENSA)

include/arch/arm64/arch.h

@@ -19,18 +19,18 @@
 /* Add include for DTS generated information */
 #include <devicetree.h>
 
-#include <arch/arm/aarch64/thread.h>
+#include <arch/arm64/thread.h>
-#include <arch/arm/aarch64/exc.h>
+#include <arch/arm64/exc.h>
-#include <arch/arm/aarch64/irq.h>
+#include <arch/arm64/irq.h>
-#include <arch/arm/aarch64/misc.h>
+#include <arch/arm64/misc.h>
-#include <arch/arm/aarch64/asm_inline.h>
+#include <arch/arm64/asm_inline.h>
-#include <arch/arm/aarch64/cpu.h>
+#include <arch/arm64/cpu.h>
-#include <arch/arm/aarch64/macro.inc>
+#include <arch/arm64/macro.inc>
-#include <arch/arm/aarch64/sys_io.h>
+#include <arch/arm64/sys_io.h>
-#include <arch/arm/aarch64/timer.h>
+#include <arch/arm64/timer.h>
-#include <arch/arm/aarch64/error.h>
+#include <arch/arm64/error.h>
-#include <arch/arm/aarch64/arm_mmu.h>
+#include <arch/arm64/arm_mmu.h>
-#include <arch/arm/aarch64/thread_stack.h>
+#include <arch/arm64/thread_stack.h>
 #include <arch/common/addr_types.h>
 #include <arch/common/sys_bitops.h>
 #include <arch/common/ffs.h>

include/arch/arm64/arch_inlines.h

@@ -11,7 +11,7 @@
 
 #include <kernel_structs.h>
 #include <arch/cpu.h>
-#include <arch/arm/aarch64/lib_helpers.h>
+#include <arch/arm64/lib_helpers.h>
 
 static ALWAYS_INLINE _cpu_t *arch_curr_cpu(void)
 {

include/arch/arm64/asm_inline.h

@@ -13,7 +13,7 @@
  */
 
 #if defined(__GNUC__)
-#include <arch/arm/aarch64/asm_inline_gcc.h>
+#include <arch/arm64/asm_inline_gcc.h>
 #else
 #include <arch/arm/asm_inline_other.h>
 #endif

include/arch/arm64/asm_inline_gcc.h

@@ -16,7 +16,7 @@
 
 #ifndef _ASMLANGUAGE
 
-#include <arch/arm/aarch64/lib_helpers.h>
+#include <arch/arm64/lib_helpers.h>
 #include <zephyr/types.h>
 
 #ifdef __cplusplus

include/arch/arm64/error.h

@@ -14,8 +14,8 @@
 #ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH64_ERROR_H_
 #define ZEPHYR_INCLUDE_ARCH_ARM_AARCH64_ERROR_H_
 
-#include <arch/arm/aarch64/syscall.h>
+#include <arch/arm64/syscall.h>
-#include <arch/arm/aarch64/exc.h>
+#include <arch/arm64/exc.h>
 #include <stdbool.h>
 
 #ifdef __cplusplus

include/arch/arm64/lib_helpers.h

@@ -9,7 +9,7 @@
 
 #ifndef _ASMLANGUAGE
 
-#include <arch/arm/aarch64/cpu.h>
+#include <arch/arm64/cpu.h>
 #include <stdint.h>
 
 /* All the macros need a memory clobber */

include/arch/arm64/syscall.h

@@ -26,7 +26,7 @@
 
 #include <zephyr/types.h>
 #include <stdbool.h>
-#include <arch/arm/aarch64/cpu.h>
+#include <arch/arm64/cpu.h>
 
 #ifdef __cplusplus
 extern "C" {