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arm/arm64: Make ARM64 a standalone architecture

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Split ARM and ARM64 architectures.

Details:

- CONFIG_ARM64 is decoupled from CONFIG_ARM (not a subset anymore)
- Arch and include AArch64 files are in a dedicated directory
  (arch/arm64 and include/arch/arm64)
- AArch64 boards and SoC are moved to soc/arm64 and boards/arm64
- AArch64-specific DTS files are moved to dts/arm64
- The A72 support for the bcm_vk/viper board is moved in the
  boards/bcm_vk/viper directory

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This commit is contained in:
Carlo Caione 2021-03-25 11:56:15 +01:00 • committed by Kumar Gala
commit 3539c2fbb3
147 changed files with 595 additions and 189 deletions
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89
boards/arm/xenvm/xenvm.dts
View file

@ -1,89 +0,0 @@
/*
* Copyright (c) 2020 EPAM Systems
*
* SPDX-License-Identifier: Apache-2.0
*
* This file was created by running
*
* # LIBXL_DEBUG_DUMP_DTB=domu-libxl.dtb xl create zephyr.conf
*
* decompilling resulting domu-libxl.dtb and then manually aligning it
* with zephyr requirements.
*/
/dts-v1/;
#include <mem.h>
#include <arm/armv8-a.dtsi>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
model = "XENVM-4.15";
compatible = "xen,xenvm-4.15", "xen,xenvm";
interrupt-parent = <&gic>;
#address-cells = <0x02>;
#size-cells = <0x02>;
chosen {
zephyr,console = &sbsa;
zephyr,shell-uart = &sbsa;
zephyr,sram = &ram;
};
cpus {
#address-cells = <0x01>;
#size-cells = <0x00>;
cpu@0 {
device_type = "cpu";
compatible = "arm,armv8";
enable-method = "psci";
reg = <0x00>;
};
};
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
method = "hvc";
label = "PSCI";
};
ram: memory@40000000 {
device_type = "mmio-sram";
reg = <0x00 0x40000000 0x00 DT_SIZE_M(16)>;
};
gic: interrupt-controller@3001000 {
compatible = "arm,gic";
label = "GIC";
#interrupt-cells = <0x04>;
#address-cells = <0x00>;
interrupt-controller;
reg = <0x00 0x3001000 0x00 0x1000 0x00 0x3002000 0x00 0x2000>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 0x0d IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY
GIC_PPI 0x0e IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY
GIC_PPI 0x0b IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
interrupt-parent = <&gic>;
label = "arch_timer";
};
hypervisor: hypervisor@38000000 {
compatible = "xen,xen-4.15", "xen,xen";
reg = <0x00 0x38000000 0x00 0x1000000>;
interrupts = <GIC_PPI 0x0f IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
interrupt-parent = <&gic>;
};
sbsa: sbsa-pl011@22000000 {
compatible = "arm,sbsa-uart";
reg = <0x00 0x22000000 0x00 0x1000>;
interrupts = <GIC_SPI 0x00 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
interrupt-parent = <&gic>;
current-speed = <0x1c200>;
label = "UART";
};
};