arm: aarch32: Use proper sys functions for cache mainteinance
This patchset is fixing two things: 1. The proper sys_* functions are used for cache mainteinance operations. 2. To check the status of the L1 cache the SCB registers are probed so the code is assuming a core architecture cache is present, thus make the code conditionally compiled on CONFIG_ARCH_CACHE. Signed-off-by: Carlo Caione <ccaione@baylibre.com>
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1 changed files with 6 additions and 3 deletions
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@ -19,6 +19,7 @@
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#include <zephyr/sys/util.h>
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#include <zephyr/sys/util.h>
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#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
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#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
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#include <zephyr/linker/linker-defs.h>
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#include <zephyr/linker/linker-defs.h>
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#include <zephyr/cache.h>
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#if defined(CONFIG_CPU_HAS_NXP_MPU)
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#if defined(CONFIG_CPU_HAS_NXP_MPU)
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#include <fsl_sysmpu.h>
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#include <fsl_sysmpu.h>
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@ -108,6 +109,7 @@ void z_arm_init_arch_hw_at_boot(void)
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NVIC->ICPR[i] = 0xFFFFFFFF;
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NVIC->ICPR[i] = 0xFFFFFFFF;
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}
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}
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#if defined(CONFIG_ARCH_CACHE)
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#if defined(CONFIG_DCACHE)
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#if defined(CONFIG_DCACHE)
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/* Reset D-Cache settings. If the D-Cache was enabled,
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/* Reset D-Cache settings. If the D-Cache was enabled,
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* SCB_DisableDCache() takes care of cleaning and invalidating it.
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* SCB_DisableDCache() takes care of cleaning and invalidating it.
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@ -115,16 +117,17 @@ void z_arm_init_arch_hw_at_boot(void)
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* reset it to a known clean state.
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* reset it to a known clean state.
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*/
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*/
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if (SCB->CCR & SCB_CCR_DC_Msk) {
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if (SCB->CCR & SCB_CCR_DC_Msk) {
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SCB_DisableDCache();
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sys_cache_data_disable();
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} else {
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} else {
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SCB_InvalidateDCache();
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sys_cache_data_invd_all();
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}
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}
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#endif /* CONFIG_DCACHE */
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#endif /* CONFIG_DCACHE */
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#if defined(CONFIG_ICACHE)
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#if defined(CONFIG_ICACHE)
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/* Reset I-Cache settings. */
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/* Reset I-Cache settings. */
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SCB_DisableICache();
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sys_cache_instr_disable();
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#endif /* CONFIG_ICACHE */
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#endif /* CONFIG_ICACHE */
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#endif /* CONFIG_ARCH_CACHE */
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/* Restore Interrupts */
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/* Restore Interrupts */
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__enable_irq();
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__enable_irq();
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