From 34e02946520ff61015b3bf745bb3f7b9544f0004 Mon Sep 17 00:00:00 2001
From: Carlo Caione <ccaione@baylibre.com>
Date: Tue, 10 Jan 2023 16:33:11 +0100
Subject: [PATCH] arm: aarch32: Use proper sys functions for cache mainteinance

This patchset is fixing two things:

1. The proper sys_* functions are used for cache mainteinance
   operations.

2. To check the status of the L1 cache the SCB registers are probed so
   the code is assuming a core architecture cache is present, thus make
   the code conditionally compiled on CONFIG_ARCH_CACHE.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
---
 arch/arm/core/aarch32/cortex_m/scb.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/arch/arm/core/aarch32/cortex_m/scb.c b/arch/arm/core/aarch32/cortex_m/scb.c
index bf377e9ac87..581ef3cf37c 100644
--- a/arch/arm/core/aarch32/cortex_m/scb.c
+++ b/arch/arm/core/aarch32/cortex_m/scb.c
@@ -19,6 +19,7 @@
 #include <zephyr/sys/util.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <zephyr/linker/linker-defs.h>
+#include <zephyr/cache.h>
 
 #if defined(CONFIG_CPU_HAS_NXP_MPU)
 #include <fsl_sysmpu.h>
@@ -108,6 +109,7 @@ void z_arm_init_arch_hw_at_boot(void)
 		NVIC->ICPR[i] = 0xFFFFFFFF;
 	}
 
+#if defined(CONFIG_ARCH_CACHE)
 #if defined(CONFIG_DCACHE)
 	/* Reset D-Cache settings. If the D-Cache was enabled,
 	 * SCB_DisableDCache() takes care of cleaning and invalidating it.
@@ -115,16 +117,17 @@ void z_arm_init_arch_hw_at_boot(void)
 	 * reset it to a known clean state.
 	 */
 	if (SCB->CCR & SCB_CCR_DC_Msk) {
-		SCB_DisableDCache();
+		sys_cache_data_disable();
 	} else {
-		SCB_InvalidateDCache();
+		sys_cache_data_invd_all();
 	}
 #endif /* CONFIG_DCACHE */
 
 #if defined(CONFIG_ICACHE)
 	/* Reset I-Cache settings. */
-	SCB_DisableICache();
+	sys_cache_instr_disable();
 #endif /* CONFIG_ICACHE */
+#endif /* CONFIG_ARCH_CACHE */
 
 	/* Restore Interrupts */
 	__enable_irq();