boards: mimxrt1160_evk: Update RT1160 documentation for dual core support
Update rt1160 documentation for dual core support Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
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@ -172,6 +172,35 @@ The MIMXRT1160 SoC has six pairs of pinmux/gpio controllers.
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| GPIO_AD_04 | FLEXPWM1_PWM2 | pwm |
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| GPIO_AD_04 | FLEXPWM1_PWM2 | pwm |
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+---------------+-----------------+---------------------------+
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+---------------+-----------------+---------------------------+
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Dual Core samples
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*****************
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+-----------+------------------+----------------------------+
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| Core | Boot Address | Comment |
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+===========+==================+============================+
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| Cortex M7 | 0x30000000[630K] | primary core |
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+-----------+------------------+----------------------------+
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| Cortex M4 | 0x20020000[96k] | boots from OCRAM |
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+-----------+------------------+----------------------------+
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+----------+------------------+-----------------------+
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| Memory | Address[Size] | Comment |
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+==========+==================+=======================+
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| flexspi1 | 0x30000000[16M] | Cortex M7 flash |
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+----------+------------------+-----------------------+
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| sdram0 | 0x80030000[64M] | Cortex M7 ram |
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+----------+------------------+-----------------------+
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| ocram | 0x20020000[512K] | Cortex M4 "flash" |
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+----------+------------------+-----------------------+
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| sram1 | 0x20000000[128K] | Cortex M4 ram |
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+----------+------------------+-----------------------+
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| ocram2 | 0x200C0000[512K] | Mailbox/shared memory |
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+----------+------------------+-----------------------+
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Only the first 16K of ocram2 has the correct MPU region attributes set to be
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used as shared memory
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System Clock
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System Clock
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============
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============
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@ -190,6 +219,20 @@ Programming and Debugging
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Build and flash applications as usual (see :ref:`build_an_application` and
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Build and flash applications as usual (see :ref:`build_an_application` and
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:ref:`application_run` for more details).
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:ref:`application_run` for more details).
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Building a Dual-Core Image
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==========================
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Dual core samples load the M4 core image from flash into the shared ``ocram``
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region. The M7 core then sets the M4 boot address to this region. The only
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sample currently enabled for dual core builds is the ``openamp`` sample.
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To flash a dual core sample, the M4 image must be flashed first, so that it is
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written to flash. Then, the M7 image must be flashed. The openamp sysbuild
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sample will do this automatically by setting the image order.
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The secondary core can be debugged normally in single core builds
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(where the target is ``mimxrt1160_evk_cm4``). For dual core builds, the
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secondary core should be placed into a loop, then a debugger can be attached
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(see `AN13264`_, section 4.2.3 for more information)
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Configuring a Debug Probe
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Configuring a Debug Probe
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=========================
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=========================
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@ -285,3 +328,6 @@ should see the following message in the terminal:
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.. _Using J-Link with MIMXRT1160-EVK or MIMXRT1170-EVK:
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.. _Using J-Link with MIMXRT1160-EVK or MIMXRT1170-EVK:
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https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/Using-J-Link-with-MIMXRT1160-EVK-or-MIMXRT1170-EVK/ta-p/1529760
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https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/Using-J-Link-with-MIMXRT1160-EVK-or-MIMXRT1170-EVK/ta-p/1529760
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.. _AN13264:
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https://www.nxp.com/docs/en/application-note/AN13264.pdf
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