diff --git a/drivers/can/Kconfig.stm32fd b/drivers/can/Kconfig.stm32fd
index 3434f8428fc..2c5bf876b4e 100644
--- a/drivers/can/Kconfig.stm32fd
+++ b/drivers/can/Kconfig.stm32fd
@@ -29,6 +29,29 @@ config CAN_MAX_EXT_ID_FILTER
 	  Defines the maximum number of filters with extended ID (29-bit)
 	  that can be attached.
 
+choice CAN_STM32FD_CLOCK_SOURCE
+	prompt "CAN clock source"
+	default CAN_STM32FD_CLOCK_SOURCE_HSE
+	help
+	  CAN clock source selection.
+
+config CAN_STM32FD_CLOCK_SOURCE_HSE
+	bool "HSE"
+	help
+	  HSE clock used as FDCAN clock source.
+
+config CAN_STM32FD_CLOCK_SOURCE_PLL
+	bool "PLL"
+	help
+	  PLL "Q" clock used ad FDCAN clock source.
+
+config CAN_STM32FD_CLOCK_SOURCE_PCLK1
+	bool "PCLK1"
+	help
+	  PCLK1 clock used ad FDCAN clock source.
+
+endchoice
+
 config CAN_STM32_CLOCK_DIVISOR
 	int "CAN clock divisor"
 	range 1 30
diff --git a/drivers/can/can_stm32fd.c b/drivers/can/can_stm32fd.c
index 85d2321ad95..8a1b936f068 100644
--- a/drivers/can/can_stm32fd.c
+++ b/drivers/can/can_stm32fd.c
@@ -16,6 +16,16 @@
 
 LOG_MODULE_REGISTER(can_stm32fd, CONFIG_CAN_LOG_LEVEL);
 
+#if defined(CONFIG_CAN_STM32FD_CLOCK_SOURCE_HSE)
+#define CAN_STM32FD_CLOCK_SOURCE LL_RCC_FDCAN_CLKSOURCE_HSE
+#elif defined(CONFIG_CAN_STM32FD_CLOCK_SOURCE_PLL)
+#define CAN_STM32FD_CLOCK_SOURCE LL_RCC_FDCAN_CLKSOURCE_PLL
+#elif defined(CONFIG_CAN_STM32FD_CLOCK_SOURCE_PCLK1)
+#define CAN_STM32FD_CLOCK_SOURCE LL_RCC_FDCAN_CLKSOURCE_PCLK1
+#else
+#error "Unsupported FDCAN clock source"
+#endif
+
 #if CONFIG_CAN_STM32_CLOCK_DIVISOR != 1 && CONFIG_CAN_STM32_CLOCK_DIVISOR & 0x01
 #error CAN_STM32_CLOCK_DIVISOR invalid.\
 Allowed values are 1 or 2 * n, where n <= 15
@@ -40,7 +50,7 @@ static int can_stm32fd_get_core_clock(const struct device *dev, uint32_t *rate)
 
 static void can_stm32fd_clock_enable(void)
 {
-	LL_RCC_SetFDCANClockSource(LL_RCC_FDCAN_CLKSOURCE_PCLK1);
+	LL_RCC_SetFDCANClockSource(CAN_STM32FD_CLOCK_SOURCE);
 	__HAL_RCC_FDCAN_CLK_ENABLE();
 
 	FDCAN_CONFIG->CKDIV = CONFIG_CAN_STM32_CLOCK_DIVISOR >> 1;