soc: Add aesc

Currently, the only available platform is Nitrogen, featuring a
VexRiscv CPU that boots from external SPI flash and runs code from
external HyperRAM.

Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>

soc/aesc/CMakeLists.txt

@@ -0,0 +1,6 @@
+# Copyright (c) 2025 Aesc Silicon
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+
+add_subdirectory(${SOC_SERIES})

soc/aesc/Kconfig

@@ -0,0 +1,4 @@
+# Copyright (c) 2025 Aesc Silicon
+# SPDX-License-Identifier: Apache-2.0
+
+rsource "*/Kconfig"

soc/aesc/Kconfig.defconfig

@@ -0,0 +1,4 @@
+# Copyright (c) 2025 Aesc Silicon
+# SPDX-License-Identifier: Apache-2.0
+
+rsource "*/Kconfig.defconfig"

soc/aesc/Kconfig.soc

@@ -0,0 +1,4 @@
+# Copyright (c) 2025 Aesc Silicon
+# SPDX-License-Identifier: Apache-2.0
+
+rsource "*/Kconfig.soc"

soc/aesc/ip_identification.h

@@ -0,0 +1,104 @@
+/** @file
+ *  @brief IP Identification API.
+ *
+ *  Copyright (c) 2025 Aesc Silicon
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdint.h>
+#include <zephyr/sys/util.h>
+
+#ifndef INCLUDE_DRIVERS_AESC_IP_IDENTIFICATION_H_
+#define INCLUDE_DRIVERS_AESC_IP_IDENTIFICATION_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Each Aesc Silicon IP core is equipped with a so-called IP identification
+ * table at the beginning of each register map. This table helps to identify
+ * the underlying hardware.
+ *
+ * IP identification table for API v0:
+ *
+ * +---------+---------+---------+---------+
+ * | 31 - 24 | 23 - 16 | 15 -  8 |  7 -  0 |
+ * +=========+=========+=========+=========+
+ * |     API |  Length |                ID |    0x00 (header)
+ * +---------+---------+-------------------+
+ * |   Major |   Minor |             Patch |    0x04 (version)
+ * +---------+---------+-------------------+
+ *
+ * header.api_version: Version of this IP identification table.
+ * header.length: Total length of the IP identification table.
+ *                Important to relocate the register map.
+ * header.id: ID of this IP core.
+ * version: Defines the version of this IP core with major.minor.patchlevel.
+ */
+
+struct aesc_ip_id_table {
+	uint32_t header;
+	uint32_t version;
+};
+
+#define CONV_ADDR(addr) ((struct aesc_ip_id_table *)addr)
+
+#define HEADER_API_MASK			GENMASK(31, 24)
+#define HEADER_LENGTH_MASK		GENMASK(23, 16)
+#define HEADER_ID_MASK			GENMASK(15, 0)
+#define VERSION_MAJOR_MASK		GENMASK(31, 24)
+#define VERSION_MINOR_MASK		GENMASK(23, 16)
+#define VERSION_PATCH_MASK		GENMASK(15, 0)
+
+static inline unsigned int ip_id_get_major_version(volatile uintptr_t *addr)
+{
+	const volatile struct aesc_ip_id_table *table = CONV_ADDR(addr);
+
+	return FIELD_GET(VERSION_MAJOR_MASK, table->version);
+}
+
+static inline unsigned int ip_id_get_minor_version(volatile uintptr_t *addr)
+{
+	const volatile struct aesc_ip_id_table *table = CONV_ADDR(addr);
+
+	return FIELD_GET(VERSION_MINOR_MASK, table->version);
+}
+
+static inline unsigned int ip_id_get_patchlevel(volatile uintptr_t *addr)
+{
+	const volatile struct aesc_ip_id_table *table = CONV_ADDR(addr);
+
+	return FIELD_GET(VERSION_PATCH_MASK, table->version);
+}
+
+static inline unsigned int ip_id_get_api_version(volatile uintptr_t *addr)
+{
+	const volatile struct aesc_ip_id_table *table = CONV_ADDR(addr);
+
+	return FIELD_GET(HEADER_API_MASK, table->header);
+}
+
+static inline unsigned int ip_id_get_header_length(volatile uintptr_t *addr)
+{
+	const volatile struct aesc_ip_id_table *table = CONV_ADDR(addr);
+
+	return FIELD_GET(HEADER_LENGTH_MASK, table->header);
+}
+
+static inline unsigned int ip_id_get_id(volatile uintptr_t *addr)
+{
+	const volatile struct aesc_ip_id_table *table = CONV_ADDR(addr);
+
+	return FIELD_GET(HEADER_ID_MASK, table->header);
+}
+
+static inline uintptr_t ip_id_relocate_driver(volatile uintptr_t *addr)
+{
+	return (uintptr_t)addr + ip_id_get_header_length(addr);
+}
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* INCLUDE_DRIVERS_AESC_IP_IDENTIFICATION_H_ */

soc/aesc/nitrogen/CMakeLists.txt

@@ -0,0 +1,5 @@
+zephyr_include_directories(.)
+
+set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld
+    CACHE INTERNAL "SoC Linker script ${SOC_NAME}"
+)

soc/aesc/nitrogen/Kconfig

@@ -0,0 +1,16 @@
+# Copyright (c) 2025 Aesc Silicon
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_NITROGEN
+	select RISCV
+	select RISCV_PRIVILEGED
+	select INCLUDE_RESET_VECTOR
+	select ATOMIC_OPERATIONS_C
+	select RISCV_ISA_RV32I
+	select RISCV_ISA_EXT_M
+	select RISCV_ISA_EXT_C
+	select RISCV_ISA_EXT_ZICSR
+	select RISCV_ISA_EXT_ZIFENCEI
+
+config SOC_PART_NUMBER
+	default "elemrv_n" if SOC_ELEMRV_N

soc/aesc/nitrogen/Kconfig.defconfig

@@ -0,0 +1,15 @@
+# Copyright (c) 2025 Aesc Silicon
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_NITROGEN
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
+
+config NUM_IRQS
+	default 12
+
+config XIP
+	default n
+
+endif # SOC_SERIES_NITROGEN

soc/aesc/nitrogen/Kconfig.soc

@@ -0,0 +1,15 @@
+# Copyright (c) 2025 Aesc Silicon
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_NITROGEN
+	bool
+
+config SOC_ELEMRV_N
+	bool
+	select SOC_SERIES_NITROGEN
+
+config SOC_SERIES
+	default "nitrogen" if SOC_SERIES_NITROGEN
+
+config SOC
+	default "elemrv_n" if SOC_ELEMRV_N

soc/aesc/nitrogen/linker.ld

@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2025 Aesc Silicon
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/arch/riscv/common/linker.ld>

soc/aesc/nitrogen/soc.h

@@ -0,0 +1,10 @@
+/*
+ * Copyright (c) 2025 Aesc Silicon
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __RISCV32_AESC_VEXRISCV_NITROGEN_SOC_H_
+#define __RISCV32_AESC_VEXRISCV_NITROGEN_SOC_H_
+
+#endif /* __RISCV32_AESC_VEXRISCV_NITROGEN_SOC_H_ */

soc/aesc/soc.yml

@@ -0,0 +1,4 @@
+series:
+- name: nitrogen
+  socs:
+  - name: elemrv_n