michaelh/zephyr
1
0
Fork 0
Code Releases Activity

soc: Add aesc

Browse source 
Currently, the only available platform is Nitrogen, featuring a
VexRiscv CPU that boots from external SPI flash and runs code from
external HyperRAM.

Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
This commit is contained in:
Daniel Schultz 2025-04-30 08:06:28 +02:00 • committed by Benjamin Cabé
commit 3112f856d2
12 changed files with 194 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

4
soc/aesc/soc.yml Normal file
View file

@ -0,0 +1,4 @@
series:
- name: nitrogen
socs:
- name: elemrv_n