From 2e0c2aff9781198d5596171df6db7e64ff2ba98a Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 18 Jan 2017 11:07:25 -0600 Subject: [PATCH] arm: nvic: kill _NvicSwInterruptTrigger _NvicSwInterruptTrigger is only utilized by a testcase for irq handling on ARM-V7M. Just put the code into the testcase so we dont need to support an additional interface. Change-Id: I763c63c32a7a52918250458351d08b8fa54069dd Signed-off-by: Kumar Gala --- include/arch/arm/cortex_m/nvic.h | 26 ------------------- tests/kernel/arm_irq_vector_table/src/main.c | 7 ++++- .../test_arm_irq_vector_table/src/main.c | 7 ++++- 3 files changed, 12 insertions(+), 28 deletions(-) diff --git a/include/arch/arm/cortex_m/nvic.h b/include/arch/arm/cortex_m/nvic.h index fdbab32923f..8bd41596b06 100644 --- a/include/arch/arm/cortex_m/nvic.h +++ b/include/arch/arm/cortex_m/nvic.h @@ -224,32 +224,6 @@ static inline uint8_t _NvicIrqPrioGet(unsigned int irq) #endif /* CONFIG_ARMV6_M */ } -#if defined(CONFIG_ARMV6_M) -#elif defined(CONFIG_ARMV7_M) -/** - * - * @brief Trigger an interrupt via software - * - * Trigger interrupt #@a irq. The CPU will handle the IRQ when interrupts are - * enabled and/or returning from a higher priority interrupt. - * - * @param irq IRQ number - * @return N/A - */ - -static inline void _NvicSwInterruptTrigger(unsigned int irq) -{ -#if defined(CONFIG_SOC_TI_LM3S6965_QEMU) - /* the QEMU does not simulate the STIR register: this is a workaround */ - _NvicIrqPend(irq); -#else - __scs.stir = irq; -#endif -} -#else -#error Unknown ARM architecture -#endif /* CONFIG_ARMV6_M */ - #endif /* !_ASMLANGUAGE */ #ifdef __cplusplus diff --git a/tests/kernel/arm_irq_vector_table/src/main.c b/tests/kernel/arm_irq_vector_table/src/main.c index 2b801f281b4..81e1db163aa 100644 --- a/tests/kernel/arm_irq_vector_table/src/main.c +++ b/tests/kernel/arm_irq_vector_table/src/main.c @@ -81,7 +81,12 @@ void test_irq_vector_table(void) k_sem_take(&sem[2], K_NO_WAIT)), NULL); for (int ii = 0; ii < 3; ii++) { - _NvicSwInterruptTrigger(ii); +#if defined(CONFIG_SOC_TI_LM3S6965_QEMU) + /* the QEMU does not simulate the STIR register: this is a workaround */ + _NvicIrqPend(ii); +#else + __scs.stir = ii; +#endif } assert_false((k_sem_take(&sem[0], K_NO_WAIT) || diff --git a/tests/legacy/kernel/test_arm_irq_vector_table/src/main.c b/tests/legacy/kernel/test_arm_irq_vector_table/src/main.c index 29e7f97706d..f678c681fb1 100644 --- a/tests/legacy/kernel/test_arm_irq_vector_table/src/main.c +++ b/tests/legacy/kernel/test_arm_irq_vector_table/src/main.c @@ -94,7 +94,12 @@ void main(void) } for (int ii = 0; ii < 3; ii++) { - _NvicSwInterruptTrigger(ii); +#if defined(CONFIG_SOC_TI_LM3S6965_QEMU) + /* the QEMU does not simulate the STIR register: this is a workaround */ + _NvicIrqPend(ii); +#else + __scs.stir = ii; +#endif } rv = nano_task_sem_take(&sem[0], TICKS_NONE) &&