diff --git a/dts/arm/silabs/xg29/efr32bg29b140f1024im40.dtsi b/dts/arm/silabs/xg29/efr32bg29b140f1024im40.dtsi new file mode 100644 index 00000000000..fd458ea3c4e --- /dev/null +++ b/dts/arm/silabs/xg29/efr32bg29b140f1024im40.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32bg29b140f1024im40", "silabs,efr32bg29", "silabs,xg29", + "silabs,efr32", "simple-bus"; + }; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(256)>; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(1024)>; +}; diff --git a/dts/arm/silabs/xg29/efr32bg29b220f1024cj45.dtsi b/dts/arm/silabs/xg29/efr32bg29b220f1024cj45.dtsi new file mode 100644 index 00000000000..ec744a27f35 --- /dev/null +++ b/dts/arm/silabs/xg29/efr32bg29b220f1024cj45.dtsi @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +/ { + soc { + compatible = "silabs,efr32bg29b220f1024cj45", "silabs,efr32bg29", "silabs,xg29", + "silabs,efr32", "simple-bus"; + }; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(256)>; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(1024)>; +}; + +&dcdc { + regulator-boot-on; + regulator-initial-mode = ; + regulator-init-microvolt = <1800000>; + status = "okay"; +}; diff --git a/dts/arm/silabs/xg29/efr32bg29b221f1024cj45.dtsi b/dts/arm/silabs/xg29/efr32bg29b221f1024cj45.dtsi new file mode 100644 index 00000000000..b3fea2edd79 --- /dev/null +++ b/dts/arm/silabs/xg29/efr32bg29b221f1024cj45.dtsi @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +/ { + soc { + compatible = "silabs,efr32bg29b221f1024cj45", "silabs,efr32bg29", "silabs,xg29", + "silabs,efr32", "simple-bus"; + }; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(192)>; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(1024)>; +}; + +&dcdc { + regulator-boot-on; + regulator-initial-mode = ; + regulator-init-microvolt = <1800000>; + status = "okay"; +}; diff --git a/dts/arm/silabs/xg29/efr32bg29b230f1024cm40.dtsi b/dts/arm/silabs/xg29/efr32bg29b230f1024cm40.dtsi new file mode 100644 index 00000000000..0acadabcbdc --- /dev/null +++ b/dts/arm/silabs/xg29/efr32bg29b230f1024cm40.dtsi @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +/ { + soc { + compatible = "silabs,efr32bg29b230f1024cm40", "silabs,efr32bg29", "silabs,xg29", + "silabs,efr32", "simple-bus"; + }; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(256)>; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(1024)>; +}; + +&dcdc { + regulator-boot-on; + regulator-initial-mode = ; + regulator-init-microvolt = <1800000>; + status = "okay"; +}; diff --git a/dts/arm/silabs/xg29/efr32mg29b140f1024im40.dtsi b/dts/arm/silabs/xg29/efr32mg29b140f1024im40.dtsi new file mode 100644 index 00000000000..84fdecb94b2 --- /dev/null +++ b/dts/arm/silabs/xg29/efr32mg29b140f1024im40.dtsi @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efr32mg29b140f1024im40", "silabs,efr32mg29", "silabs,xg29", + "silabs,efr32", "simple-bus"; + }; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(256)>; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(1024)>; +}; diff --git a/dts/arm/silabs/xg29/efr32mg29b230f1024cm40.dtsi b/dts/arm/silabs/xg29/efr32mg29b230f1024cm40.dtsi new file mode 100644 index 00000000000..60e2d9f7465 --- /dev/null +++ b/dts/arm/silabs/xg29/efr32mg29b230f1024cm40.dtsi @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +/ { + soc { + compatible = "silabs,efr32mg29b230f1024cm40", "silabs,efr32mg29", "silabs,xg29", + "silabs,efr32", "simple-bus"; + }; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(256)>; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(1024)>; +}; + +&dcdc { + regulator-boot-on; + regulator-initial-mode = ; + regulator-init-microvolt = <1800000>; + status = "okay"; +}; diff --git a/dts/arm/silabs/xg29/xg29.dtsi b/dts/arm/silabs/xg29/xg29.dtsi new file mode 100644 index 00000000000..ee5c3b423b4 --- /dev/null +++ b/dts/arm/silabs/xg29/xg29.dtsi @@ -0,0 +1,461 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include + +/ { + chosen { + zephyr,flash-controller = &msc; + zephyr,entropy = &se; + }; + + clocks { + hfxort: hfxort { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&hfxo>; + }; + + hfrcodpllrt: hfrcodpllrt { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&hfrcodpll>; + }; + + sysclk: sysclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&hfrcodpll>; + }; + + hclk: hclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sysclk>; + /* Divisors 1, 2, 4, 8, 16 allowed */ + clock-div = <1>; + }; + + pclk: pclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&hclk>; + /* Divisors 1, 2 allowed */ + clock-div = <2>; + }; + + lspclk: lspclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&pclk>; + /* Fixed divisor of 2 */ + clock-div = <2>; + }; + + hclkdiv1024: hclkdiv1024 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&hclk>; + /* Fixed divisor of 1024 */ + clock-div = <1024>; + }; + + traceclk: traceclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sysclk>; + /* Divisors 1, 2, 3, 4 allowed */ + clock-div = <1>; + }; + + em01grpaclk: em01grpaclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&hfrcodpll>; + }; + + em01grpbclk: em01grpbclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&hfrcodpll>; + }; + + em01grpcclk: em01grpcclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&hfrcodpll>; + }; + + iadcclk: iadcclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&em01grpaclk>; + }; + + em23grpaclk: em23grpaclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&lfrco>; + }; + + em4grpaclk: em4grpaclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&lfrco>; + }; + + rtccclk: rtccclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&lfrco>; + }; + + wdog0clk: wdog0clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&lfrco>; + }; + + systickclk: systickclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&hclk>; + }; + + eusart0clk: eusart0clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&em01grpaclk>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m33"; + reg = <0>; + cpu-power-states = <&pstate_em1 &pstate_em2>; + }; + + power-states { + /* + * EM1 is a basic "CPU WFI idle", all high-freq clocks remain + * enabled. + */ + pstate_em1: em1 { + compatible = "zephyr,power-state"; + power-state-name = "runtime-idle"; + min-residency-us = <4>; + /* HFXO remains active */ + exit-latency-us = <2>; + }; + + /* + * EM2 is a deepsleep with HF clocks disabled by HW, voltages + * scaled down, etc. + */ + pstate_em2: em2 { + compatible = "zephyr,power-state"; + power-state-name = "suspend-to-idle"; + min-residency-us = <260>; + exit-latency-us = <250>; + }; + }; + }; + + sram0: memory@20000000 { + device_type = "memory"; + compatible = "mmio-sram"; + }; + + soc { + cmu: clock@50008000 { + compatible = "silabs,series-clock"; + reg = <0x50008000 0x4000>; + interrupts = <52 0>; + interrupt-names = "cmu"; + status = "okay"; + #clock-cells = <2>; + }; + + hfxo: hfxo@5000c000 { + #clock-cells = <0>; + compatible = "silabs,hfxo"; + reg = <0x5000c000 0x4000>; + interrupts = <50 0>; + interrupt-names = "hfxo0"; + clock-frequency = ; + ctune = <140>; + precision = <50>; + status = "disabled"; + }; + + hfrcodpll: hfrcodpll@50010000 { + #clock-cells = <0>; + compatible = "silabs,series2-hfrcodpll"; + reg = <0x50010000 0x4000>; + interrupts = <51 0>, <56 0>; + interrupt-names = "hfrco0", "dpll0"; + clock-frequency = ; + }; + + fsrco: fsrco@50018000 { + #clock-cells = <0>; + compatible = "fixed-clock"; + reg = <0x50018000 0x4000>; + clock-frequency = ; + }; + + lfxo: lfxo@50020000 { + #clock-cells = <0>; + compatible = "silabs,series2-lfxo"; + reg = <0x50020000 0x4000>; + interrupts = <27 0>; + interrupt-names = "lfxo"; + clock-frequency = <32768>; + ctune = <63>; + precision = <50>; + timeout = <4096>; + status = "disabled"; + }; + + lfrco: lfrco@50024000 { + #clock-cells = <0>; + compatible = "silabs,series2-lfrco"; + reg = <0x50024000 0x4000>; + interrupts = <28 0>; + interrupt-names = "lfrco"; + clock-frequency = <32768>; + }; + + ulfrco: ulfrco@50028000 { + #clock-cells = <0>; + compatible = "fixed-clock"; + reg = <0x50028000 0x4000>; + interrupts = <29 0>; + interrupt-names = "ulfrco"; + clock-frequency = <1000>; + }; + + clkin0: clkin0@5003c460 { + #clock-cells = <0>; + compatible = "fixed-clock"; + reg = <0x5003c460 0x4>; + clock-frequency = ; + }; + + msc: flash-controller@50030000 { + compatible = "silabs,gecko-flash-controller"; + reg = <0x50030000 0x4000>; + interrupts = <55 0>; + interrupt-names = "msc"; + #address-cells = <1>; + #size-cells = <1>; + + flash0: flash@8000000 { + compatible = "soc-nv-flash"; + write-block-size = <4>; + erase-block-size = <8192>; + }; + }; + + gpio: gpio@5003c000 { + compatible = "silabs,gecko-gpio"; + reg = <0x5003C000 0x440>; + interrupts = <31 0>, <30 0>; + interrupt-names = "GPIO_EVEN", "GPIO_ODD"; + clocks = <&cmu CLOCK_GPIO CLOCK_BRANCH_PCLK>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + + gpioa: gpio@5003c000 { + compatible = "silabs,gecko-gpio-port"; + reg = <0x5003C000 0x30>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + gpiob: gpio@5003c030 { + compatible = "silabs,gecko-gpio-port"; + reg = <0x5003C030 0x30>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + gpioc: gpio@5003c060 { + compatible = "silabs,gecko-gpio-port"; + reg = <0x5003C060 0x30>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + gpiod: gpio@5003c090 { + compatible = "silabs,gecko-gpio-port"; + reg = <0x5003C090 0x30>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + }; + + pinctrl: pin-controller@5003c440 { + compatible = "silabs,dbus-pinctrl"; + reg = <0x5003c440 0xbc0>; + }; + + dma0: dma@40040000{ + compatible = "silabs,ldma"; + reg = <0x40040000 0x4000>; + interrupts = <26 0>; + interrupt-names = "ldma"; + #dma-cells = <3>; + dma_channels = <8>; + status = "disabled"; + }; + + usart0: usart@5005c000 { + compatible = "silabs,gecko-usart"; + reg = <0x5005C000 0x400>; + interrupts = <16 0>, <17 0>; + interrupt-names = "rx", "tx"; + clocks = <&cmu CLOCK_USART0 CLOCK_BRANCH_PCLK>; + status = "disabled"; + }; + + usart1: usart@50060000 { + compatible = "silabs,gecko-usart"; + reg = <0x50060000 0x400>; + interrupts = <18 0>, <19 0>; + interrupt-names = "rx", "tx"; + clocks = <&cmu CLOCK_USART1 CLOCK_BRANCH_PCLK>; + status = "disabled"; + }; + + burtc0: burtc@50064000 { + compatible = "silabs,gecko-burtc"; + reg = <0x50064000 0x4000>; + interrupts = <23 0>; + interrupt-names = "burtc"; + clocks = <&cmu CLOCK_BURTC CLOCK_BRANCH_EM4GRPACLK>; + status = "disabled"; + }; + + i2c0: i2c@5a010000 { + compatible = "silabs,gecko-i2c"; + clock-frequency = ; + reg = <0x5a010000 0x4000>; + interrupts = <32 0>; + interrupt-names = "i2c0"; + clocks = <&cmu CLOCK_I2C0 CLOCK_BRANCH_LSPCLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@50068000 { + compatible = "silabs,gecko-i2c"; + clock-frequency = ; + reg = <0x50068000 0x4000>; + interrupts = <33 0>; + interrupt-names = "i2c1"; + clocks = <&cmu CLOCK_I2C1 CLOCK_BRANCH_PCLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + dcdc: dcdc@50094000 { + compatible = "silabs,series2-dcdc"; + reg = <0x50094000 0x4000>; + interrupts = <8 0>; + interrupt-names = "dcdc"; + status = "disabled"; + }; + + eusart0: eusart@5a040000 { + compatible = "silabs,eusart-spi"; + reg = <0x5A040000 0x4000>; + interrupts = <20 0>, <21 0>; + interrupt-names = "rx", "tx"; + clocks = <&cmu CLOCK_EUSART0 CLOCK_BRANCH_EUSART0CLK>; + status = "disabled"; + }; + + eusart1: eusart@500b4000 { + compatible = "silabs,eusart-spi"; + reg = <0x500B4000 0x4000>; + interrupts = <68 0>, <69 0>; + interrupt-names = "rx", "tx"; + clocks = <&cmu CLOCK_EUSART1 CLOCK_BRANCH_EM01GRPCCLK>; + status = "disabled"; + }; + + rtcc0: rtcc@58000000 { + compatible = "silabs,gecko-stimer"; + reg = <0x58000000 0x4000>; + interrupts = <15 0>; + interrupt-names = "rtcc"; + clocks = <&cmu CLOCK_RTCC CLOCK_BRANCH_RTCCCLK>; + clock-frequency = <32768>; + prescaler = <1>; + status = "disabled"; + }; + + wdog0: wdog@58018000 { + compatible = "silabs,gecko-wdog"; + reg = <0x58018000 0x4000>; + peripheral-id = <0>; + interrupts = <49 0>; + interrupt-names = "wdog0"; + clocks = <&cmu CLOCK_WDOG0 CLOCK_BRANCH_WDOG0CLK>; + status = "disabled"; + }; + + adc0: adc@5a004000 { + compatible = "silabs,gecko-iadc"; + reg = <0x5a004000 0x4000>; + interrupts = <54 0>; + interrupt-names = "iadc0"; + clocks = <&cmu CLOCK_IADC0 CLOCK_BRANCH_IADCCLK>; + status = "disabled"; + #io-channel-cells = <1>; + }; + + se: semailbox@4c000000 { + compatible = "silabs,gecko-semailbox"; + reg = <0x4c000000 0x1000>; + interrupts = <0 3>, <1 3>, <2 3>; + interrupt-names = "SETAMPERHOST", "SEMBRX", "SEMBTX"; + status = "disabled"; + }; + }; + + bt_hci_silabs: bt_hci_silabs { + compatible = "silabs,bt-hci-efr32"; + status = "disabled"; + }; + + hwinfo: hwinfo { + compatible = "silabs,series2-hwinfo"; + status = "disabled"; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <4>; +}; diff --git a/include/zephyr/drivers/clock_control/clock_control_silabs.h b/include/zephyr/drivers/clock_control/clock_control_silabs.h index ebabe6cbd83..b893c82aa56 100644 --- a/include/zephyr/drivers/clock_control/clock_control_silabs.h +++ b/include/zephyr/drivers/clock_control/clock_control_silabs.h @@ -19,6 +19,8 @@ #include #elif defined(CONFIG_SOC_SERIES_EFR32BG27) #include +#elif defined(CONFIG_SOC_SERIES_EFR32BG29) || defined(CONFIG_SOC_SERIES_EFR32MG29) +#include #endif struct silabs_clock_control_cmu_config { diff --git a/include/zephyr/dt-bindings/clock/silabs/xg29-clock.h b/include/zephyr/dt-bindings/clock/silabs/xg29-clock.h new file mode 100644 index 00000000000..20a9eb4b783 --- /dev/null +++ b/include/zephyr/dt-bindings/clock/silabs/xg29-clock.h @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2024 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * This file was generated by the script gen_clock_control.py in the hal_silabs module. + * Do not manually edit. + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG29_CLOCK_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG29_CLOCK_H_ + +#include +#include "common-clock.h" + +/* + * DT macros for clock tree nodes. + * Defined as: + * 0..5 - Bit within CLKEN register + * 6..8 - CLKEN register number + * Must stay in sync with equivalent SL_BUS_*_VALUE constants in the Silicon Labs HAL to be + * interpreted correctly by the clock control driver. + */ +#define CLOCK_ACMP0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 19)) +#define CLOCK_AGC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 0)) +#define CLOCK_AMUXCP0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 11)) +#define CLOCK_BUFC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 11)) +#define CLOCK_BURAM (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 28)) +#define CLOCK_BURTC (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 29)) +#define CLOCK_SEMAILBOX (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 21)) +#define CLOCK_DMEM (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 22)) +#define CLOCK_DCDC (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 31)) +#define CLOCK_DPLL0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 17)) +#define CLOCK_ETAMPDET (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 28)) +#define CLOCK_EUSART0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 20)) +#define CLOCK_EUSART1 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 23)) +#define CLOCK_FRC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 3)) +#define CLOCK_FSRCO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 20)) +#define CLOCK_GPCRC0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 3)) +#define CLOCK_GPIO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 26)) +#define CLOCK_HFRCO0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 18)) +#define CLOCK_HFXO0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 19)) +#define CLOCK_I2C0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 14)) +#define CLOCK_I2C1 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 15)) +#define CLOCK_IADC0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 10)) +#define CLOCK_ICACHE0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 16)) +#define CLOCK_IFADCDEBUG (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 12)) +#define CLOCK_LDMA0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 0)) +#define CLOCK_LDMAXBAR0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 1)) +#define CLOCK_LETIMER0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 12)) +#define CLOCK_LFRCO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 21)) +#define CLOCK_LFXO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 22)) +#define CLOCK_MODEM (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 1)) +#define CLOCK_MSC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 17)) +#define CLOCK_PDM (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 25)) +#define CLOCK_PRORTC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 10)) +#define CLOCK_PROTIMER (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 4)) +#define CLOCK_PRS (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 27)) +#define CLOCK_RAC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 5)) +#define CLOCK_RADIOAES (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 2)) +#define CLOCK_RDMAILBOX0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 8)) +#define CLOCK_RDMAILBOX1 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 9)) +#define CLOCK_RDSCRATCHPAD (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 7)) +#define CLOCK_RFCRC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 2)) +#define CLOCK_RFSENSE (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 14)) +#define CLOCK_RTCC (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 30)) +#define CLOCK_SMU (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 15)) +#define CLOCK_SYNTH (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 6)) +#define CLOCK_SYSCFG (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 16)) +#define CLOCK_TIMER0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 4)) +#define CLOCK_TIMER1 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 5)) +#define CLOCK_TIMER2 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 6)) +#define CLOCK_TIMER3 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 7)) +#define CLOCK_TIMER4 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 18)) +#define CLOCK_ULFRCO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 23)) +#define CLOCK_USART0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 8)) +#define CLOCK_USART1 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 9)) +#define CLOCK_WDOG0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 13)) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG29_CLOCK_H_ */ diff --git a/include/zephyr/dt-bindings/pinctrl/silabs/xg29-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/silabs/xg29-pinctrl.h new file mode 100644 index 00000000000..7a43b6a4975 --- /dev/null +++ b/include/zephyr/dt-bindings/pinctrl/silabs/xg29-pinctrl.h @@ -0,0 +1,2039 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * SPDX-License-Identifier: Apache-2.0 + * + * Pin Control for Silicon Labs XG29 devices + * + * This file was generated by the script gen_pinctrl.py in the hal_silabs module. + * Do not manually edit. + */ + +#ifndef ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG29_PINCTRL_H_ +#define ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG29_PINCTRL_H_ + +#include + +#define SILABS_DBUS_ACMP0_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 4, 1, 0, 1) + +#define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 7, 1, 0, 2) +#define SILABS_DBUS_CMU_CLKOUT1(port, pin) SILABS_DBUS(port, pin, 7, 1, 1, 3) +#define SILABS_DBUS_CMU_CLKOUT2(port, pin) SILABS_DBUS(port, pin, 7, 1, 2, 4) +#define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 7, 0, 0, 1) + +#define SILABS_DBUS_EUSART0_CS(port, pin) SILABS_DBUS(port, pin, 19, 1, 0, 1) +#define SILABS_DBUS_EUSART0_RTS(port, pin) SILABS_DBUS(port, pin, 19, 1, 1, 3) +#define SILABS_DBUS_EUSART0_RX(port, pin) SILABS_DBUS(port, pin, 19, 1, 2, 4) +#define SILABS_DBUS_EUSART0_SCLK(port, pin) SILABS_DBUS(port, pin, 19, 1, 3, 5) +#define SILABS_DBUS_EUSART0_TX(port, pin) SILABS_DBUS(port, pin, 19, 1, 4, 6) +#define SILABS_DBUS_EUSART0_CTS(port, pin) SILABS_DBUS(port, pin, 19, 0, 0, 2) + +#define SILABS_DBUS_EUSART1_CS(port, pin) SILABS_DBUS(port, pin, 27, 1, 0, 1) +#define SILABS_DBUS_EUSART1_RTS(port, pin) SILABS_DBUS(port, pin, 27, 1, 1, 3) +#define SILABS_DBUS_EUSART1_RX(port, pin) SILABS_DBUS(port, pin, 27, 1, 2, 4) +#define SILABS_DBUS_EUSART1_SCLK(port, pin) SILABS_DBUS(port, pin, 27, 1, 3, 5) +#define SILABS_DBUS_EUSART1_TX(port, pin) SILABS_DBUS(port, pin, 27, 1, 4, 6) +#define SILABS_DBUS_EUSART1_CTS(port, pin) SILABS_DBUS(port, pin, 27, 0, 0, 2) + +#define SILABS_DBUS_PTI_DCLK(port, pin) SILABS_DBUS(port, pin, 35, 1, 0, 1) +#define SILABS_DBUS_PTI_DFRAME(port, pin) SILABS_DBUS(port, pin, 35, 1, 1, 2) +#define SILABS_DBUS_PTI_DOUT(port, pin) SILABS_DBUS(port, pin, 35, 1, 2, 3) + +#define SILABS_DBUS_I2C0_SCL(port, pin) SILABS_DBUS(port, pin, 40, 1, 0, 1) +#define SILABS_DBUS_I2C0_SDA(port, pin) SILABS_DBUS(port, pin, 40, 1, 1, 2) + +#define SILABS_DBUS_I2C1_SCL(port, pin) SILABS_DBUS(port, pin, 44, 1, 0, 1) +#define SILABS_DBUS_I2C1_SDA(port, pin) SILABS_DBUS(port, pin, 44, 1, 1, 2) + +#define SILABS_DBUS_LETIMER0_OUT0(port, pin) SILABS_DBUS(port, pin, 48, 1, 0, 1) +#define SILABS_DBUS_LETIMER0_OUT1(port, pin) SILABS_DBUS(port, pin, 48, 1, 1, 2) + +#define SILABS_DBUS_MODEM_ANT0(port, pin) SILABS_DBUS(port, pin, 52, 1, 0, 1) +#define SILABS_DBUS_MODEM_ANT1(port, pin) SILABS_DBUS(port, pin, 52, 1, 1, 2) +#define SILABS_DBUS_MODEM_ANTROLLOVER(port, pin) SILABS_DBUS(port, pin, 52, 1, 2, 3) +#define SILABS_DBUS_MODEM_ANTRR0(port, pin) SILABS_DBUS(port, pin, 52, 1, 3, 4) +#define SILABS_DBUS_MODEM_ANTRR1(port, pin) SILABS_DBUS(port, pin, 52, 1, 4, 5) +#define SILABS_DBUS_MODEM_ANTRR2(port, pin) SILABS_DBUS(port, pin, 52, 1, 5, 6) +#define SILABS_DBUS_MODEM_ANTRR3(port, pin) SILABS_DBUS(port, pin, 52, 1, 6, 7) +#define SILABS_DBUS_MODEM_ANTRR4(port, pin) SILABS_DBUS(port, pin, 52, 1, 7, 8) +#define SILABS_DBUS_MODEM_ANTRR5(port, pin) SILABS_DBUS(port, pin, 52, 1, 8, 9) +#define SILABS_DBUS_MODEM_ANTSWEN(port, pin) SILABS_DBUS(port, pin, 52, 1, 9, 10) +#define SILABS_DBUS_MODEM_ANTSWUS(port, pin) SILABS_DBUS(port, pin, 52, 1, 10, 11) +#define SILABS_DBUS_MODEM_ANTTRIG(port, pin) SILABS_DBUS(port, pin, 52, 1, 11, 12) +#define SILABS_DBUS_MODEM_ANTTRIGSTOP(port, pin) SILABS_DBUS(port, pin, 52, 1, 12, 13) +#define SILABS_DBUS_MODEM_DCLK(port, pin) SILABS_DBUS(port, pin, 52, 1, 13, 14) +#define SILABS_DBUS_MODEM_DOUT(port, pin) SILABS_DBUS(port, pin, 52, 1, 14, 16) +#define SILABS_DBUS_MODEM_DIN(port, pin) SILABS_DBUS(port, pin, 52, 0, 0, 15) + +#define SILABS_DBUS_PDM_CLK(port, pin) SILABS_DBUS(port, pin, 70, 1, 0, 1) +#define SILABS_DBUS_PDM_DAT0(port, pin) SILABS_DBUS(port, pin, 70, 0, 0, 2) +#define SILABS_DBUS_PDM_DAT1(port, pin) SILABS_DBUS(port, pin, 70, 0, 0, 3) + +#define SILABS_DBUS_PRS0_ASYNCH0(port, pin) SILABS_DBUS(port, pin, 75, 1, 0, 1) +#define SILABS_DBUS_PRS0_ASYNCH1(port, pin) SILABS_DBUS(port, pin, 75, 1, 1, 2) +#define SILABS_DBUS_PRS0_ASYNCH2(port, pin) SILABS_DBUS(port, pin, 75, 1, 2, 3) +#define SILABS_DBUS_PRS0_ASYNCH3(port, pin) SILABS_DBUS(port, pin, 75, 1, 3, 4) +#define SILABS_DBUS_PRS0_ASYNCH4(port, pin) SILABS_DBUS(port, pin, 75, 1, 4, 5) +#define SILABS_DBUS_PRS0_ASYNCH5(port, pin) SILABS_DBUS(port, pin, 75, 1, 5, 6) +#define SILABS_DBUS_PRS0_ASYNCH6(port, pin) SILABS_DBUS(port, pin, 75, 1, 6, 7) +#define SILABS_DBUS_PRS0_ASYNCH7(port, pin) SILABS_DBUS(port, pin, 75, 1, 7, 8) +#define SILABS_DBUS_PRS0_ASYNCH8(port, pin) SILABS_DBUS(port, pin, 75, 1, 8, 9) +#define SILABS_DBUS_PRS0_ASYNCH9(port, pin) SILABS_DBUS(port, pin, 75, 1, 9, 10) +#define SILABS_DBUS_PRS0_ASYNCH10(port, pin) SILABS_DBUS(port, pin, 75, 1, 10, 11) +#define SILABS_DBUS_PRS0_ASYNCH11(port, pin) SILABS_DBUS(port, pin, 75, 1, 11, 12) +#define SILABS_DBUS_PRS0_SYNCH0(port, pin) SILABS_DBUS(port, pin, 75, 1, 12, 13) +#define SILABS_DBUS_PRS0_SYNCH1(port, pin) SILABS_DBUS(port, pin, 75, 1, 13, 14) +#define SILABS_DBUS_PRS0_SYNCH2(port, pin) SILABS_DBUS(port, pin, 75, 1, 14, 15) +#define SILABS_DBUS_PRS0_SYNCH3(port, pin) SILABS_DBUS(port, pin, 75, 1, 15, 16) + +#define SILABS_DBUS_TIMER0_CC0(port, pin) SILABS_DBUS(port, pin, 93, 1, 0, 1) +#define SILABS_DBUS_TIMER0_CC1(port, pin) SILABS_DBUS(port, pin, 93, 1, 1, 2) +#define SILABS_DBUS_TIMER0_CC2(port, pin) SILABS_DBUS(port, pin, 93, 1, 2, 3) +#define SILABS_DBUS_TIMER0_CDTI0(port, pin) SILABS_DBUS(port, pin, 93, 1, 3, 4) +#define SILABS_DBUS_TIMER0_CDTI1(port, pin) SILABS_DBUS(port, pin, 93, 1, 4, 5) +#define SILABS_DBUS_TIMER0_CDTI2(port, pin) SILABS_DBUS(port, pin, 93, 1, 5, 6) + +#define SILABS_DBUS_TIMER1_CC0(port, pin) SILABS_DBUS(port, pin, 101, 1, 0, 1) +#define SILABS_DBUS_TIMER1_CC1(port, pin) SILABS_DBUS(port, pin, 101, 1, 1, 2) +#define SILABS_DBUS_TIMER1_CC2(port, pin) SILABS_DBUS(port, pin, 101, 1, 2, 3) +#define SILABS_DBUS_TIMER1_CDTI0(port, pin) SILABS_DBUS(port, pin, 101, 1, 3, 4) +#define SILABS_DBUS_TIMER1_CDTI1(port, pin) SILABS_DBUS(port, pin, 101, 1, 4, 5) +#define SILABS_DBUS_TIMER1_CDTI2(port, pin) SILABS_DBUS(port, pin, 101, 1, 5, 6) + +#define SILABS_DBUS_TIMER2_CC0(port, pin) SILABS_DBUS(port, pin, 109, 1, 0, 1) +#define SILABS_DBUS_TIMER2_CC1(port, pin) SILABS_DBUS(port, pin, 109, 1, 1, 2) +#define SILABS_DBUS_TIMER2_CC2(port, pin) SILABS_DBUS(port, pin, 109, 1, 2, 3) +#define SILABS_DBUS_TIMER2_CDTI0(port, pin) SILABS_DBUS(port, pin, 109, 1, 3, 4) +#define SILABS_DBUS_TIMER2_CDTI1(port, pin) SILABS_DBUS(port, pin, 109, 1, 4, 5) +#define SILABS_DBUS_TIMER2_CDTI2(port, pin) SILABS_DBUS(port, pin, 109, 1, 5, 6) + +#define SILABS_DBUS_TIMER3_CC0(port, pin) SILABS_DBUS(port, pin, 117, 1, 0, 1) +#define SILABS_DBUS_TIMER3_CC1(port, pin) SILABS_DBUS(port, pin, 117, 1, 1, 2) +#define SILABS_DBUS_TIMER3_CC2(port, pin) SILABS_DBUS(port, pin, 117, 1, 2, 3) +#define SILABS_DBUS_TIMER3_CDTI0(port, pin) SILABS_DBUS(port, pin, 117, 1, 3, 4) +#define SILABS_DBUS_TIMER3_CDTI1(port, pin) SILABS_DBUS(port, pin, 117, 1, 4, 5) +#define SILABS_DBUS_TIMER3_CDTI2(port, pin) SILABS_DBUS(port, pin, 117, 1, 5, 6) + +#define SILABS_DBUS_TIMER4_CC0(port, pin) SILABS_DBUS(port, pin, 125, 1, 0, 1) +#define SILABS_DBUS_TIMER4_CC1(port, pin) SILABS_DBUS(port, pin, 125, 1, 1, 2) +#define SILABS_DBUS_TIMER4_CC2(port, pin) SILABS_DBUS(port, pin, 125, 1, 2, 3) +#define SILABS_DBUS_TIMER4_CDTI0(port, pin) SILABS_DBUS(port, pin, 125, 1, 3, 4) +#define SILABS_DBUS_TIMER4_CDTI1(port, pin) SILABS_DBUS(port, pin, 125, 1, 4, 5) +#define SILABS_DBUS_TIMER4_CDTI2(port, pin) SILABS_DBUS(port, pin, 125, 1, 5, 6) + +#define SILABS_DBUS_USART0_CS(port, pin) SILABS_DBUS(port, pin, 133, 1, 0, 1) +#define SILABS_DBUS_USART0_RTS(port, pin) SILABS_DBUS(port, pin, 133, 1, 1, 3) +#define SILABS_DBUS_USART0_RX(port, pin) SILABS_DBUS(port, pin, 133, 1, 2, 4) +#define SILABS_DBUS_USART0_CLK(port, pin) SILABS_DBUS(port, pin, 133, 1, 3, 5) +#define SILABS_DBUS_USART0_TX(port, pin) SILABS_DBUS(port, pin, 133, 1, 4, 6) +#define SILABS_DBUS_USART0_CTS(port, pin) SILABS_DBUS(port, pin, 133, 0, 0, 2) + +#define SILABS_DBUS_USART1_CS(port, pin) SILABS_DBUS(port, pin, 141, 1, 0, 1) +#define SILABS_DBUS_USART1_RTS(port, pin) SILABS_DBUS(port, pin, 141, 1, 1, 3) +#define SILABS_DBUS_USART1_RX(port, pin) SILABS_DBUS(port, pin, 141, 1, 2, 4) +#define SILABS_DBUS_USART1_CLK(port, pin) SILABS_DBUS(port, pin, 141, 1, 3, 5) +#define SILABS_DBUS_USART1_TX(port, pin) SILABS_DBUS(port, pin, 141, 1, 4, 6) +#define SILABS_DBUS_USART1_CTS(port, pin) SILABS_DBUS(port, pin, 141, 0, 0, 2) + +#define ACMP0_ACMPOUT_PA0 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x0) +#define ACMP0_ACMPOUT_PA1 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x1) +#define ACMP0_ACMPOUT_PA2 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x2) +#define ACMP0_ACMPOUT_PA3 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x3) +#define ACMP0_ACMPOUT_PA4 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x4) +#define ACMP0_ACMPOUT_PA5 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x5) +#define ACMP0_ACMPOUT_PA6 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x6) +#define ACMP0_ACMPOUT_PA7 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x7) +#define ACMP0_ACMPOUT_PA8 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x8) +#define ACMP0_ACMPOUT_PB0 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x0) +#define ACMP0_ACMPOUT_PB1 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x1) +#define ACMP0_ACMPOUT_PB2 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x2) +#define ACMP0_ACMPOUT_PB3 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x3) +#define ACMP0_ACMPOUT_PB4 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x4) +#define ACMP0_ACMPOUT_PC0 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x0) +#define ACMP0_ACMPOUT_PC1 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x1) +#define ACMP0_ACMPOUT_PC2 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x2) +#define ACMP0_ACMPOUT_PC3 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x3) +#define ACMP0_ACMPOUT_PC4 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x4) +#define ACMP0_ACMPOUT_PC5 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x5) +#define ACMP0_ACMPOUT_PC6 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x6) +#define ACMP0_ACMPOUT_PC7 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x7) +#define ACMP0_ACMPOUT_PD0 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x0) +#define ACMP0_ACMPOUT_PD1 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x1) +#define ACMP0_ACMPOUT_PD2 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x2) +#define ACMP0_ACMPOUT_PD3 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x3) + +#define CMU_CLKOUT0_PC0 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x0) +#define CMU_CLKOUT0_PC1 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x1) +#define CMU_CLKOUT0_PC2 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x2) +#define CMU_CLKOUT0_PC3 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x3) +#define CMU_CLKOUT0_PC4 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x4) +#define CMU_CLKOUT0_PC5 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x5) +#define CMU_CLKOUT0_PC6 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x6) +#define CMU_CLKOUT0_PC7 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x7) +#define CMU_CLKOUT0_PD0 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x0) +#define CMU_CLKOUT0_PD1 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x1) +#define CMU_CLKOUT0_PD2 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x2) +#define CMU_CLKOUT0_PD3 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x3) +#define CMU_CLKOUT1_PC0 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x0) +#define CMU_CLKOUT1_PC1 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x1) +#define CMU_CLKOUT1_PC2 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x2) +#define CMU_CLKOUT1_PC3 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x3) +#define CMU_CLKOUT1_PC4 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x4) +#define CMU_CLKOUT1_PC5 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x5) +#define CMU_CLKOUT1_PC6 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x6) +#define CMU_CLKOUT1_PC7 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x7) +#define CMU_CLKOUT1_PD0 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x0) +#define CMU_CLKOUT1_PD1 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x1) +#define CMU_CLKOUT1_PD2 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x2) +#define CMU_CLKOUT1_PD3 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x3) +#define CMU_CLKOUT2_PA0 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x0) +#define CMU_CLKOUT2_PA1 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x1) +#define CMU_CLKOUT2_PA2 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x2) +#define CMU_CLKOUT2_PA3 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x3) +#define CMU_CLKOUT2_PA4 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x4) +#define CMU_CLKOUT2_PA5 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x5) +#define CMU_CLKOUT2_PA6 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x6) +#define CMU_CLKOUT2_PA7 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x7) +#define CMU_CLKOUT2_PA8 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x8) +#define CMU_CLKOUT2_PB0 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x0) +#define CMU_CLKOUT2_PB1 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x1) +#define CMU_CLKOUT2_PB2 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x2) +#define CMU_CLKOUT2_PB3 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x3) +#define CMU_CLKOUT2_PB4 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x4) +#define CMU_CLKIN0_PC0 SILABS_DBUS_CMU_CLKIN0(0x2, 0x0) +#define CMU_CLKIN0_PC1 SILABS_DBUS_CMU_CLKIN0(0x2, 0x1) +#define CMU_CLKIN0_PC2 SILABS_DBUS_CMU_CLKIN0(0x2, 0x2) +#define CMU_CLKIN0_PC3 SILABS_DBUS_CMU_CLKIN0(0x2, 0x3) +#define CMU_CLKIN0_PC4 SILABS_DBUS_CMU_CLKIN0(0x2, 0x4) +#define CMU_CLKIN0_PC5 SILABS_DBUS_CMU_CLKIN0(0x2, 0x5) +#define CMU_CLKIN0_PC6 SILABS_DBUS_CMU_CLKIN0(0x2, 0x6) +#define CMU_CLKIN0_PC7 SILABS_DBUS_CMU_CLKIN0(0x2, 0x7) +#define CMU_CLKIN0_PD0 SILABS_DBUS_CMU_CLKIN0(0x3, 0x0) +#define CMU_CLKIN0_PD1 SILABS_DBUS_CMU_CLKIN0(0x3, 0x1) +#define CMU_CLKIN0_PD2 SILABS_DBUS_CMU_CLKIN0(0x3, 0x2) +#define CMU_CLKIN0_PD3 SILABS_DBUS_CMU_CLKIN0(0x3, 0x3) + +#define EUSART0_CS_PA0 SILABS_DBUS_EUSART0_CS(0x0, 0x0) +#define EUSART0_CS_PA1 SILABS_DBUS_EUSART0_CS(0x0, 0x1) +#define EUSART0_CS_PA2 SILABS_DBUS_EUSART0_CS(0x0, 0x2) +#define EUSART0_CS_PA3 SILABS_DBUS_EUSART0_CS(0x0, 0x3) +#define EUSART0_CS_PA4 SILABS_DBUS_EUSART0_CS(0x0, 0x4) +#define EUSART0_CS_PA5 SILABS_DBUS_EUSART0_CS(0x0, 0x5) +#define EUSART0_CS_PA6 SILABS_DBUS_EUSART0_CS(0x0, 0x6) +#define EUSART0_CS_PA7 SILABS_DBUS_EUSART0_CS(0x0, 0x7) +#define EUSART0_CS_PA8 SILABS_DBUS_EUSART0_CS(0x0, 0x8) +#define EUSART0_CS_PB0 SILABS_DBUS_EUSART0_CS(0x1, 0x0) +#define EUSART0_CS_PB1 SILABS_DBUS_EUSART0_CS(0x1, 0x1) +#define EUSART0_CS_PB2 SILABS_DBUS_EUSART0_CS(0x1, 0x2) +#define EUSART0_CS_PB3 SILABS_DBUS_EUSART0_CS(0x1, 0x3) +#define EUSART0_CS_PB4 SILABS_DBUS_EUSART0_CS(0x1, 0x4) +#define EUSART0_CS_PC0 SILABS_DBUS_EUSART0_CS(0x2, 0x0) +#define EUSART0_CS_PC1 SILABS_DBUS_EUSART0_CS(0x2, 0x1) +#define EUSART0_CS_PC2 SILABS_DBUS_EUSART0_CS(0x2, 0x2) +#define EUSART0_CS_PC3 SILABS_DBUS_EUSART0_CS(0x2, 0x3) +#define EUSART0_CS_PC4 SILABS_DBUS_EUSART0_CS(0x2, 0x4) +#define EUSART0_CS_PC5 SILABS_DBUS_EUSART0_CS(0x2, 0x5) +#define EUSART0_CS_PC6 SILABS_DBUS_EUSART0_CS(0x2, 0x6) +#define EUSART0_CS_PC7 SILABS_DBUS_EUSART0_CS(0x2, 0x7) +#define EUSART0_CS_PD0 SILABS_DBUS_EUSART0_CS(0x3, 0x0) +#define EUSART0_CS_PD1 SILABS_DBUS_EUSART0_CS(0x3, 0x1) +#define EUSART0_CS_PD2 SILABS_DBUS_EUSART0_CS(0x3, 0x2) +#define EUSART0_CS_PD3 SILABS_DBUS_EUSART0_CS(0x3, 0x3) +#define EUSART0_RTS_PA0 SILABS_DBUS_EUSART0_RTS(0x0, 0x0) +#define EUSART0_RTS_PA1 SILABS_DBUS_EUSART0_RTS(0x0, 0x1) +#define EUSART0_RTS_PA2 SILABS_DBUS_EUSART0_RTS(0x0, 0x2) +#define EUSART0_RTS_PA3 SILABS_DBUS_EUSART0_RTS(0x0, 0x3) +#define EUSART0_RTS_PA4 SILABS_DBUS_EUSART0_RTS(0x0, 0x4) +#define EUSART0_RTS_PA5 SILABS_DBUS_EUSART0_RTS(0x0, 0x5) +#define EUSART0_RTS_PA6 SILABS_DBUS_EUSART0_RTS(0x0, 0x6) +#define EUSART0_RTS_PA7 SILABS_DBUS_EUSART0_RTS(0x0, 0x7) +#define EUSART0_RTS_PA8 SILABS_DBUS_EUSART0_RTS(0x0, 0x8) +#define EUSART0_RTS_PB0 SILABS_DBUS_EUSART0_RTS(0x1, 0x0) +#define EUSART0_RTS_PB1 SILABS_DBUS_EUSART0_RTS(0x1, 0x1) +#define EUSART0_RTS_PB2 SILABS_DBUS_EUSART0_RTS(0x1, 0x2) +#define EUSART0_RTS_PB3 SILABS_DBUS_EUSART0_RTS(0x1, 0x3) +#define EUSART0_RTS_PB4 SILABS_DBUS_EUSART0_RTS(0x1, 0x4) +#define EUSART0_RTS_PC0 SILABS_DBUS_EUSART0_RTS(0x2, 0x0) +#define EUSART0_RTS_PC1 SILABS_DBUS_EUSART0_RTS(0x2, 0x1) +#define EUSART0_RTS_PC2 SILABS_DBUS_EUSART0_RTS(0x2, 0x2) +#define EUSART0_RTS_PC3 SILABS_DBUS_EUSART0_RTS(0x2, 0x3) +#define EUSART0_RTS_PC4 SILABS_DBUS_EUSART0_RTS(0x2, 0x4) +#define EUSART0_RTS_PC5 SILABS_DBUS_EUSART0_RTS(0x2, 0x5) +#define EUSART0_RTS_PC6 SILABS_DBUS_EUSART0_RTS(0x2, 0x6) +#define EUSART0_RTS_PC7 SILABS_DBUS_EUSART0_RTS(0x2, 0x7) +#define EUSART0_RTS_PD0 SILABS_DBUS_EUSART0_RTS(0x3, 0x0) +#define EUSART0_RTS_PD1 SILABS_DBUS_EUSART0_RTS(0x3, 0x1) +#define EUSART0_RTS_PD2 SILABS_DBUS_EUSART0_RTS(0x3, 0x2) +#define EUSART0_RTS_PD3 SILABS_DBUS_EUSART0_RTS(0x3, 0x3) +#define EUSART0_RX_PA0 SILABS_DBUS_EUSART0_RX(0x0, 0x0) +#define EUSART0_RX_PA1 SILABS_DBUS_EUSART0_RX(0x0, 0x1) +#define EUSART0_RX_PA2 SILABS_DBUS_EUSART0_RX(0x0, 0x2) +#define EUSART0_RX_PA3 SILABS_DBUS_EUSART0_RX(0x0, 0x3) +#define EUSART0_RX_PA4 SILABS_DBUS_EUSART0_RX(0x0, 0x4) +#define EUSART0_RX_PA5 SILABS_DBUS_EUSART0_RX(0x0, 0x5) +#define EUSART0_RX_PA6 SILABS_DBUS_EUSART0_RX(0x0, 0x6) +#define EUSART0_RX_PA7 SILABS_DBUS_EUSART0_RX(0x0, 0x7) +#define EUSART0_RX_PA8 SILABS_DBUS_EUSART0_RX(0x0, 0x8) +#define EUSART0_RX_PB0 SILABS_DBUS_EUSART0_RX(0x1, 0x0) +#define EUSART0_RX_PB1 SILABS_DBUS_EUSART0_RX(0x1, 0x1) +#define EUSART0_RX_PB2 SILABS_DBUS_EUSART0_RX(0x1, 0x2) +#define EUSART0_RX_PB3 SILABS_DBUS_EUSART0_RX(0x1, 0x3) +#define EUSART0_RX_PB4 SILABS_DBUS_EUSART0_RX(0x1, 0x4) +#define EUSART0_RX_PC0 SILABS_DBUS_EUSART0_RX(0x2, 0x0) +#define EUSART0_RX_PC1 SILABS_DBUS_EUSART0_RX(0x2, 0x1) +#define EUSART0_RX_PC2 SILABS_DBUS_EUSART0_RX(0x2, 0x2) +#define EUSART0_RX_PC3 SILABS_DBUS_EUSART0_RX(0x2, 0x3) +#define EUSART0_RX_PC4 SILABS_DBUS_EUSART0_RX(0x2, 0x4) +#define EUSART0_RX_PC5 SILABS_DBUS_EUSART0_RX(0x2, 0x5) +#define EUSART0_RX_PC6 SILABS_DBUS_EUSART0_RX(0x2, 0x6) +#define EUSART0_RX_PC7 SILABS_DBUS_EUSART0_RX(0x2, 0x7) +#define EUSART0_RX_PD0 SILABS_DBUS_EUSART0_RX(0x3, 0x0) +#define EUSART0_RX_PD1 SILABS_DBUS_EUSART0_RX(0x3, 0x1) +#define EUSART0_RX_PD2 SILABS_DBUS_EUSART0_RX(0x3, 0x2) +#define EUSART0_RX_PD3 SILABS_DBUS_EUSART0_RX(0x3, 0x3) +#define EUSART0_SCLK_PA0 SILABS_DBUS_EUSART0_SCLK(0x0, 0x0) +#define EUSART0_SCLK_PA1 SILABS_DBUS_EUSART0_SCLK(0x0, 0x1) +#define EUSART0_SCLK_PA2 SILABS_DBUS_EUSART0_SCLK(0x0, 0x2) +#define EUSART0_SCLK_PA3 SILABS_DBUS_EUSART0_SCLK(0x0, 0x3) +#define EUSART0_SCLK_PA4 SILABS_DBUS_EUSART0_SCLK(0x0, 0x4) +#define EUSART0_SCLK_PA5 SILABS_DBUS_EUSART0_SCLK(0x0, 0x5) +#define EUSART0_SCLK_PA6 SILABS_DBUS_EUSART0_SCLK(0x0, 0x6) +#define EUSART0_SCLK_PA7 SILABS_DBUS_EUSART0_SCLK(0x0, 0x7) +#define EUSART0_SCLK_PA8 SILABS_DBUS_EUSART0_SCLK(0x0, 0x8) +#define EUSART0_SCLK_PB0 SILABS_DBUS_EUSART0_SCLK(0x1, 0x0) +#define EUSART0_SCLK_PB1 SILABS_DBUS_EUSART0_SCLK(0x1, 0x1) +#define EUSART0_SCLK_PB2 SILABS_DBUS_EUSART0_SCLK(0x1, 0x2) +#define EUSART0_SCLK_PB3 SILABS_DBUS_EUSART0_SCLK(0x1, 0x3) +#define EUSART0_SCLK_PB4 SILABS_DBUS_EUSART0_SCLK(0x1, 0x4) +#define EUSART0_SCLK_PC0 SILABS_DBUS_EUSART0_SCLK(0x2, 0x0) +#define EUSART0_SCLK_PC1 SILABS_DBUS_EUSART0_SCLK(0x2, 0x1) +#define EUSART0_SCLK_PC2 SILABS_DBUS_EUSART0_SCLK(0x2, 0x2) +#define EUSART0_SCLK_PC3 SILABS_DBUS_EUSART0_SCLK(0x2, 0x3) +#define EUSART0_SCLK_PC4 SILABS_DBUS_EUSART0_SCLK(0x2, 0x4) +#define EUSART0_SCLK_PC5 SILABS_DBUS_EUSART0_SCLK(0x2, 0x5) +#define EUSART0_SCLK_PC6 SILABS_DBUS_EUSART0_SCLK(0x2, 0x6) +#define EUSART0_SCLK_PC7 SILABS_DBUS_EUSART0_SCLK(0x2, 0x7) +#define EUSART0_SCLK_PD0 SILABS_DBUS_EUSART0_SCLK(0x3, 0x0) +#define EUSART0_SCLK_PD1 SILABS_DBUS_EUSART0_SCLK(0x3, 0x1) +#define EUSART0_SCLK_PD2 SILABS_DBUS_EUSART0_SCLK(0x3, 0x2) +#define EUSART0_SCLK_PD3 SILABS_DBUS_EUSART0_SCLK(0x3, 0x3) +#define EUSART0_TX_PA0 SILABS_DBUS_EUSART0_TX(0x0, 0x0) +#define EUSART0_TX_PA1 SILABS_DBUS_EUSART0_TX(0x0, 0x1) +#define EUSART0_TX_PA2 SILABS_DBUS_EUSART0_TX(0x0, 0x2) +#define EUSART0_TX_PA3 SILABS_DBUS_EUSART0_TX(0x0, 0x3) +#define EUSART0_TX_PA4 SILABS_DBUS_EUSART0_TX(0x0, 0x4) +#define EUSART0_TX_PA5 SILABS_DBUS_EUSART0_TX(0x0, 0x5) +#define EUSART0_TX_PA6 SILABS_DBUS_EUSART0_TX(0x0, 0x6) +#define EUSART0_TX_PA7 SILABS_DBUS_EUSART0_TX(0x0, 0x7) +#define EUSART0_TX_PA8 SILABS_DBUS_EUSART0_TX(0x0, 0x8) +#define EUSART0_TX_PB0 SILABS_DBUS_EUSART0_TX(0x1, 0x0) +#define EUSART0_TX_PB1 SILABS_DBUS_EUSART0_TX(0x1, 0x1) +#define EUSART0_TX_PB2 SILABS_DBUS_EUSART0_TX(0x1, 0x2) +#define EUSART0_TX_PB3 SILABS_DBUS_EUSART0_TX(0x1, 0x3) +#define EUSART0_TX_PB4 SILABS_DBUS_EUSART0_TX(0x1, 0x4) +#define EUSART0_TX_PC0 SILABS_DBUS_EUSART0_TX(0x2, 0x0) +#define EUSART0_TX_PC1 SILABS_DBUS_EUSART0_TX(0x2, 0x1) +#define EUSART0_TX_PC2 SILABS_DBUS_EUSART0_TX(0x2, 0x2) +#define EUSART0_TX_PC3 SILABS_DBUS_EUSART0_TX(0x2, 0x3) +#define EUSART0_TX_PC4 SILABS_DBUS_EUSART0_TX(0x2, 0x4) +#define EUSART0_TX_PC5 SILABS_DBUS_EUSART0_TX(0x2, 0x5) +#define EUSART0_TX_PC6 SILABS_DBUS_EUSART0_TX(0x2, 0x6) +#define EUSART0_TX_PC7 SILABS_DBUS_EUSART0_TX(0x2, 0x7) +#define EUSART0_TX_PD0 SILABS_DBUS_EUSART0_TX(0x3, 0x0) +#define EUSART0_TX_PD1 SILABS_DBUS_EUSART0_TX(0x3, 0x1) +#define EUSART0_TX_PD2 SILABS_DBUS_EUSART0_TX(0x3, 0x2) +#define EUSART0_TX_PD3 SILABS_DBUS_EUSART0_TX(0x3, 0x3) +#define EUSART0_CTS_PA0 SILABS_DBUS_EUSART0_CTS(0x0, 0x0) +#define EUSART0_CTS_PA1 SILABS_DBUS_EUSART0_CTS(0x0, 0x1) +#define EUSART0_CTS_PA2 SILABS_DBUS_EUSART0_CTS(0x0, 0x2) +#define EUSART0_CTS_PA3 SILABS_DBUS_EUSART0_CTS(0x0, 0x3) +#define EUSART0_CTS_PA4 SILABS_DBUS_EUSART0_CTS(0x0, 0x4) +#define EUSART0_CTS_PA5 SILABS_DBUS_EUSART0_CTS(0x0, 0x5) +#define EUSART0_CTS_PA6 SILABS_DBUS_EUSART0_CTS(0x0, 0x6) +#define EUSART0_CTS_PA7 SILABS_DBUS_EUSART0_CTS(0x0, 0x7) +#define EUSART0_CTS_PA8 SILABS_DBUS_EUSART0_CTS(0x0, 0x8) +#define EUSART0_CTS_PB0 SILABS_DBUS_EUSART0_CTS(0x1, 0x0) +#define EUSART0_CTS_PB1 SILABS_DBUS_EUSART0_CTS(0x1, 0x1) +#define EUSART0_CTS_PB2 SILABS_DBUS_EUSART0_CTS(0x1, 0x2) +#define EUSART0_CTS_PB3 SILABS_DBUS_EUSART0_CTS(0x1, 0x3) +#define EUSART0_CTS_PB4 SILABS_DBUS_EUSART0_CTS(0x1, 0x4) +#define EUSART0_CTS_PC0 SILABS_DBUS_EUSART0_CTS(0x2, 0x0) +#define EUSART0_CTS_PC1 SILABS_DBUS_EUSART0_CTS(0x2, 0x1) +#define EUSART0_CTS_PC2 SILABS_DBUS_EUSART0_CTS(0x2, 0x2) +#define EUSART0_CTS_PC3 SILABS_DBUS_EUSART0_CTS(0x2, 0x3) +#define EUSART0_CTS_PC4 SILABS_DBUS_EUSART0_CTS(0x2, 0x4) +#define EUSART0_CTS_PC5 SILABS_DBUS_EUSART0_CTS(0x2, 0x5) +#define EUSART0_CTS_PC6 SILABS_DBUS_EUSART0_CTS(0x2, 0x6) +#define EUSART0_CTS_PC7 SILABS_DBUS_EUSART0_CTS(0x2, 0x7) +#define EUSART0_CTS_PD0 SILABS_DBUS_EUSART0_CTS(0x3, 0x0) +#define EUSART0_CTS_PD1 SILABS_DBUS_EUSART0_CTS(0x3, 0x1) +#define EUSART0_CTS_PD2 SILABS_DBUS_EUSART0_CTS(0x3, 0x2) +#define EUSART0_CTS_PD3 SILABS_DBUS_EUSART0_CTS(0x3, 0x3) + +#define EUSART1_CS_PA0 SILABS_DBUS_EUSART1_CS(0x0, 0x0) +#define EUSART1_CS_PA1 SILABS_DBUS_EUSART1_CS(0x0, 0x1) +#define EUSART1_CS_PA2 SILABS_DBUS_EUSART1_CS(0x0, 0x2) +#define EUSART1_CS_PA3 SILABS_DBUS_EUSART1_CS(0x0, 0x3) +#define EUSART1_CS_PA4 SILABS_DBUS_EUSART1_CS(0x0, 0x4) +#define EUSART1_CS_PA5 SILABS_DBUS_EUSART1_CS(0x0, 0x5) +#define EUSART1_CS_PA6 SILABS_DBUS_EUSART1_CS(0x0, 0x6) +#define EUSART1_CS_PA7 SILABS_DBUS_EUSART1_CS(0x0, 0x7) +#define EUSART1_CS_PA8 SILABS_DBUS_EUSART1_CS(0x0, 0x8) +#define EUSART1_CS_PB0 SILABS_DBUS_EUSART1_CS(0x1, 0x0) +#define EUSART1_CS_PB1 SILABS_DBUS_EUSART1_CS(0x1, 0x1) +#define EUSART1_CS_PB2 SILABS_DBUS_EUSART1_CS(0x1, 0x2) +#define EUSART1_CS_PB3 SILABS_DBUS_EUSART1_CS(0x1, 0x3) +#define EUSART1_CS_PB4 SILABS_DBUS_EUSART1_CS(0x1, 0x4) +#define EUSART1_CS_PC0 SILABS_DBUS_EUSART1_CS(0x2, 0x0) +#define EUSART1_CS_PC1 SILABS_DBUS_EUSART1_CS(0x2, 0x1) +#define EUSART1_CS_PC2 SILABS_DBUS_EUSART1_CS(0x2, 0x2) +#define EUSART1_CS_PC3 SILABS_DBUS_EUSART1_CS(0x2, 0x3) +#define EUSART1_CS_PC4 SILABS_DBUS_EUSART1_CS(0x2, 0x4) +#define EUSART1_CS_PC5 SILABS_DBUS_EUSART1_CS(0x2, 0x5) +#define EUSART1_CS_PC6 SILABS_DBUS_EUSART1_CS(0x2, 0x6) +#define EUSART1_CS_PC7 SILABS_DBUS_EUSART1_CS(0x2, 0x7) +#define EUSART1_CS_PD0 SILABS_DBUS_EUSART1_CS(0x3, 0x0) +#define EUSART1_CS_PD1 SILABS_DBUS_EUSART1_CS(0x3, 0x1) +#define EUSART1_CS_PD2 SILABS_DBUS_EUSART1_CS(0x3, 0x2) +#define EUSART1_CS_PD3 SILABS_DBUS_EUSART1_CS(0x3, 0x3) +#define EUSART1_RTS_PA0 SILABS_DBUS_EUSART1_RTS(0x0, 0x0) +#define EUSART1_RTS_PA1 SILABS_DBUS_EUSART1_RTS(0x0, 0x1) +#define EUSART1_RTS_PA2 SILABS_DBUS_EUSART1_RTS(0x0, 0x2) +#define EUSART1_RTS_PA3 SILABS_DBUS_EUSART1_RTS(0x0, 0x3) +#define EUSART1_RTS_PA4 SILABS_DBUS_EUSART1_RTS(0x0, 0x4) +#define EUSART1_RTS_PA5 SILABS_DBUS_EUSART1_RTS(0x0, 0x5) +#define EUSART1_RTS_PA6 SILABS_DBUS_EUSART1_RTS(0x0, 0x6) +#define EUSART1_RTS_PA7 SILABS_DBUS_EUSART1_RTS(0x0, 0x7) +#define EUSART1_RTS_PA8 SILABS_DBUS_EUSART1_RTS(0x0, 0x8) +#define EUSART1_RTS_PB0 SILABS_DBUS_EUSART1_RTS(0x1, 0x0) +#define EUSART1_RTS_PB1 SILABS_DBUS_EUSART1_RTS(0x1, 0x1) +#define EUSART1_RTS_PB2 SILABS_DBUS_EUSART1_RTS(0x1, 0x2) +#define EUSART1_RTS_PB3 SILABS_DBUS_EUSART1_RTS(0x1, 0x3) +#define EUSART1_RTS_PB4 SILABS_DBUS_EUSART1_RTS(0x1, 0x4) +#define EUSART1_RTS_PC0 SILABS_DBUS_EUSART1_RTS(0x2, 0x0) +#define EUSART1_RTS_PC1 SILABS_DBUS_EUSART1_RTS(0x2, 0x1) +#define EUSART1_RTS_PC2 SILABS_DBUS_EUSART1_RTS(0x2, 0x2) +#define EUSART1_RTS_PC3 SILABS_DBUS_EUSART1_RTS(0x2, 0x3) +#define EUSART1_RTS_PC4 SILABS_DBUS_EUSART1_RTS(0x2, 0x4) +#define EUSART1_RTS_PC5 SILABS_DBUS_EUSART1_RTS(0x2, 0x5) +#define EUSART1_RTS_PC6 SILABS_DBUS_EUSART1_RTS(0x2, 0x6) +#define EUSART1_RTS_PC7 SILABS_DBUS_EUSART1_RTS(0x2, 0x7) +#define EUSART1_RTS_PD0 SILABS_DBUS_EUSART1_RTS(0x3, 0x0) +#define EUSART1_RTS_PD1 SILABS_DBUS_EUSART1_RTS(0x3, 0x1) +#define EUSART1_RTS_PD2 SILABS_DBUS_EUSART1_RTS(0x3, 0x2) +#define EUSART1_RTS_PD3 SILABS_DBUS_EUSART1_RTS(0x3, 0x3) +#define EUSART1_RX_PA0 SILABS_DBUS_EUSART1_RX(0x0, 0x0) +#define EUSART1_RX_PA1 SILABS_DBUS_EUSART1_RX(0x0, 0x1) +#define EUSART1_RX_PA2 SILABS_DBUS_EUSART1_RX(0x0, 0x2) +#define EUSART1_RX_PA3 SILABS_DBUS_EUSART1_RX(0x0, 0x3) +#define EUSART1_RX_PA4 SILABS_DBUS_EUSART1_RX(0x0, 0x4) +#define EUSART1_RX_PA5 SILABS_DBUS_EUSART1_RX(0x0, 0x5) +#define EUSART1_RX_PA6 SILABS_DBUS_EUSART1_RX(0x0, 0x6) +#define EUSART1_RX_PA7 SILABS_DBUS_EUSART1_RX(0x0, 0x7) +#define EUSART1_RX_PA8 SILABS_DBUS_EUSART1_RX(0x0, 0x8) +#define EUSART1_RX_PB0 SILABS_DBUS_EUSART1_RX(0x1, 0x0) +#define EUSART1_RX_PB1 SILABS_DBUS_EUSART1_RX(0x1, 0x1) +#define EUSART1_RX_PB2 SILABS_DBUS_EUSART1_RX(0x1, 0x2) +#define EUSART1_RX_PB3 SILABS_DBUS_EUSART1_RX(0x1, 0x3) +#define EUSART1_RX_PB4 SILABS_DBUS_EUSART1_RX(0x1, 0x4) +#define EUSART1_RX_PC0 SILABS_DBUS_EUSART1_RX(0x2, 0x0) +#define EUSART1_RX_PC1 SILABS_DBUS_EUSART1_RX(0x2, 0x1) +#define EUSART1_RX_PC2 SILABS_DBUS_EUSART1_RX(0x2, 0x2) +#define EUSART1_RX_PC3 SILABS_DBUS_EUSART1_RX(0x2, 0x3) +#define EUSART1_RX_PC4 SILABS_DBUS_EUSART1_RX(0x2, 0x4) +#define EUSART1_RX_PC5 SILABS_DBUS_EUSART1_RX(0x2, 0x5) +#define EUSART1_RX_PC6 SILABS_DBUS_EUSART1_RX(0x2, 0x6) +#define EUSART1_RX_PC7 SILABS_DBUS_EUSART1_RX(0x2, 0x7) +#define EUSART1_RX_PD0 SILABS_DBUS_EUSART1_RX(0x3, 0x0) +#define EUSART1_RX_PD1 SILABS_DBUS_EUSART1_RX(0x3, 0x1) +#define EUSART1_RX_PD2 SILABS_DBUS_EUSART1_RX(0x3, 0x2) +#define EUSART1_RX_PD3 SILABS_DBUS_EUSART1_RX(0x3, 0x3) +#define EUSART1_SCLK_PA0 SILABS_DBUS_EUSART1_SCLK(0x0, 0x0) +#define EUSART1_SCLK_PA1 SILABS_DBUS_EUSART1_SCLK(0x0, 0x1) +#define EUSART1_SCLK_PA2 SILABS_DBUS_EUSART1_SCLK(0x0, 0x2) +#define EUSART1_SCLK_PA3 SILABS_DBUS_EUSART1_SCLK(0x0, 0x3) +#define EUSART1_SCLK_PA4 SILABS_DBUS_EUSART1_SCLK(0x0, 0x4) +#define EUSART1_SCLK_PA5 SILABS_DBUS_EUSART1_SCLK(0x0, 0x5) +#define EUSART1_SCLK_PA6 SILABS_DBUS_EUSART1_SCLK(0x0, 0x6) +#define EUSART1_SCLK_PA7 SILABS_DBUS_EUSART1_SCLK(0x0, 0x7) +#define EUSART1_SCLK_PA8 SILABS_DBUS_EUSART1_SCLK(0x0, 0x8) +#define EUSART1_SCLK_PB0 SILABS_DBUS_EUSART1_SCLK(0x1, 0x0) +#define EUSART1_SCLK_PB1 SILABS_DBUS_EUSART1_SCLK(0x1, 0x1) +#define EUSART1_SCLK_PB2 SILABS_DBUS_EUSART1_SCLK(0x1, 0x2) +#define EUSART1_SCLK_PB3 SILABS_DBUS_EUSART1_SCLK(0x1, 0x3) +#define EUSART1_SCLK_PB4 SILABS_DBUS_EUSART1_SCLK(0x1, 0x4) +#define EUSART1_SCLK_PC0 SILABS_DBUS_EUSART1_SCLK(0x2, 0x0) +#define EUSART1_SCLK_PC1 SILABS_DBUS_EUSART1_SCLK(0x2, 0x1) +#define EUSART1_SCLK_PC2 SILABS_DBUS_EUSART1_SCLK(0x2, 0x2) +#define EUSART1_SCLK_PC3 SILABS_DBUS_EUSART1_SCLK(0x2, 0x3) +#define EUSART1_SCLK_PC4 SILABS_DBUS_EUSART1_SCLK(0x2, 0x4) +#define EUSART1_SCLK_PC5 SILABS_DBUS_EUSART1_SCLK(0x2, 0x5) +#define EUSART1_SCLK_PC6 SILABS_DBUS_EUSART1_SCLK(0x2, 0x6) +#define EUSART1_SCLK_PC7 SILABS_DBUS_EUSART1_SCLK(0x2, 0x7) +#define EUSART1_SCLK_PD0 SILABS_DBUS_EUSART1_SCLK(0x3, 0x0) +#define EUSART1_SCLK_PD1 SILABS_DBUS_EUSART1_SCLK(0x3, 0x1) +#define EUSART1_SCLK_PD2 SILABS_DBUS_EUSART1_SCLK(0x3, 0x2) +#define EUSART1_SCLK_PD3 SILABS_DBUS_EUSART1_SCLK(0x3, 0x3) +#define EUSART1_TX_PA0 SILABS_DBUS_EUSART1_TX(0x0, 0x0) +#define EUSART1_TX_PA1 SILABS_DBUS_EUSART1_TX(0x0, 0x1) +#define EUSART1_TX_PA2 SILABS_DBUS_EUSART1_TX(0x0, 0x2) +#define EUSART1_TX_PA3 SILABS_DBUS_EUSART1_TX(0x0, 0x3) +#define EUSART1_TX_PA4 SILABS_DBUS_EUSART1_TX(0x0, 0x4) +#define EUSART1_TX_PA5 SILABS_DBUS_EUSART1_TX(0x0, 0x5) +#define EUSART1_TX_PA6 SILABS_DBUS_EUSART1_TX(0x0, 0x6) +#define EUSART1_TX_PA7 SILABS_DBUS_EUSART1_TX(0x0, 0x7) +#define EUSART1_TX_PA8 SILABS_DBUS_EUSART1_TX(0x0, 0x8) +#define EUSART1_TX_PB0 SILABS_DBUS_EUSART1_TX(0x1, 0x0) +#define EUSART1_TX_PB1 SILABS_DBUS_EUSART1_TX(0x1, 0x1) +#define EUSART1_TX_PB2 SILABS_DBUS_EUSART1_TX(0x1, 0x2) +#define EUSART1_TX_PB3 SILABS_DBUS_EUSART1_TX(0x1, 0x3) +#define EUSART1_TX_PB4 SILABS_DBUS_EUSART1_TX(0x1, 0x4) +#define EUSART1_TX_PC0 SILABS_DBUS_EUSART1_TX(0x2, 0x0) +#define EUSART1_TX_PC1 SILABS_DBUS_EUSART1_TX(0x2, 0x1) +#define EUSART1_TX_PC2 SILABS_DBUS_EUSART1_TX(0x2, 0x2) +#define EUSART1_TX_PC3 SILABS_DBUS_EUSART1_TX(0x2, 0x3) +#define EUSART1_TX_PC4 SILABS_DBUS_EUSART1_TX(0x2, 0x4) +#define EUSART1_TX_PC5 SILABS_DBUS_EUSART1_TX(0x2, 0x5) +#define EUSART1_TX_PC6 SILABS_DBUS_EUSART1_TX(0x2, 0x6) +#define EUSART1_TX_PC7 SILABS_DBUS_EUSART1_TX(0x2, 0x7) +#define EUSART1_TX_PD0 SILABS_DBUS_EUSART1_TX(0x3, 0x0) +#define EUSART1_TX_PD1 SILABS_DBUS_EUSART1_TX(0x3, 0x1) +#define EUSART1_TX_PD2 SILABS_DBUS_EUSART1_TX(0x3, 0x2) +#define EUSART1_TX_PD3 SILABS_DBUS_EUSART1_TX(0x3, 0x3) +#define EUSART1_CTS_PA0 SILABS_DBUS_EUSART1_CTS(0x0, 0x0) +#define EUSART1_CTS_PA1 SILABS_DBUS_EUSART1_CTS(0x0, 0x1) +#define EUSART1_CTS_PA2 SILABS_DBUS_EUSART1_CTS(0x0, 0x2) +#define EUSART1_CTS_PA3 SILABS_DBUS_EUSART1_CTS(0x0, 0x3) +#define EUSART1_CTS_PA4 SILABS_DBUS_EUSART1_CTS(0x0, 0x4) +#define EUSART1_CTS_PA5 SILABS_DBUS_EUSART1_CTS(0x0, 0x5) +#define EUSART1_CTS_PA6 SILABS_DBUS_EUSART1_CTS(0x0, 0x6) +#define EUSART1_CTS_PA7 SILABS_DBUS_EUSART1_CTS(0x0, 0x7) +#define EUSART1_CTS_PA8 SILABS_DBUS_EUSART1_CTS(0x0, 0x8) +#define EUSART1_CTS_PB0 SILABS_DBUS_EUSART1_CTS(0x1, 0x0) +#define EUSART1_CTS_PB1 SILABS_DBUS_EUSART1_CTS(0x1, 0x1) +#define EUSART1_CTS_PB2 SILABS_DBUS_EUSART1_CTS(0x1, 0x2) +#define EUSART1_CTS_PB3 SILABS_DBUS_EUSART1_CTS(0x1, 0x3) +#define EUSART1_CTS_PB4 SILABS_DBUS_EUSART1_CTS(0x1, 0x4) +#define EUSART1_CTS_PC0 SILABS_DBUS_EUSART1_CTS(0x2, 0x0) +#define EUSART1_CTS_PC1 SILABS_DBUS_EUSART1_CTS(0x2, 0x1) +#define EUSART1_CTS_PC2 SILABS_DBUS_EUSART1_CTS(0x2, 0x2) +#define EUSART1_CTS_PC3 SILABS_DBUS_EUSART1_CTS(0x2, 0x3) +#define EUSART1_CTS_PC4 SILABS_DBUS_EUSART1_CTS(0x2, 0x4) +#define EUSART1_CTS_PC5 SILABS_DBUS_EUSART1_CTS(0x2, 0x5) +#define EUSART1_CTS_PC6 SILABS_DBUS_EUSART1_CTS(0x2, 0x6) +#define EUSART1_CTS_PC7 SILABS_DBUS_EUSART1_CTS(0x2, 0x7) +#define EUSART1_CTS_PD0 SILABS_DBUS_EUSART1_CTS(0x3, 0x0) +#define EUSART1_CTS_PD1 SILABS_DBUS_EUSART1_CTS(0x3, 0x1) +#define EUSART1_CTS_PD2 SILABS_DBUS_EUSART1_CTS(0x3, 0x2) +#define EUSART1_CTS_PD3 SILABS_DBUS_EUSART1_CTS(0x3, 0x3) + +#define PTI_DCLK_PC0 SILABS_DBUS_PTI_DCLK(0x2, 0x0) +#define PTI_DCLK_PC1 SILABS_DBUS_PTI_DCLK(0x2, 0x1) +#define PTI_DCLK_PC2 SILABS_DBUS_PTI_DCLK(0x2, 0x2) +#define PTI_DCLK_PC3 SILABS_DBUS_PTI_DCLK(0x2, 0x3) +#define PTI_DCLK_PC4 SILABS_DBUS_PTI_DCLK(0x2, 0x4) +#define PTI_DCLK_PC5 SILABS_DBUS_PTI_DCLK(0x2, 0x5) +#define PTI_DCLK_PC6 SILABS_DBUS_PTI_DCLK(0x2, 0x6) +#define PTI_DCLK_PC7 SILABS_DBUS_PTI_DCLK(0x2, 0x7) +#define PTI_DCLK_PD0 SILABS_DBUS_PTI_DCLK(0x3, 0x0) +#define PTI_DCLK_PD1 SILABS_DBUS_PTI_DCLK(0x3, 0x1) +#define PTI_DCLK_PD2 SILABS_DBUS_PTI_DCLK(0x3, 0x2) +#define PTI_DCLK_PD3 SILABS_DBUS_PTI_DCLK(0x3, 0x3) +#define PTI_DFRAME_PC0 SILABS_DBUS_PTI_DFRAME(0x2, 0x0) +#define PTI_DFRAME_PC1 SILABS_DBUS_PTI_DFRAME(0x2, 0x1) +#define PTI_DFRAME_PC2 SILABS_DBUS_PTI_DFRAME(0x2, 0x2) +#define PTI_DFRAME_PC3 SILABS_DBUS_PTI_DFRAME(0x2, 0x3) +#define PTI_DFRAME_PC4 SILABS_DBUS_PTI_DFRAME(0x2, 0x4) +#define PTI_DFRAME_PC5 SILABS_DBUS_PTI_DFRAME(0x2, 0x5) +#define PTI_DFRAME_PC6 SILABS_DBUS_PTI_DFRAME(0x2, 0x6) +#define PTI_DFRAME_PC7 SILABS_DBUS_PTI_DFRAME(0x2, 0x7) +#define PTI_DFRAME_PD0 SILABS_DBUS_PTI_DFRAME(0x3, 0x0) +#define PTI_DFRAME_PD1 SILABS_DBUS_PTI_DFRAME(0x3, 0x1) +#define PTI_DFRAME_PD2 SILABS_DBUS_PTI_DFRAME(0x3, 0x2) +#define PTI_DFRAME_PD3 SILABS_DBUS_PTI_DFRAME(0x3, 0x3) +#define PTI_DOUT_PC0 SILABS_DBUS_PTI_DOUT(0x2, 0x0) +#define PTI_DOUT_PC1 SILABS_DBUS_PTI_DOUT(0x2, 0x1) +#define PTI_DOUT_PC2 SILABS_DBUS_PTI_DOUT(0x2, 0x2) +#define PTI_DOUT_PC3 SILABS_DBUS_PTI_DOUT(0x2, 0x3) +#define PTI_DOUT_PC4 SILABS_DBUS_PTI_DOUT(0x2, 0x4) +#define PTI_DOUT_PC5 SILABS_DBUS_PTI_DOUT(0x2, 0x5) +#define PTI_DOUT_PC6 SILABS_DBUS_PTI_DOUT(0x2, 0x6) +#define PTI_DOUT_PC7 SILABS_DBUS_PTI_DOUT(0x2, 0x7) +#define PTI_DOUT_PD0 SILABS_DBUS_PTI_DOUT(0x3, 0x0) +#define PTI_DOUT_PD1 SILABS_DBUS_PTI_DOUT(0x3, 0x1) +#define PTI_DOUT_PD2 SILABS_DBUS_PTI_DOUT(0x3, 0x2) +#define PTI_DOUT_PD3 SILABS_DBUS_PTI_DOUT(0x3, 0x3) + +#define I2C0_SCL_PA0 SILABS_DBUS_I2C0_SCL(0x0, 0x0) +#define I2C0_SCL_PA1 SILABS_DBUS_I2C0_SCL(0x0, 0x1) +#define I2C0_SCL_PA2 SILABS_DBUS_I2C0_SCL(0x0, 0x2) +#define I2C0_SCL_PA3 SILABS_DBUS_I2C0_SCL(0x0, 0x3) +#define I2C0_SCL_PA4 SILABS_DBUS_I2C0_SCL(0x0, 0x4) +#define I2C0_SCL_PA5 SILABS_DBUS_I2C0_SCL(0x0, 0x5) +#define I2C0_SCL_PA6 SILABS_DBUS_I2C0_SCL(0x0, 0x6) +#define I2C0_SCL_PA7 SILABS_DBUS_I2C0_SCL(0x0, 0x7) +#define I2C0_SCL_PA8 SILABS_DBUS_I2C0_SCL(0x0, 0x8) +#define I2C0_SCL_PB0 SILABS_DBUS_I2C0_SCL(0x1, 0x0) +#define I2C0_SCL_PB1 SILABS_DBUS_I2C0_SCL(0x1, 0x1) +#define I2C0_SCL_PB2 SILABS_DBUS_I2C0_SCL(0x1, 0x2) +#define I2C0_SCL_PB3 SILABS_DBUS_I2C0_SCL(0x1, 0x3) +#define I2C0_SCL_PB4 SILABS_DBUS_I2C0_SCL(0x1, 0x4) +#define I2C0_SCL_PC0 SILABS_DBUS_I2C0_SCL(0x2, 0x0) +#define I2C0_SCL_PC1 SILABS_DBUS_I2C0_SCL(0x2, 0x1) +#define I2C0_SCL_PC2 SILABS_DBUS_I2C0_SCL(0x2, 0x2) +#define I2C0_SCL_PC3 SILABS_DBUS_I2C0_SCL(0x2, 0x3) +#define I2C0_SCL_PC4 SILABS_DBUS_I2C0_SCL(0x2, 0x4) +#define I2C0_SCL_PC5 SILABS_DBUS_I2C0_SCL(0x2, 0x5) +#define I2C0_SCL_PC6 SILABS_DBUS_I2C0_SCL(0x2, 0x6) +#define I2C0_SCL_PC7 SILABS_DBUS_I2C0_SCL(0x2, 0x7) +#define I2C0_SCL_PD0 SILABS_DBUS_I2C0_SCL(0x3, 0x0) +#define I2C0_SCL_PD1 SILABS_DBUS_I2C0_SCL(0x3, 0x1) +#define I2C0_SCL_PD2 SILABS_DBUS_I2C0_SCL(0x3, 0x2) +#define I2C0_SCL_PD3 SILABS_DBUS_I2C0_SCL(0x3, 0x3) +#define I2C0_SDA_PA0 SILABS_DBUS_I2C0_SDA(0x0, 0x0) +#define I2C0_SDA_PA1 SILABS_DBUS_I2C0_SDA(0x0, 0x1) +#define I2C0_SDA_PA2 SILABS_DBUS_I2C0_SDA(0x0, 0x2) +#define I2C0_SDA_PA3 SILABS_DBUS_I2C0_SDA(0x0, 0x3) +#define I2C0_SDA_PA4 SILABS_DBUS_I2C0_SDA(0x0, 0x4) +#define I2C0_SDA_PA5 SILABS_DBUS_I2C0_SDA(0x0, 0x5) +#define I2C0_SDA_PA6 SILABS_DBUS_I2C0_SDA(0x0, 0x6) +#define I2C0_SDA_PA7 SILABS_DBUS_I2C0_SDA(0x0, 0x7) +#define I2C0_SDA_PA8 SILABS_DBUS_I2C0_SDA(0x0, 0x8) +#define I2C0_SDA_PB0 SILABS_DBUS_I2C0_SDA(0x1, 0x0) +#define I2C0_SDA_PB1 SILABS_DBUS_I2C0_SDA(0x1, 0x1) +#define I2C0_SDA_PB2 SILABS_DBUS_I2C0_SDA(0x1, 0x2) +#define I2C0_SDA_PB3 SILABS_DBUS_I2C0_SDA(0x1, 0x3) +#define I2C0_SDA_PB4 SILABS_DBUS_I2C0_SDA(0x1, 0x4) +#define I2C0_SDA_PC0 SILABS_DBUS_I2C0_SDA(0x2, 0x0) +#define I2C0_SDA_PC1 SILABS_DBUS_I2C0_SDA(0x2, 0x1) +#define I2C0_SDA_PC2 SILABS_DBUS_I2C0_SDA(0x2, 0x2) +#define I2C0_SDA_PC3 SILABS_DBUS_I2C0_SDA(0x2, 0x3) +#define I2C0_SDA_PC4 SILABS_DBUS_I2C0_SDA(0x2, 0x4) +#define I2C0_SDA_PC5 SILABS_DBUS_I2C0_SDA(0x2, 0x5) +#define I2C0_SDA_PC6 SILABS_DBUS_I2C0_SDA(0x2, 0x6) +#define I2C0_SDA_PC7 SILABS_DBUS_I2C0_SDA(0x2, 0x7) +#define I2C0_SDA_PD0 SILABS_DBUS_I2C0_SDA(0x3, 0x0) +#define I2C0_SDA_PD1 SILABS_DBUS_I2C0_SDA(0x3, 0x1) +#define I2C0_SDA_PD2 SILABS_DBUS_I2C0_SDA(0x3, 0x2) +#define I2C0_SDA_PD3 SILABS_DBUS_I2C0_SDA(0x3, 0x3) + +#define I2C1_SCL_PC0 SILABS_DBUS_I2C1_SCL(0x2, 0x0) +#define I2C1_SCL_PC1 SILABS_DBUS_I2C1_SCL(0x2, 0x1) +#define I2C1_SCL_PC2 SILABS_DBUS_I2C1_SCL(0x2, 0x2) +#define I2C1_SCL_PC3 SILABS_DBUS_I2C1_SCL(0x2, 0x3) +#define I2C1_SCL_PC4 SILABS_DBUS_I2C1_SCL(0x2, 0x4) +#define I2C1_SCL_PC5 SILABS_DBUS_I2C1_SCL(0x2, 0x5) +#define I2C1_SCL_PC6 SILABS_DBUS_I2C1_SCL(0x2, 0x6) +#define I2C1_SCL_PC7 SILABS_DBUS_I2C1_SCL(0x2, 0x7) +#define I2C1_SCL_PD0 SILABS_DBUS_I2C1_SCL(0x3, 0x0) +#define I2C1_SCL_PD1 SILABS_DBUS_I2C1_SCL(0x3, 0x1) +#define I2C1_SCL_PD2 SILABS_DBUS_I2C1_SCL(0x3, 0x2) +#define I2C1_SCL_PD3 SILABS_DBUS_I2C1_SCL(0x3, 0x3) +#define I2C1_SDA_PC0 SILABS_DBUS_I2C1_SDA(0x2, 0x0) +#define I2C1_SDA_PC1 SILABS_DBUS_I2C1_SDA(0x2, 0x1) +#define I2C1_SDA_PC2 SILABS_DBUS_I2C1_SDA(0x2, 0x2) +#define I2C1_SDA_PC3 SILABS_DBUS_I2C1_SDA(0x2, 0x3) +#define I2C1_SDA_PC4 SILABS_DBUS_I2C1_SDA(0x2, 0x4) +#define I2C1_SDA_PC5 SILABS_DBUS_I2C1_SDA(0x2, 0x5) +#define I2C1_SDA_PC6 SILABS_DBUS_I2C1_SDA(0x2, 0x6) +#define I2C1_SDA_PC7 SILABS_DBUS_I2C1_SDA(0x2, 0x7) +#define I2C1_SDA_PD0 SILABS_DBUS_I2C1_SDA(0x3, 0x0) +#define I2C1_SDA_PD1 SILABS_DBUS_I2C1_SDA(0x3, 0x1) +#define I2C1_SDA_PD2 SILABS_DBUS_I2C1_SDA(0x3, 0x2) +#define I2C1_SDA_PD3 SILABS_DBUS_I2C1_SDA(0x3, 0x3) + +#define LETIMER0_OUT0_PA0 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x0) +#define LETIMER0_OUT0_PA1 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x1) +#define LETIMER0_OUT0_PA2 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x2) +#define LETIMER0_OUT0_PA3 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x3) +#define LETIMER0_OUT0_PA4 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x4) +#define LETIMER0_OUT0_PA5 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x5) +#define LETIMER0_OUT0_PA6 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x6) +#define LETIMER0_OUT0_PA7 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x7) +#define LETIMER0_OUT0_PA8 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x8) +#define LETIMER0_OUT0_PB0 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x0) +#define LETIMER0_OUT0_PB1 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x1) +#define LETIMER0_OUT0_PB2 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x2) +#define LETIMER0_OUT0_PB3 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x3) +#define LETIMER0_OUT0_PB4 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x4) +#define LETIMER0_OUT1_PA0 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x0) +#define LETIMER0_OUT1_PA1 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x1) +#define LETIMER0_OUT1_PA2 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x2) +#define LETIMER0_OUT1_PA3 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x3) +#define LETIMER0_OUT1_PA4 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x4) +#define LETIMER0_OUT1_PA5 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x5) +#define LETIMER0_OUT1_PA6 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x6) +#define LETIMER0_OUT1_PA7 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x7) +#define LETIMER0_OUT1_PA8 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x8) +#define LETIMER0_OUT1_PB0 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x0) +#define LETIMER0_OUT1_PB1 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x1) +#define LETIMER0_OUT1_PB2 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x2) +#define LETIMER0_OUT1_PB3 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x3) +#define LETIMER0_OUT1_PB4 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x4) + +#define MODEM_ANT0_PA0 SILABS_DBUS_MODEM_ANT0(0x0, 0x0) +#define MODEM_ANT0_PA1 SILABS_DBUS_MODEM_ANT0(0x0, 0x1) +#define MODEM_ANT0_PA2 SILABS_DBUS_MODEM_ANT0(0x0, 0x2) +#define MODEM_ANT0_PA3 SILABS_DBUS_MODEM_ANT0(0x0, 0x3) +#define MODEM_ANT0_PA4 SILABS_DBUS_MODEM_ANT0(0x0, 0x4) +#define MODEM_ANT0_PA5 SILABS_DBUS_MODEM_ANT0(0x0, 0x5) +#define MODEM_ANT0_PA6 SILABS_DBUS_MODEM_ANT0(0x0, 0x6) +#define MODEM_ANT0_PA7 SILABS_DBUS_MODEM_ANT0(0x0, 0x7) +#define MODEM_ANT0_PA8 SILABS_DBUS_MODEM_ANT0(0x0, 0x8) +#define MODEM_ANT0_PB0 SILABS_DBUS_MODEM_ANT0(0x1, 0x0) +#define MODEM_ANT0_PB1 SILABS_DBUS_MODEM_ANT0(0x1, 0x1) +#define MODEM_ANT0_PB2 SILABS_DBUS_MODEM_ANT0(0x1, 0x2) +#define MODEM_ANT0_PB3 SILABS_DBUS_MODEM_ANT0(0x1, 0x3) +#define MODEM_ANT0_PB4 SILABS_DBUS_MODEM_ANT0(0x1, 0x4) +#define MODEM_ANT0_PC0 SILABS_DBUS_MODEM_ANT0(0x2, 0x0) +#define MODEM_ANT0_PC1 SILABS_DBUS_MODEM_ANT0(0x2, 0x1) +#define MODEM_ANT0_PC2 SILABS_DBUS_MODEM_ANT0(0x2, 0x2) +#define MODEM_ANT0_PC3 SILABS_DBUS_MODEM_ANT0(0x2, 0x3) +#define MODEM_ANT0_PC4 SILABS_DBUS_MODEM_ANT0(0x2, 0x4) +#define MODEM_ANT0_PC5 SILABS_DBUS_MODEM_ANT0(0x2, 0x5) +#define MODEM_ANT0_PC6 SILABS_DBUS_MODEM_ANT0(0x2, 0x6) +#define MODEM_ANT0_PC7 SILABS_DBUS_MODEM_ANT0(0x2, 0x7) +#define MODEM_ANT0_PD0 SILABS_DBUS_MODEM_ANT0(0x3, 0x0) +#define MODEM_ANT0_PD1 SILABS_DBUS_MODEM_ANT0(0x3, 0x1) +#define MODEM_ANT0_PD2 SILABS_DBUS_MODEM_ANT0(0x3, 0x2) +#define MODEM_ANT0_PD3 SILABS_DBUS_MODEM_ANT0(0x3, 0x3) +#define MODEM_ANT1_PA0 SILABS_DBUS_MODEM_ANT1(0x0, 0x0) +#define MODEM_ANT1_PA1 SILABS_DBUS_MODEM_ANT1(0x0, 0x1) +#define MODEM_ANT1_PA2 SILABS_DBUS_MODEM_ANT1(0x0, 0x2) +#define MODEM_ANT1_PA3 SILABS_DBUS_MODEM_ANT1(0x0, 0x3) +#define MODEM_ANT1_PA4 SILABS_DBUS_MODEM_ANT1(0x0, 0x4) +#define MODEM_ANT1_PA5 SILABS_DBUS_MODEM_ANT1(0x0, 0x5) +#define MODEM_ANT1_PA6 SILABS_DBUS_MODEM_ANT1(0x0, 0x6) +#define MODEM_ANT1_PA7 SILABS_DBUS_MODEM_ANT1(0x0, 0x7) +#define MODEM_ANT1_PA8 SILABS_DBUS_MODEM_ANT1(0x0, 0x8) +#define MODEM_ANT1_PB0 SILABS_DBUS_MODEM_ANT1(0x1, 0x0) +#define MODEM_ANT1_PB1 SILABS_DBUS_MODEM_ANT1(0x1, 0x1) +#define MODEM_ANT1_PB2 SILABS_DBUS_MODEM_ANT1(0x1, 0x2) +#define MODEM_ANT1_PB3 SILABS_DBUS_MODEM_ANT1(0x1, 0x3) +#define MODEM_ANT1_PB4 SILABS_DBUS_MODEM_ANT1(0x1, 0x4) +#define MODEM_ANT1_PC0 SILABS_DBUS_MODEM_ANT1(0x2, 0x0) +#define MODEM_ANT1_PC1 SILABS_DBUS_MODEM_ANT1(0x2, 0x1) +#define MODEM_ANT1_PC2 SILABS_DBUS_MODEM_ANT1(0x2, 0x2) +#define MODEM_ANT1_PC3 SILABS_DBUS_MODEM_ANT1(0x2, 0x3) +#define MODEM_ANT1_PC4 SILABS_DBUS_MODEM_ANT1(0x2, 0x4) +#define MODEM_ANT1_PC5 SILABS_DBUS_MODEM_ANT1(0x2, 0x5) +#define MODEM_ANT1_PC6 SILABS_DBUS_MODEM_ANT1(0x2, 0x6) +#define MODEM_ANT1_PC7 SILABS_DBUS_MODEM_ANT1(0x2, 0x7) +#define MODEM_ANT1_PD0 SILABS_DBUS_MODEM_ANT1(0x3, 0x0) +#define MODEM_ANT1_PD1 SILABS_DBUS_MODEM_ANT1(0x3, 0x1) +#define MODEM_ANT1_PD2 SILABS_DBUS_MODEM_ANT1(0x3, 0x2) +#define MODEM_ANT1_PD3 SILABS_DBUS_MODEM_ANT1(0x3, 0x3) +#define MODEM_ANTROLLOVER_PC0 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x0) +#define MODEM_ANTROLLOVER_PC1 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x1) +#define MODEM_ANTROLLOVER_PC2 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x2) +#define MODEM_ANTROLLOVER_PC3 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x3) +#define MODEM_ANTROLLOVER_PC4 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x4) +#define MODEM_ANTROLLOVER_PC5 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x5) +#define MODEM_ANTROLLOVER_PC6 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x6) +#define MODEM_ANTROLLOVER_PC7 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x7) +#define MODEM_ANTROLLOVER_PD0 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x0) +#define MODEM_ANTROLLOVER_PD1 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x1) +#define MODEM_ANTROLLOVER_PD2 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x2) +#define MODEM_ANTROLLOVER_PD3 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x3) +#define MODEM_ANTRR0_PC0 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x0) +#define MODEM_ANTRR0_PC1 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x1) +#define MODEM_ANTRR0_PC2 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x2) +#define MODEM_ANTRR0_PC3 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x3) +#define MODEM_ANTRR0_PC4 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x4) +#define MODEM_ANTRR0_PC5 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x5) +#define MODEM_ANTRR0_PC6 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x6) +#define MODEM_ANTRR0_PC7 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x7) +#define MODEM_ANTRR0_PD0 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x0) +#define MODEM_ANTRR0_PD1 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x1) +#define MODEM_ANTRR0_PD2 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x2) +#define MODEM_ANTRR0_PD3 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x3) +#define MODEM_ANTRR1_PC0 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x0) +#define MODEM_ANTRR1_PC1 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x1) +#define MODEM_ANTRR1_PC2 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x2) +#define MODEM_ANTRR1_PC3 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x3) +#define MODEM_ANTRR1_PC4 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x4) +#define MODEM_ANTRR1_PC5 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x5) +#define MODEM_ANTRR1_PC6 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x6) +#define MODEM_ANTRR1_PC7 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x7) +#define MODEM_ANTRR1_PD0 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x0) +#define MODEM_ANTRR1_PD1 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x1) +#define MODEM_ANTRR1_PD2 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x2) +#define MODEM_ANTRR1_PD3 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x3) +#define MODEM_ANTRR2_PC0 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x0) +#define MODEM_ANTRR2_PC1 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x1) +#define MODEM_ANTRR2_PC2 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x2) +#define MODEM_ANTRR2_PC3 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x3) +#define MODEM_ANTRR2_PC4 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x4) +#define MODEM_ANTRR2_PC5 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x5) +#define MODEM_ANTRR2_PC6 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x6) +#define MODEM_ANTRR2_PC7 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x7) +#define MODEM_ANTRR2_PD0 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x0) +#define MODEM_ANTRR2_PD1 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x1) +#define MODEM_ANTRR2_PD2 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x2) +#define MODEM_ANTRR2_PD3 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x3) +#define MODEM_ANTRR3_PC0 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x0) +#define MODEM_ANTRR3_PC1 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x1) +#define MODEM_ANTRR3_PC2 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x2) +#define MODEM_ANTRR3_PC3 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x3) +#define MODEM_ANTRR3_PC4 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x4) +#define MODEM_ANTRR3_PC5 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x5) +#define MODEM_ANTRR3_PC6 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x6) +#define MODEM_ANTRR3_PC7 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x7) +#define MODEM_ANTRR3_PD0 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x0) +#define MODEM_ANTRR3_PD1 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x1) +#define MODEM_ANTRR3_PD2 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x2) +#define MODEM_ANTRR3_PD3 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x3) +#define MODEM_ANTRR4_PC0 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x0) +#define MODEM_ANTRR4_PC1 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x1) +#define MODEM_ANTRR4_PC2 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x2) +#define MODEM_ANTRR4_PC3 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x3) +#define MODEM_ANTRR4_PC4 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x4) +#define MODEM_ANTRR4_PC5 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x5) +#define MODEM_ANTRR4_PC6 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x6) +#define MODEM_ANTRR4_PC7 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x7) +#define MODEM_ANTRR4_PD0 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x0) +#define MODEM_ANTRR4_PD1 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x1) +#define MODEM_ANTRR4_PD2 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x2) +#define MODEM_ANTRR4_PD3 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x3) +#define MODEM_ANTRR5_PC0 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x0) +#define MODEM_ANTRR5_PC1 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x1) +#define MODEM_ANTRR5_PC2 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x2) +#define MODEM_ANTRR5_PC3 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x3) +#define MODEM_ANTRR5_PC4 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x4) +#define MODEM_ANTRR5_PC5 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x5) +#define MODEM_ANTRR5_PC6 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x6) +#define MODEM_ANTRR5_PC7 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x7) +#define MODEM_ANTRR5_PD0 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x0) +#define MODEM_ANTRR5_PD1 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x1) +#define MODEM_ANTRR5_PD2 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x2) +#define MODEM_ANTRR5_PD3 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x3) +#define MODEM_ANTSWEN_PC0 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x0) +#define MODEM_ANTSWEN_PC1 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x1) +#define MODEM_ANTSWEN_PC2 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x2) +#define MODEM_ANTSWEN_PC3 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x3) +#define MODEM_ANTSWEN_PC4 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x4) +#define MODEM_ANTSWEN_PC5 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x5) +#define MODEM_ANTSWEN_PC6 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x6) +#define MODEM_ANTSWEN_PC7 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x7) +#define MODEM_ANTSWEN_PD0 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x0) +#define MODEM_ANTSWEN_PD1 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x1) +#define MODEM_ANTSWEN_PD2 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x2) +#define MODEM_ANTSWEN_PD3 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x3) +#define MODEM_ANTSWUS_PC0 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x0) +#define MODEM_ANTSWUS_PC1 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x1) +#define MODEM_ANTSWUS_PC2 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x2) +#define MODEM_ANTSWUS_PC3 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x3) +#define MODEM_ANTSWUS_PC4 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x4) +#define MODEM_ANTSWUS_PC5 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x5) +#define MODEM_ANTSWUS_PC6 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x6) +#define MODEM_ANTSWUS_PC7 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x7) +#define MODEM_ANTSWUS_PD0 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x0) +#define MODEM_ANTSWUS_PD1 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x1) +#define MODEM_ANTSWUS_PD2 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x2) +#define MODEM_ANTSWUS_PD3 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x3) +#define MODEM_ANTTRIG_PC0 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x0) +#define MODEM_ANTTRIG_PC1 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x1) +#define MODEM_ANTTRIG_PC2 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x2) +#define MODEM_ANTTRIG_PC3 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x3) +#define MODEM_ANTTRIG_PC4 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x4) +#define MODEM_ANTTRIG_PC5 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x5) +#define MODEM_ANTTRIG_PC6 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x6) +#define MODEM_ANTTRIG_PC7 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x7) +#define MODEM_ANTTRIG_PD0 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x0) +#define MODEM_ANTTRIG_PD1 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x1) +#define MODEM_ANTTRIG_PD2 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x2) +#define MODEM_ANTTRIG_PD3 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x3) +#define MODEM_ANTTRIGSTOP_PC0 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x0) +#define MODEM_ANTTRIGSTOP_PC1 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x1) +#define MODEM_ANTTRIGSTOP_PC2 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x2) +#define MODEM_ANTTRIGSTOP_PC3 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x3) +#define MODEM_ANTTRIGSTOP_PC4 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x4) +#define MODEM_ANTTRIGSTOP_PC5 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x5) +#define MODEM_ANTTRIGSTOP_PC6 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x6) +#define MODEM_ANTTRIGSTOP_PC7 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x7) +#define MODEM_ANTTRIGSTOP_PD0 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x0) +#define MODEM_ANTTRIGSTOP_PD1 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x1) +#define MODEM_ANTTRIGSTOP_PD2 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x2) +#define MODEM_ANTTRIGSTOP_PD3 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x3) +#define MODEM_DCLK_PA0 SILABS_DBUS_MODEM_DCLK(0x0, 0x0) +#define MODEM_DCLK_PA1 SILABS_DBUS_MODEM_DCLK(0x0, 0x1) +#define MODEM_DCLK_PA2 SILABS_DBUS_MODEM_DCLK(0x0, 0x2) +#define MODEM_DCLK_PA3 SILABS_DBUS_MODEM_DCLK(0x0, 0x3) +#define MODEM_DCLK_PA4 SILABS_DBUS_MODEM_DCLK(0x0, 0x4) +#define MODEM_DCLK_PA5 SILABS_DBUS_MODEM_DCLK(0x0, 0x5) +#define MODEM_DCLK_PA6 SILABS_DBUS_MODEM_DCLK(0x0, 0x6) +#define MODEM_DCLK_PA7 SILABS_DBUS_MODEM_DCLK(0x0, 0x7) +#define MODEM_DCLK_PA8 SILABS_DBUS_MODEM_DCLK(0x0, 0x8) +#define MODEM_DCLK_PB0 SILABS_DBUS_MODEM_DCLK(0x1, 0x0) +#define MODEM_DCLK_PB1 SILABS_DBUS_MODEM_DCLK(0x1, 0x1) +#define MODEM_DCLK_PB2 SILABS_DBUS_MODEM_DCLK(0x1, 0x2) +#define MODEM_DCLK_PB3 SILABS_DBUS_MODEM_DCLK(0x1, 0x3) +#define MODEM_DCLK_PB4 SILABS_DBUS_MODEM_DCLK(0x1, 0x4) +#define MODEM_DOUT_PA0 SILABS_DBUS_MODEM_DOUT(0x0, 0x0) +#define MODEM_DOUT_PA1 SILABS_DBUS_MODEM_DOUT(0x0, 0x1) +#define MODEM_DOUT_PA2 SILABS_DBUS_MODEM_DOUT(0x0, 0x2) +#define MODEM_DOUT_PA3 SILABS_DBUS_MODEM_DOUT(0x0, 0x3) +#define MODEM_DOUT_PA4 SILABS_DBUS_MODEM_DOUT(0x0, 0x4) +#define MODEM_DOUT_PA5 SILABS_DBUS_MODEM_DOUT(0x0, 0x5) +#define MODEM_DOUT_PA6 SILABS_DBUS_MODEM_DOUT(0x0, 0x6) +#define MODEM_DOUT_PA7 SILABS_DBUS_MODEM_DOUT(0x0, 0x7) +#define MODEM_DOUT_PA8 SILABS_DBUS_MODEM_DOUT(0x0, 0x8) +#define MODEM_DOUT_PB0 SILABS_DBUS_MODEM_DOUT(0x1, 0x0) +#define MODEM_DOUT_PB1 SILABS_DBUS_MODEM_DOUT(0x1, 0x1) +#define MODEM_DOUT_PB2 SILABS_DBUS_MODEM_DOUT(0x1, 0x2) +#define MODEM_DOUT_PB3 SILABS_DBUS_MODEM_DOUT(0x1, 0x3) +#define MODEM_DOUT_PB4 SILABS_DBUS_MODEM_DOUT(0x1, 0x4) +#define MODEM_DIN_PA0 SILABS_DBUS_MODEM_DIN(0x0, 0x0) +#define MODEM_DIN_PA1 SILABS_DBUS_MODEM_DIN(0x0, 0x1) +#define MODEM_DIN_PA2 SILABS_DBUS_MODEM_DIN(0x0, 0x2) +#define MODEM_DIN_PA3 SILABS_DBUS_MODEM_DIN(0x0, 0x3) +#define MODEM_DIN_PA4 SILABS_DBUS_MODEM_DIN(0x0, 0x4) +#define MODEM_DIN_PA5 SILABS_DBUS_MODEM_DIN(0x0, 0x5) +#define MODEM_DIN_PA6 SILABS_DBUS_MODEM_DIN(0x0, 0x6) +#define MODEM_DIN_PA7 SILABS_DBUS_MODEM_DIN(0x0, 0x7) +#define MODEM_DIN_PA8 SILABS_DBUS_MODEM_DIN(0x0, 0x8) +#define MODEM_DIN_PB0 SILABS_DBUS_MODEM_DIN(0x1, 0x0) +#define MODEM_DIN_PB1 SILABS_DBUS_MODEM_DIN(0x1, 0x1) +#define MODEM_DIN_PB2 SILABS_DBUS_MODEM_DIN(0x1, 0x2) +#define MODEM_DIN_PB3 SILABS_DBUS_MODEM_DIN(0x1, 0x3) +#define MODEM_DIN_PB4 SILABS_DBUS_MODEM_DIN(0x1, 0x4) + +#define PDM_CLK_PA0 SILABS_DBUS_PDM_CLK(0x0, 0x0) +#define PDM_CLK_PA1 SILABS_DBUS_PDM_CLK(0x0, 0x1) +#define PDM_CLK_PA2 SILABS_DBUS_PDM_CLK(0x0, 0x2) +#define PDM_CLK_PA3 SILABS_DBUS_PDM_CLK(0x0, 0x3) +#define PDM_CLK_PA4 SILABS_DBUS_PDM_CLK(0x0, 0x4) +#define PDM_CLK_PA5 SILABS_DBUS_PDM_CLK(0x0, 0x5) +#define PDM_CLK_PA6 SILABS_DBUS_PDM_CLK(0x0, 0x6) +#define PDM_CLK_PA7 SILABS_DBUS_PDM_CLK(0x0, 0x7) +#define PDM_CLK_PA8 SILABS_DBUS_PDM_CLK(0x0, 0x8) +#define PDM_CLK_PB0 SILABS_DBUS_PDM_CLK(0x1, 0x0) +#define PDM_CLK_PB1 SILABS_DBUS_PDM_CLK(0x1, 0x1) +#define PDM_CLK_PB2 SILABS_DBUS_PDM_CLK(0x1, 0x2) +#define PDM_CLK_PB3 SILABS_DBUS_PDM_CLK(0x1, 0x3) +#define PDM_CLK_PB4 SILABS_DBUS_PDM_CLK(0x1, 0x4) +#define PDM_CLK_PC0 SILABS_DBUS_PDM_CLK(0x2, 0x0) +#define PDM_CLK_PC1 SILABS_DBUS_PDM_CLK(0x2, 0x1) +#define PDM_CLK_PC2 SILABS_DBUS_PDM_CLK(0x2, 0x2) +#define PDM_CLK_PC3 SILABS_DBUS_PDM_CLK(0x2, 0x3) +#define PDM_CLK_PC4 SILABS_DBUS_PDM_CLK(0x2, 0x4) +#define PDM_CLK_PC5 SILABS_DBUS_PDM_CLK(0x2, 0x5) +#define PDM_CLK_PC6 SILABS_DBUS_PDM_CLK(0x2, 0x6) +#define PDM_CLK_PC7 SILABS_DBUS_PDM_CLK(0x2, 0x7) +#define PDM_CLK_PD0 SILABS_DBUS_PDM_CLK(0x3, 0x0) +#define PDM_CLK_PD1 SILABS_DBUS_PDM_CLK(0x3, 0x1) +#define PDM_CLK_PD2 SILABS_DBUS_PDM_CLK(0x3, 0x2) +#define PDM_CLK_PD3 SILABS_DBUS_PDM_CLK(0x3, 0x3) +#define PDM_DAT0_PA0 SILABS_DBUS_PDM_DAT0(0x0, 0x0) +#define PDM_DAT0_PA1 SILABS_DBUS_PDM_DAT0(0x0, 0x1) +#define PDM_DAT0_PA2 SILABS_DBUS_PDM_DAT0(0x0, 0x2) +#define PDM_DAT0_PA3 SILABS_DBUS_PDM_DAT0(0x0, 0x3) +#define PDM_DAT0_PA4 SILABS_DBUS_PDM_DAT0(0x0, 0x4) +#define PDM_DAT0_PA5 SILABS_DBUS_PDM_DAT0(0x0, 0x5) +#define PDM_DAT0_PA6 SILABS_DBUS_PDM_DAT0(0x0, 0x6) +#define PDM_DAT0_PA7 SILABS_DBUS_PDM_DAT0(0x0, 0x7) +#define PDM_DAT0_PA8 SILABS_DBUS_PDM_DAT0(0x0, 0x8) +#define PDM_DAT0_PB0 SILABS_DBUS_PDM_DAT0(0x1, 0x0) +#define PDM_DAT0_PB1 SILABS_DBUS_PDM_DAT0(0x1, 0x1) +#define PDM_DAT0_PB2 SILABS_DBUS_PDM_DAT0(0x1, 0x2) +#define PDM_DAT0_PB3 SILABS_DBUS_PDM_DAT0(0x1, 0x3) +#define PDM_DAT0_PB4 SILABS_DBUS_PDM_DAT0(0x1, 0x4) +#define PDM_DAT0_PC0 SILABS_DBUS_PDM_DAT0(0x2, 0x0) +#define PDM_DAT0_PC1 SILABS_DBUS_PDM_DAT0(0x2, 0x1) +#define PDM_DAT0_PC2 SILABS_DBUS_PDM_DAT0(0x2, 0x2) +#define PDM_DAT0_PC3 SILABS_DBUS_PDM_DAT0(0x2, 0x3) +#define PDM_DAT0_PC4 SILABS_DBUS_PDM_DAT0(0x2, 0x4) +#define PDM_DAT0_PC5 SILABS_DBUS_PDM_DAT0(0x2, 0x5) +#define PDM_DAT0_PC6 SILABS_DBUS_PDM_DAT0(0x2, 0x6) +#define PDM_DAT0_PC7 SILABS_DBUS_PDM_DAT0(0x2, 0x7) +#define PDM_DAT0_PD0 SILABS_DBUS_PDM_DAT0(0x3, 0x0) +#define PDM_DAT0_PD1 SILABS_DBUS_PDM_DAT0(0x3, 0x1) +#define PDM_DAT0_PD2 SILABS_DBUS_PDM_DAT0(0x3, 0x2) +#define PDM_DAT0_PD3 SILABS_DBUS_PDM_DAT0(0x3, 0x3) +#define PDM_DAT1_PA0 SILABS_DBUS_PDM_DAT1(0x0, 0x0) +#define PDM_DAT1_PA1 SILABS_DBUS_PDM_DAT1(0x0, 0x1) +#define PDM_DAT1_PA2 SILABS_DBUS_PDM_DAT1(0x0, 0x2) +#define PDM_DAT1_PA3 SILABS_DBUS_PDM_DAT1(0x0, 0x3) +#define PDM_DAT1_PA4 SILABS_DBUS_PDM_DAT1(0x0, 0x4) +#define PDM_DAT1_PA5 SILABS_DBUS_PDM_DAT1(0x0, 0x5) +#define PDM_DAT1_PA6 SILABS_DBUS_PDM_DAT1(0x0, 0x6) +#define PDM_DAT1_PA7 SILABS_DBUS_PDM_DAT1(0x0, 0x7) +#define PDM_DAT1_PA8 SILABS_DBUS_PDM_DAT1(0x0, 0x8) +#define PDM_DAT1_PB0 SILABS_DBUS_PDM_DAT1(0x1, 0x0) +#define PDM_DAT1_PB1 SILABS_DBUS_PDM_DAT1(0x1, 0x1) +#define PDM_DAT1_PB2 SILABS_DBUS_PDM_DAT1(0x1, 0x2) +#define PDM_DAT1_PB3 SILABS_DBUS_PDM_DAT1(0x1, 0x3) +#define PDM_DAT1_PB4 SILABS_DBUS_PDM_DAT1(0x1, 0x4) +#define PDM_DAT1_PC0 SILABS_DBUS_PDM_DAT1(0x2, 0x0) +#define PDM_DAT1_PC1 SILABS_DBUS_PDM_DAT1(0x2, 0x1) +#define PDM_DAT1_PC2 SILABS_DBUS_PDM_DAT1(0x2, 0x2) +#define PDM_DAT1_PC3 SILABS_DBUS_PDM_DAT1(0x2, 0x3) +#define PDM_DAT1_PC4 SILABS_DBUS_PDM_DAT1(0x2, 0x4) +#define PDM_DAT1_PC5 SILABS_DBUS_PDM_DAT1(0x2, 0x5) +#define PDM_DAT1_PC6 SILABS_DBUS_PDM_DAT1(0x2, 0x6) +#define PDM_DAT1_PC7 SILABS_DBUS_PDM_DAT1(0x2, 0x7) +#define PDM_DAT1_PD0 SILABS_DBUS_PDM_DAT1(0x3, 0x0) +#define PDM_DAT1_PD1 SILABS_DBUS_PDM_DAT1(0x3, 0x1) +#define PDM_DAT1_PD2 SILABS_DBUS_PDM_DAT1(0x3, 0x2) +#define PDM_DAT1_PD3 SILABS_DBUS_PDM_DAT1(0x3, 0x3) + +#define PRS0_ASYNCH0_PA0 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x0) +#define PRS0_ASYNCH0_PA1 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x1) +#define PRS0_ASYNCH0_PA2 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x2) +#define PRS0_ASYNCH0_PA3 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x3) +#define PRS0_ASYNCH0_PA4 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x4) +#define PRS0_ASYNCH0_PA5 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x5) +#define PRS0_ASYNCH0_PA6 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x6) +#define PRS0_ASYNCH0_PA7 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x7) +#define PRS0_ASYNCH0_PA8 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x8) +#define PRS0_ASYNCH0_PB0 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x0) +#define PRS0_ASYNCH0_PB1 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x1) +#define PRS0_ASYNCH0_PB2 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x2) +#define PRS0_ASYNCH0_PB3 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x3) +#define PRS0_ASYNCH0_PB4 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x4) +#define PRS0_ASYNCH1_PA0 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x0) +#define PRS0_ASYNCH1_PA1 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x1) +#define PRS0_ASYNCH1_PA2 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x2) +#define PRS0_ASYNCH1_PA3 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x3) +#define PRS0_ASYNCH1_PA4 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x4) +#define PRS0_ASYNCH1_PA5 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x5) +#define PRS0_ASYNCH1_PA6 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x6) +#define PRS0_ASYNCH1_PA7 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x7) +#define PRS0_ASYNCH1_PA8 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x8) +#define PRS0_ASYNCH1_PB0 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x0) +#define PRS0_ASYNCH1_PB1 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x1) +#define PRS0_ASYNCH1_PB2 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x2) +#define PRS0_ASYNCH1_PB3 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x3) +#define PRS0_ASYNCH1_PB4 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x4) +#define PRS0_ASYNCH2_PA0 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x0) +#define PRS0_ASYNCH2_PA1 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x1) +#define PRS0_ASYNCH2_PA2 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x2) +#define PRS0_ASYNCH2_PA3 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x3) +#define PRS0_ASYNCH2_PA4 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x4) +#define PRS0_ASYNCH2_PA5 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x5) +#define PRS0_ASYNCH2_PA6 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x6) +#define PRS0_ASYNCH2_PA7 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x7) +#define PRS0_ASYNCH2_PA8 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x8) +#define PRS0_ASYNCH2_PB0 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x0) +#define PRS0_ASYNCH2_PB1 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x1) +#define PRS0_ASYNCH2_PB2 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x2) +#define PRS0_ASYNCH2_PB3 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x3) +#define PRS0_ASYNCH2_PB4 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x4) +#define PRS0_ASYNCH3_PA0 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x0) +#define PRS0_ASYNCH3_PA1 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x1) +#define PRS0_ASYNCH3_PA2 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x2) +#define PRS0_ASYNCH3_PA3 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x3) +#define PRS0_ASYNCH3_PA4 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x4) +#define PRS0_ASYNCH3_PA5 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x5) +#define PRS0_ASYNCH3_PA6 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x6) +#define PRS0_ASYNCH3_PA7 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x7) +#define PRS0_ASYNCH3_PA8 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x8) +#define PRS0_ASYNCH3_PB0 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x0) +#define PRS0_ASYNCH3_PB1 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x1) +#define PRS0_ASYNCH3_PB2 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x2) +#define PRS0_ASYNCH3_PB3 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x3) +#define PRS0_ASYNCH3_PB4 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x4) +#define PRS0_ASYNCH4_PA0 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x0) +#define PRS0_ASYNCH4_PA1 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x1) +#define PRS0_ASYNCH4_PA2 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x2) +#define PRS0_ASYNCH4_PA3 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x3) +#define PRS0_ASYNCH4_PA4 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x4) +#define PRS0_ASYNCH4_PA5 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x5) +#define PRS0_ASYNCH4_PA6 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x6) +#define PRS0_ASYNCH4_PA7 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x7) +#define PRS0_ASYNCH4_PA8 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x8) +#define PRS0_ASYNCH4_PB0 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x0) +#define PRS0_ASYNCH4_PB1 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x1) +#define PRS0_ASYNCH4_PB2 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x2) +#define PRS0_ASYNCH4_PB3 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x3) +#define PRS0_ASYNCH4_PB4 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x4) +#define PRS0_ASYNCH5_PA0 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x0) +#define PRS0_ASYNCH5_PA1 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x1) +#define PRS0_ASYNCH5_PA2 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x2) +#define PRS0_ASYNCH5_PA3 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x3) +#define PRS0_ASYNCH5_PA4 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x4) +#define PRS0_ASYNCH5_PA5 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x5) +#define PRS0_ASYNCH5_PA6 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x6) +#define PRS0_ASYNCH5_PA7 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x7) +#define PRS0_ASYNCH5_PA8 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x8) +#define PRS0_ASYNCH5_PB0 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x0) +#define PRS0_ASYNCH5_PB1 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x1) +#define PRS0_ASYNCH5_PB2 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x2) +#define PRS0_ASYNCH5_PB3 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x3) +#define PRS0_ASYNCH5_PB4 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x4) +#define PRS0_ASYNCH6_PC0 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x0) +#define PRS0_ASYNCH6_PC1 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x1) +#define PRS0_ASYNCH6_PC2 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x2) +#define PRS0_ASYNCH6_PC3 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x3) +#define PRS0_ASYNCH6_PC4 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x4) +#define PRS0_ASYNCH6_PC5 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x5) +#define PRS0_ASYNCH6_PC6 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x6) +#define PRS0_ASYNCH6_PC7 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x7) +#define PRS0_ASYNCH6_PD0 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x0) +#define PRS0_ASYNCH6_PD1 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x1) +#define PRS0_ASYNCH6_PD2 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x2) +#define PRS0_ASYNCH6_PD3 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x3) +#define PRS0_ASYNCH7_PC0 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x0) +#define PRS0_ASYNCH7_PC1 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x1) +#define PRS0_ASYNCH7_PC2 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x2) +#define PRS0_ASYNCH7_PC3 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x3) +#define PRS0_ASYNCH7_PC4 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x4) +#define PRS0_ASYNCH7_PC5 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x5) +#define PRS0_ASYNCH7_PC6 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x6) +#define PRS0_ASYNCH7_PC7 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x7) +#define PRS0_ASYNCH7_PD0 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x0) +#define PRS0_ASYNCH7_PD1 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x1) +#define PRS0_ASYNCH7_PD2 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x2) +#define PRS0_ASYNCH7_PD3 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x3) +#define PRS0_ASYNCH8_PC0 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x0) +#define PRS0_ASYNCH8_PC1 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x1) +#define PRS0_ASYNCH8_PC2 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x2) +#define PRS0_ASYNCH8_PC3 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x3) +#define PRS0_ASYNCH8_PC4 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x4) +#define PRS0_ASYNCH8_PC5 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x5) +#define PRS0_ASYNCH8_PC6 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x6) +#define PRS0_ASYNCH8_PC7 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x7) +#define PRS0_ASYNCH8_PD0 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x0) +#define PRS0_ASYNCH8_PD1 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x1) +#define PRS0_ASYNCH8_PD2 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x2) +#define PRS0_ASYNCH8_PD3 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x3) +#define PRS0_ASYNCH9_PC0 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x0) +#define PRS0_ASYNCH9_PC1 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x1) +#define PRS0_ASYNCH9_PC2 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x2) +#define PRS0_ASYNCH9_PC3 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x3) +#define PRS0_ASYNCH9_PC4 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x4) +#define PRS0_ASYNCH9_PC5 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x5) +#define PRS0_ASYNCH9_PC6 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x6) +#define PRS0_ASYNCH9_PC7 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x7) +#define PRS0_ASYNCH9_PD0 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x0) +#define PRS0_ASYNCH9_PD1 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x1) +#define PRS0_ASYNCH9_PD2 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x2) +#define PRS0_ASYNCH9_PD3 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x3) +#define PRS0_ASYNCH10_PC0 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x0) +#define PRS0_ASYNCH10_PC1 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x1) +#define PRS0_ASYNCH10_PC2 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x2) +#define PRS0_ASYNCH10_PC3 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x3) +#define PRS0_ASYNCH10_PC4 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x4) +#define PRS0_ASYNCH10_PC5 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x5) +#define PRS0_ASYNCH10_PC6 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x6) +#define PRS0_ASYNCH10_PC7 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x7) +#define PRS0_ASYNCH10_PD0 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x0) +#define PRS0_ASYNCH10_PD1 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x1) +#define PRS0_ASYNCH10_PD2 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x2) +#define PRS0_ASYNCH10_PD3 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x3) +#define PRS0_ASYNCH11_PC0 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x0) +#define PRS0_ASYNCH11_PC1 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x1) +#define PRS0_ASYNCH11_PC2 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x2) +#define PRS0_ASYNCH11_PC3 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x3) +#define PRS0_ASYNCH11_PC4 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x4) +#define PRS0_ASYNCH11_PC5 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x5) +#define PRS0_ASYNCH11_PC6 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x6) +#define PRS0_ASYNCH11_PC7 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x7) +#define PRS0_ASYNCH11_PD0 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x0) +#define PRS0_ASYNCH11_PD1 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x1) +#define PRS0_ASYNCH11_PD2 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x2) +#define PRS0_ASYNCH11_PD3 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x3) +#define PRS0_SYNCH0_PA0 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x0) +#define PRS0_SYNCH0_PA1 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x1) +#define PRS0_SYNCH0_PA2 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x2) +#define PRS0_SYNCH0_PA3 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x3) +#define PRS0_SYNCH0_PA4 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x4) +#define PRS0_SYNCH0_PA5 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x5) +#define PRS0_SYNCH0_PA6 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x6) +#define PRS0_SYNCH0_PA7 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x7) +#define PRS0_SYNCH0_PA8 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x8) +#define PRS0_SYNCH0_PB0 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x0) +#define PRS0_SYNCH0_PB1 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x1) +#define PRS0_SYNCH0_PB2 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x2) +#define PRS0_SYNCH0_PB3 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x3) +#define PRS0_SYNCH0_PB4 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x4) +#define PRS0_SYNCH0_PC0 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x0) +#define PRS0_SYNCH0_PC1 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x1) +#define PRS0_SYNCH0_PC2 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x2) +#define PRS0_SYNCH0_PC3 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x3) +#define PRS0_SYNCH0_PC4 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x4) +#define PRS0_SYNCH0_PC5 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x5) +#define PRS0_SYNCH0_PC6 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x6) +#define PRS0_SYNCH0_PC7 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x7) +#define PRS0_SYNCH0_PD0 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x0) +#define PRS0_SYNCH0_PD1 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x1) +#define PRS0_SYNCH0_PD2 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x2) +#define PRS0_SYNCH0_PD3 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x3) +#define PRS0_SYNCH1_PA0 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x0) +#define PRS0_SYNCH1_PA1 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x1) +#define PRS0_SYNCH1_PA2 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x2) +#define PRS0_SYNCH1_PA3 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x3) +#define PRS0_SYNCH1_PA4 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x4) +#define PRS0_SYNCH1_PA5 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x5) +#define PRS0_SYNCH1_PA6 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x6) +#define PRS0_SYNCH1_PA7 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x7) +#define PRS0_SYNCH1_PA8 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x8) +#define PRS0_SYNCH1_PB0 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x0) +#define PRS0_SYNCH1_PB1 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x1) +#define PRS0_SYNCH1_PB2 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x2) +#define PRS0_SYNCH1_PB3 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x3) +#define PRS0_SYNCH1_PB4 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x4) +#define PRS0_SYNCH1_PC0 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x0) +#define PRS0_SYNCH1_PC1 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x1) +#define PRS0_SYNCH1_PC2 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x2) +#define PRS0_SYNCH1_PC3 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x3) +#define PRS0_SYNCH1_PC4 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x4) +#define PRS0_SYNCH1_PC5 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x5) +#define PRS0_SYNCH1_PC6 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x6) +#define PRS0_SYNCH1_PC7 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x7) +#define PRS0_SYNCH1_PD0 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x0) +#define PRS0_SYNCH1_PD1 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x1) +#define PRS0_SYNCH1_PD2 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x2) +#define PRS0_SYNCH1_PD3 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x3) +#define PRS0_SYNCH2_PA0 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x0) +#define PRS0_SYNCH2_PA1 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x1) +#define PRS0_SYNCH2_PA2 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x2) +#define PRS0_SYNCH2_PA3 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x3) +#define PRS0_SYNCH2_PA4 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x4) +#define PRS0_SYNCH2_PA5 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x5) +#define PRS0_SYNCH2_PA6 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x6) +#define PRS0_SYNCH2_PA7 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x7) +#define PRS0_SYNCH2_PA8 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x8) +#define PRS0_SYNCH2_PB0 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x0) +#define PRS0_SYNCH2_PB1 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x1) +#define PRS0_SYNCH2_PB2 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x2) +#define PRS0_SYNCH2_PB3 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x3) +#define PRS0_SYNCH2_PB4 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x4) +#define PRS0_SYNCH2_PC0 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x0) +#define PRS0_SYNCH2_PC1 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x1) +#define PRS0_SYNCH2_PC2 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x2) +#define PRS0_SYNCH2_PC3 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x3) +#define PRS0_SYNCH2_PC4 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x4) +#define PRS0_SYNCH2_PC5 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x5) +#define PRS0_SYNCH2_PC6 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x6) +#define PRS0_SYNCH2_PC7 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x7) +#define PRS0_SYNCH2_PD0 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x0) +#define PRS0_SYNCH2_PD1 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x1) +#define PRS0_SYNCH2_PD2 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x2) +#define PRS0_SYNCH2_PD3 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x3) +#define PRS0_SYNCH3_PA0 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x0) +#define PRS0_SYNCH3_PA1 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x1) +#define PRS0_SYNCH3_PA2 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x2) +#define PRS0_SYNCH3_PA3 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x3) +#define PRS0_SYNCH3_PA4 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x4) +#define PRS0_SYNCH3_PA5 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x5) +#define PRS0_SYNCH3_PA6 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x6) +#define PRS0_SYNCH3_PA7 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x7) +#define PRS0_SYNCH3_PA8 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x8) +#define PRS0_SYNCH3_PB0 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x0) +#define PRS0_SYNCH3_PB1 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x1) +#define PRS0_SYNCH3_PB2 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x2) +#define PRS0_SYNCH3_PB3 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x3) +#define PRS0_SYNCH3_PB4 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x4) +#define PRS0_SYNCH3_PC0 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x0) +#define PRS0_SYNCH3_PC1 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x1) +#define PRS0_SYNCH3_PC2 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x2) +#define PRS0_SYNCH3_PC3 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x3) +#define PRS0_SYNCH3_PC4 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x4) +#define PRS0_SYNCH3_PC5 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x5) +#define PRS0_SYNCH3_PC6 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x6) +#define PRS0_SYNCH3_PC7 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x7) +#define PRS0_SYNCH3_PD0 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x0) +#define PRS0_SYNCH3_PD1 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x1) +#define PRS0_SYNCH3_PD2 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x2) +#define PRS0_SYNCH3_PD3 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x3) + +#define TIMER0_CC0_PA0 SILABS_DBUS_TIMER0_CC0(0x0, 0x0) +#define TIMER0_CC0_PA1 SILABS_DBUS_TIMER0_CC0(0x0, 0x1) +#define TIMER0_CC0_PA2 SILABS_DBUS_TIMER0_CC0(0x0, 0x2) +#define TIMER0_CC0_PA3 SILABS_DBUS_TIMER0_CC0(0x0, 0x3) +#define TIMER0_CC0_PA4 SILABS_DBUS_TIMER0_CC0(0x0, 0x4) +#define TIMER0_CC0_PA5 SILABS_DBUS_TIMER0_CC0(0x0, 0x5) +#define TIMER0_CC0_PA6 SILABS_DBUS_TIMER0_CC0(0x0, 0x6) +#define TIMER0_CC0_PA7 SILABS_DBUS_TIMER0_CC0(0x0, 0x7) +#define TIMER0_CC0_PA8 SILABS_DBUS_TIMER0_CC0(0x0, 0x8) +#define TIMER0_CC0_PB0 SILABS_DBUS_TIMER0_CC0(0x1, 0x0) +#define TIMER0_CC0_PB1 SILABS_DBUS_TIMER0_CC0(0x1, 0x1) +#define TIMER0_CC0_PB2 SILABS_DBUS_TIMER0_CC0(0x1, 0x2) +#define TIMER0_CC0_PB3 SILABS_DBUS_TIMER0_CC0(0x1, 0x3) +#define TIMER0_CC0_PB4 SILABS_DBUS_TIMER0_CC0(0x1, 0x4) +#define TIMER0_CC0_PC0 SILABS_DBUS_TIMER0_CC0(0x2, 0x0) +#define TIMER0_CC0_PC1 SILABS_DBUS_TIMER0_CC0(0x2, 0x1) +#define TIMER0_CC0_PC2 SILABS_DBUS_TIMER0_CC0(0x2, 0x2) +#define TIMER0_CC0_PC3 SILABS_DBUS_TIMER0_CC0(0x2, 0x3) +#define TIMER0_CC0_PC4 SILABS_DBUS_TIMER0_CC0(0x2, 0x4) +#define TIMER0_CC0_PC5 SILABS_DBUS_TIMER0_CC0(0x2, 0x5) +#define TIMER0_CC0_PC6 SILABS_DBUS_TIMER0_CC0(0x2, 0x6) +#define TIMER0_CC0_PC7 SILABS_DBUS_TIMER0_CC0(0x2, 0x7) +#define TIMER0_CC0_PD0 SILABS_DBUS_TIMER0_CC0(0x3, 0x0) +#define TIMER0_CC0_PD1 SILABS_DBUS_TIMER0_CC0(0x3, 0x1) +#define TIMER0_CC0_PD2 SILABS_DBUS_TIMER0_CC0(0x3, 0x2) +#define TIMER0_CC0_PD3 SILABS_DBUS_TIMER0_CC0(0x3, 0x3) +#define TIMER0_CC1_PA0 SILABS_DBUS_TIMER0_CC1(0x0, 0x0) +#define TIMER0_CC1_PA1 SILABS_DBUS_TIMER0_CC1(0x0, 0x1) +#define TIMER0_CC1_PA2 SILABS_DBUS_TIMER0_CC1(0x0, 0x2) +#define TIMER0_CC1_PA3 SILABS_DBUS_TIMER0_CC1(0x0, 0x3) +#define TIMER0_CC1_PA4 SILABS_DBUS_TIMER0_CC1(0x0, 0x4) +#define TIMER0_CC1_PA5 SILABS_DBUS_TIMER0_CC1(0x0, 0x5) +#define TIMER0_CC1_PA6 SILABS_DBUS_TIMER0_CC1(0x0, 0x6) +#define TIMER0_CC1_PA7 SILABS_DBUS_TIMER0_CC1(0x0, 0x7) +#define TIMER0_CC1_PA8 SILABS_DBUS_TIMER0_CC1(0x0, 0x8) +#define TIMER0_CC1_PB0 SILABS_DBUS_TIMER0_CC1(0x1, 0x0) +#define TIMER0_CC1_PB1 SILABS_DBUS_TIMER0_CC1(0x1, 0x1) +#define TIMER0_CC1_PB2 SILABS_DBUS_TIMER0_CC1(0x1, 0x2) +#define TIMER0_CC1_PB3 SILABS_DBUS_TIMER0_CC1(0x1, 0x3) +#define TIMER0_CC1_PB4 SILABS_DBUS_TIMER0_CC1(0x1, 0x4) +#define TIMER0_CC1_PC0 SILABS_DBUS_TIMER0_CC1(0x2, 0x0) +#define TIMER0_CC1_PC1 SILABS_DBUS_TIMER0_CC1(0x2, 0x1) +#define TIMER0_CC1_PC2 SILABS_DBUS_TIMER0_CC1(0x2, 0x2) +#define TIMER0_CC1_PC3 SILABS_DBUS_TIMER0_CC1(0x2, 0x3) +#define TIMER0_CC1_PC4 SILABS_DBUS_TIMER0_CC1(0x2, 0x4) +#define TIMER0_CC1_PC5 SILABS_DBUS_TIMER0_CC1(0x2, 0x5) +#define TIMER0_CC1_PC6 SILABS_DBUS_TIMER0_CC1(0x2, 0x6) +#define TIMER0_CC1_PC7 SILABS_DBUS_TIMER0_CC1(0x2, 0x7) +#define TIMER0_CC1_PD0 SILABS_DBUS_TIMER0_CC1(0x3, 0x0) +#define TIMER0_CC1_PD1 SILABS_DBUS_TIMER0_CC1(0x3, 0x1) +#define TIMER0_CC1_PD2 SILABS_DBUS_TIMER0_CC1(0x3, 0x2) +#define TIMER0_CC1_PD3 SILABS_DBUS_TIMER0_CC1(0x3, 0x3) +#define TIMER0_CC2_PA0 SILABS_DBUS_TIMER0_CC2(0x0, 0x0) +#define TIMER0_CC2_PA1 SILABS_DBUS_TIMER0_CC2(0x0, 0x1) +#define TIMER0_CC2_PA2 SILABS_DBUS_TIMER0_CC2(0x0, 0x2) +#define TIMER0_CC2_PA3 SILABS_DBUS_TIMER0_CC2(0x0, 0x3) +#define TIMER0_CC2_PA4 SILABS_DBUS_TIMER0_CC2(0x0, 0x4) +#define TIMER0_CC2_PA5 SILABS_DBUS_TIMER0_CC2(0x0, 0x5) +#define TIMER0_CC2_PA6 SILABS_DBUS_TIMER0_CC2(0x0, 0x6) +#define TIMER0_CC2_PA7 SILABS_DBUS_TIMER0_CC2(0x0, 0x7) +#define TIMER0_CC2_PA8 SILABS_DBUS_TIMER0_CC2(0x0, 0x8) +#define TIMER0_CC2_PB0 SILABS_DBUS_TIMER0_CC2(0x1, 0x0) +#define TIMER0_CC2_PB1 SILABS_DBUS_TIMER0_CC2(0x1, 0x1) +#define TIMER0_CC2_PB2 SILABS_DBUS_TIMER0_CC2(0x1, 0x2) +#define TIMER0_CC2_PB3 SILABS_DBUS_TIMER0_CC2(0x1, 0x3) +#define TIMER0_CC2_PB4 SILABS_DBUS_TIMER0_CC2(0x1, 0x4) +#define TIMER0_CC2_PC0 SILABS_DBUS_TIMER0_CC2(0x2, 0x0) +#define TIMER0_CC2_PC1 SILABS_DBUS_TIMER0_CC2(0x2, 0x1) +#define TIMER0_CC2_PC2 SILABS_DBUS_TIMER0_CC2(0x2, 0x2) +#define TIMER0_CC2_PC3 SILABS_DBUS_TIMER0_CC2(0x2, 0x3) +#define TIMER0_CC2_PC4 SILABS_DBUS_TIMER0_CC2(0x2, 0x4) +#define TIMER0_CC2_PC5 SILABS_DBUS_TIMER0_CC2(0x2, 0x5) +#define TIMER0_CC2_PC6 SILABS_DBUS_TIMER0_CC2(0x2, 0x6) +#define TIMER0_CC2_PC7 SILABS_DBUS_TIMER0_CC2(0x2, 0x7) +#define TIMER0_CC2_PD0 SILABS_DBUS_TIMER0_CC2(0x3, 0x0) +#define TIMER0_CC2_PD1 SILABS_DBUS_TIMER0_CC2(0x3, 0x1) +#define TIMER0_CC2_PD2 SILABS_DBUS_TIMER0_CC2(0x3, 0x2) +#define TIMER0_CC2_PD3 SILABS_DBUS_TIMER0_CC2(0x3, 0x3) +#define TIMER0_CDTI0_PA0 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x0) +#define TIMER0_CDTI0_PA1 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x1) +#define TIMER0_CDTI0_PA2 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x2) +#define TIMER0_CDTI0_PA3 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x3) +#define TIMER0_CDTI0_PA4 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x4) +#define TIMER0_CDTI0_PA5 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x5) +#define TIMER0_CDTI0_PA6 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x6) +#define TIMER0_CDTI0_PA7 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x7) +#define TIMER0_CDTI0_PA8 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x8) +#define TIMER0_CDTI0_PB0 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x0) +#define TIMER0_CDTI0_PB1 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x1) +#define TIMER0_CDTI0_PB2 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x2) +#define TIMER0_CDTI0_PB3 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x3) +#define TIMER0_CDTI0_PB4 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x4) +#define TIMER0_CDTI0_PC0 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x0) +#define TIMER0_CDTI0_PC1 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x1) +#define TIMER0_CDTI0_PC2 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x2) +#define TIMER0_CDTI0_PC3 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x3) +#define TIMER0_CDTI0_PC4 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x4) +#define TIMER0_CDTI0_PC5 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x5) +#define TIMER0_CDTI0_PC6 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x6) +#define TIMER0_CDTI0_PC7 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x7) +#define TIMER0_CDTI0_PD0 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x0) +#define TIMER0_CDTI0_PD1 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x1) +#define TIMER0_CDTI0_PD2 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x2) +#define TIMER0_CDTI0_PD3 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x3) +#define TIMER0_CDTI1_PA0 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x0) +#define TIMER0_CDTI1_PA1 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x1) +#define TIMER0_CDTI1_PA2 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x2) +#define TIMER0_CDTI1_PA3 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x3) +#define TIMER0_CDTI1_PA4 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x4) +#define TIMER0_CDTI1_PA5 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x5) +#define TIMER0_CDTI1_PA6 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x6) +#define TIMER0_CDTI1_PA7 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x7) +#define TIMER0_CDTI1_PA8 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x8) +#define TIMER0_CDTI1_PB0 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x0) +#define TIMER0_CDTI1_PB1 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x1) +#define TIMER0_CDTI1_PB2 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x2) +#define TIMER0_CDTI1_PB3 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x3) +#define TIMER0_CDTI1_PB4 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x4) +#define TIMER0_CDTI1_PC0 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x0) +#define TIMER0_CDTI1_PC1 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x1) +#define TIMER0_CDTI1_PC2 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x2) +#define TIMER0_CDTI1_PC3 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x3) +#define TIMER0_CDTI1_PC4 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x4) +#define TIMER0_CDTI1_PC5 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x5) +#define TIMER0_CDTI1_PC6 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x6) +#define TIMER0_CDTI1_PC7 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x7) +#define TIMER0_CDTI1_PD0 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x0) +#define TIMER0_CDTI1_PD1 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x1) +#define TIMER0_CDTI1_PD2 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x2) +#define TIMER0_CDTI1_PD3 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x3) +#define TIMER0_CDTI2_PA0 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x0) +#define TIMER0_CDTI2_PA1 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x1) +#define TIMER0_CDTI2_PA2 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x2) +#define TIMER0_CDTI2_PA3 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x3) +#define TIMER0_CDTI2_PA4 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x4) +#define TIMER0_CDTI2_PA5 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x5) +#define TIMER0_CDTI2_PA6 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x6) +#define TIMER0_CDTI2_PA7 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x7) +#define TIMER0_CDTI2_PA8 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x8) +#define TIMER0_CDTI2_PB0 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x0) +#define TIMER0_CDTI2_PB1 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x1) +#define TIMER0_CDTI2_PB2 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x2) +#define TIMER0_CDTI2_PB3 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x3) +#define TIMER0_CDTI2_PB4 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x4) +#define TIMER0_CDTI2_PC0 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x0) +#define TIMER0_CDTI2_PC1 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x1) +#define TIMER0_CDTI2_PC2 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x2) +#define TIMER0_CDTI2_PC3 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x3) +#define TIMER0_CDTI2_PC4 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x4) +#define TIMER0_CDTI2_PC5 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x5) +#define TIMER0_CDTI2_PC6 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x6) +#define TIMER0_CDTI2_PC7 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x7) +#define TIMER0_CDTI2_PD0 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x0) +#define TIMER0_CDTI2_PD1 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x1) +#define TIMER0_CDTI2_PD2 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x2) +#define TIMER0_CDTI2_PD3 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x3) + +#define TIMER1_CC0_PA0 SILABS_DBUS_TIMER1_CC0(0x0, 0x0) +#define TIMER1_CC0_PA1 SILABS_DBUS_TIMER1_CC0(0x0, 0x1) +#define TIMER1_CC0_PA2 SILABS_DBUS_TIMER1_CC0(0x0, 0x2) +#define TIMER1_CC0_PA3 SILABS_DBUS_TIMER1_CC0(0x0, 0x3) +#define TIMER1_CC0_PA4 SILABS_DBUS_TIMER1_CC0(0x0, 0x4) +#define TIMER1_CC0_PA5 SILABS_DBUS_TIMER1_CC0(0x0, 0x5) +#define TIMER1_CC0_PA6 SILABS_DBUS_TIMER1_CC0(0x0, 0x6) +#define TIMER1_CC0_PA7 SILABS_DBUS_TIMER1_CC0(0x0, 0x7) +#define TIMER1_CC0_PA8 SILABS_DBUS_TIMER1_CC0(0x0, 0x8) +#define TIMER1_CC0_PB0 SILABS_DBUS_TIMER1_CC0(0x1, 0x0) +#define TIMER1_CC0_PB1 SILABS_DBUS_TIMER1_CC0(0x1, 0x1) +#define TIMER1_CC0_PB2 SILABS_DBUS_TIMER1_CC0(0x1, 0x2) +#define TIMER1_CC0_PB3 SILABS_DBUS_TIMER1_CC0(0x1, 0x3) +#define TIMER1_CC0_PB4 SILABS_DBUS_TIMER1_CC0(0x1, 0x4) +#define TIMER1_CC0_PC0 SILABS_DBUS_TIMER1_CC0(0x2, 0x0) +#define TIMER1_CC0_PC1 SILABS_DBUS_TIMER1_CC0(0x2, 0x1) +#define TIMER1_CC0_PC2 SILABS_DBUS_TIMER1_CC0(0x2, 0x2) +#define TIMER1_CC0_PC3 SILABS_DBUS_TIMER1_CC0(0x2, 0x3) +#define TIMER1_CC0_PC4 SILABS_DBUS_TIMER1_CC0(0x2, 0x4) +#define TIMER1_CC0_PC5 SILABS_DBUS_TIMER1_CC0(0x2, 0x5) +#define TIMER1_CC0_PC6 SILABS_DBUS_TIMER1_CC0(0x2, 0x6) +#define TIMER1_CC0_PC7 SILABS_DBUS_TIMER1_CC0(0x2, 0x7) +#define TIMER1_CC0_PD0 SILABS_DBUS_TIMER1_CC0(0x3, 0x0) +#define TIMER1_CC0_PD1 SILABS_DBUS_TIMER1_CC0(0x3, 0x1) +#define TIMER1_CC0_PD2 SILABS_DBUS_TIMER1_CC0(0x3, 0x2) +#define TIMER1_CC0_PD3 SILABS_DBUS_TIMER1_CC0(0x3, 0x3) +#define TIMER1_CC1_PA0 SILABS_DBUS_TIMER1_CC1(0x0, 0x0) +#define TIMER1_CC1_PA1 SILABS_DBUS_TIMER1_CC1(0x0, 0x1) +#define TIMER1_CC1_PA2 SILABS_DBUS_TIMER1_CC1(0x0, 0x2) +#define TIMER1_CC1_PA3 SILABS_DBUS_TIMER1_CC1(0x0, 0x3) +#define TIMER1_CC1_PA4 SILABS_DBUS_TIMER1_CC1(0x0, 0x4) +#define TIMER1_CC1_PA5 SILABS_DBUS_TIMER1_CC1(0x0, 0x5) +#define TIMER1_CC1_PA6 SILABS_DBUS_TIMER1_CC1(0x0, 0x6) +#define TIMER1_CC1_PA7 SILABS_DBUS_TIMER1_CC1(0x0, 0x7) +#define TIMER1_CC1_PA8 SILABS_DBUS_TIMER1_CC1(0x0, 0x8) +#define TIMER1_CC1_PB0 SILABS_DBUS_TIMER1_CC1(0x1, 0x0) +#define TIMER1_CC1_PB1 SILABS_DBUS_TIMER1_CC1(0x1, 0x1) +#define TIMER1_CC1_PB2 SILABS_DBUS_TIMER1_CC1(0x1, 0x2) +#define TIMER1_CC1_PB3 SILABS_DBUS_TIMER1_CC1(0x1, 0x3) +#define TIMER1_CC1_PB4 SILABS_DBUS_TIMER1_CC1(0x1, 0x4) +#define TIMER1_CC1_PC0 SILABS_DBUS_TIMER1_CC1(0x2, 0x0) +#define TIMER1_CC1_PC1 SILABS_DBUS_TIMER1_CC1(0x2, 0x1) +#define TIMER1_CC1_PC2 SILABS_DBUS_TIMER1_CC1(0x2, 0x2) +#define TIMER1_CC1_PC3 SILABS_DBUS_TIMER1_CC1(0x2, 0x3) +#define TIMER1_CC1_PC4 SILABS_DBUS_TIMER1_CC1(0x2, 0x4) +#define TIMER1_CC1_PC5 SILABS_DBUS_TIMER1_CC1(0x2, 0x5) +#define TIMER1_CC1_PC6 SILABS_DBUS_TIMER1_CC1(0x2, 0x6) +#define TIMER1_CC1_PC7 SILABS_DBUS_TIMER1_CC1(0x2, 0x7) +#define TIMER1_CC1_PD0 SILABS_DBUS_TIMER1_CC1(0x3, 0x0) +#define TIMER1_CC1_PD1 SILABS_DBUS_TIMER1_CC1(0x3, 0x1) +#define TIMER1_CC1_PD2 SILABS_DBUS_TIMER1_CC1(0x3, 0x2) +#define TIMER1_CC1_PD3 SILABS_DBUS_TIMER1_CC1(0x3, 0x3) +#define TIMER1_CC2_PA0 SILABS_DBUS_TIMER1_CC2(0x0, 0x0) +#define TIMER1_CC2_PA1 SILABS_DBUS_TIMER1_CC2(0x0, 0x1) +#define TIMER1_CC2_PA2 SILABS_DBUS_TIMER1_CC2(0x0, 0x2) +#define TIMER1_CC2_PA3 SILABS_DBUS_TIMER1_CC2(0x0, 0x3) +#define TIMER1_CC2_PA4 SILABS_DBUS_TIMER1_CC2(0x0, 0x4) +#define TIMER1_CC2_PA5 SILABS_DBUS_TIMER1_CC2(0x0, 0x5) +#define TIMER1_CC2_PA6 SILABS_DBUS_TIMER1_CC2(0x0, 0x6) +#define TIMER1_CC2_PA7 SILABS_DBUS_TIMER1_CC2(0x0, 0x7) +#define TIMER1_CC2_PA8 SILABS_DBUS_TIMER1_CC2(0x0, 0x8) +#define TIMER1_CC2_PB0 SILABS_DBUS_TIMER1_CC2(0x1, 0x0) +#define TIMER1_CC2_PB1 SILABS_DBUS_TIMER1_CC2(0x1, 0x1) +#define TIMER1_CC2_PB2 SILABS_DBUS_TIMER1_CC2(0x1, 0x2) +#define TIMER1_CC2_PB3 SILABS_DBUS_TIMER1_CC2(0x1, 0x3) +#define TIMER1_CC2_PB4 SILABS_DBUS_TIMER1_CC2(0x1, 0x4) +#define TIMER1_CC2_PC0 SILABS_DBUS_TIMER1_CC2(0x2, 0x0) +#define TIMER1_CC2_PC1 SILABS_DBUS_TIMER1_CC2(0x2, 0x1) +#define TIMER1_CC2_PC2 SILABS_DBUS_TIMER1_CC2(0x2, 0x2) +#define TIMER1_CC2_PC3 SILABS_DBUS_TIMER1_CC2(0x2, 0x3) +#define TIMER1_CC2_PC4 SILABS_DBUS_TIMER1_CC2(0x2, 0x4) +#define TIMER1_CC2_PC5 SILABS_DBUS_TIMER1_CC2(0x2, 0x5) +#define TIMER1_CC2_PC6 SILABS_DBUS_TIMER1_CC2(0x2, 0x6) +#define TIMER1_CC2_PC7 SILABS_DBUS_TIMER1_CC2(0x2, 0x7) +#define TIMER1_CC2_PD0 SILABS_DBUS_TIMER1_CC2(0x3, 0x0) +#define TIMER1_CC2_PD1 SILABS_DBUS_TIMER1_CC2(0x3, 0x1) +#define TIMER1_CC2_PD2 SILABS_DBUS_TIMER1_CC2(0x3, 0x2) +#define TIMER1_CC2_PD3 SILABS_DBUS_TIMER1_CC2(0x3, 0x3) +#define TIMER1_CDTI0_PA0 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x0) +#define TIMER1_CDTI0_PA1 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x1) +#define TIMER1_CDTI0_PA2 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x2) +#define TIMER1_CDTI0_PA3 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x3) +#define TIMER1_CDTI0_PA4 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x4) +#define TIMER1_CDTI0_PA5 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x5) +#define TIMER1_CDTI0_PA6 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x6) +#define TIMER1_CDTI0_PA7 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x7) +#define TIMER1_CDTI0_PA8 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x8) +#define TIMER1_CDTI0_PB0 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x0) +#define TIMER1_CDTI0_PB1 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x1) +#define TIMER1_CDTI0_PB2 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x2) +#define TIMER1_CDTI0_PB3 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x3) +#define TIMER1_CDTI0_PB4 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x4) +#define TIMER1_CDTI0_PC0 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x0) +#define TIMER1_CDTI0_PC1 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x1) +#define TIMER1_CDTI0_PC2 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x2) +#define TIMER1_CDTI0_PC3 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x3) +#define TIMER1_CDTI0_PC4 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x4) +#define TIMER1_CDTI0_PC5 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x5) +#define TIMER1_CDTI0_PC6 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x6) +#define TIMER1_CDTI0_PC7 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x7) +#define TIMER1_CDTI0_PD0 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x0) +#define TIMER1_CDTI0_PD1 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x1) +#define TIMER1_CDTI0_PD2 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x2) +#define TIMER1_CDTI0_PD3 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x3) +#define TIMER1_CDTI1_PA0 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x0) +#define TIMER1_CDTI1_PA1 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x1) +#define TIMER1_CDTI1_PA2 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x2) +#define TIMER1_CDTI1_PA3 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x3) +#define TIMER1_CDTI1_PA4 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x4) +#define TIMER1_CDTI1_PA5 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x5) +#define TIMER1_CDTI1_PA6 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x6) +#define TIMER1_CDTI1_PA7 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x7) +#define TIMER1_CDTI1_PA8 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x8) +#define TIMER1_CDTI1_PB0 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x0) +#define TIMER1_CDTI1_PB1 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x1) +#define TIMER1_CDTI1_PB2 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x2) +#define TIMER1_CDTI1_PB3 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x3) +#define TIMER1_CDTI1_PB4 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x4) +#define TIMER1_CDTI1_PC0 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x0) +#define TIMER1_CDTI1_PC1 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x1) +#define TIMER1_CDTI1_PC2 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x2) +#define TIMER1_CDTI1_PC3 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x3) +#define TIMER1_CDTI1_PC4 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x4) +#define TIMER1_CDTI1_PC5 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x5) +#define TIMER1_CDTI1_PC6 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x6) +#define TIMER1_CDTI1_PC7 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x7) +#define TIMER1_CDTI1_PD0 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x0) +#define TIMER1_CDTI1_PD1 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x1) +#define TIMER1_CDTI1_PD2 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x2) +#define TIMER1_CDTI1_PD3 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x3) +#define TIMER1_CDTI2_PA0 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x0) +#define TIMER1_CDTI2_PA1 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x1) +#define TIMER1_CDTI2_PA2 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x2) +#define TIMER1_CDTI2_PA3 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x3) +#define TIMER1_CDTI2_PA4 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x4) +#define TIMER1_CDTI2_PA5 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x5) +#define TIMER1_CDTI2_PA6 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x6) +#define TIMER1_CDTI2_PA7 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x7) +#define TIMER1_CDTI2_PA8 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x8) +#define TIMER1_CDTI2_PB0 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x0) +#define TIMER1_CDTI2_PB1 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x1) +#define TIMER1_CDTI2_PB2 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x2) +#define TIMER1_CDTI2_PB3 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x3) +#define TIMER1_CDTI2_PB4 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x4) +#define TIMER1_CDTI2_PC0 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x0) +#define TIMER1_CDTI2_PC1 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x1) +#define TIMER1_CDTI2_PC2 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x2) +#define TIMER1_CDTI2_PC3 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x3) +#define TIMER1_CDTI2_PC4 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x4) +#define TIMER1_CDTI2_PC5 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x5) +#define TIMER1_CDTI2_PC6 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x6) +#define TIMER1_CDTI2_PC7 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x7) +#define TIMER1_CDTI2_PD0 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x0) +#define TIMER1_CDTI2_PD1 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x1) +#define TIMER1_CDTI2_PD2 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x2) +#define TIMER1_CDTI2_PD3 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x3) + +#define TIMER2_CC0_PA0 SILABS_DBUS_TIMER2_CC0(0x0, 0x0) +#define TIMER2_CC0_PA1 SILABS_DBUS_TIMER2_CC0(0x0, 0x1) +#define TIMER2_CC0_PA2 SILABS_DBUS_TIMER2_CC0(0x0, 0x2) +#define TIMER2_CC0_PA3 SILABS_DBUS_TIMER2_CC0(0x0, 0x3) +#define TIMER2_CC0_PA4 SILABS_DBUS_TIMER2_CC0(0x0, 0x4) +#define TIMER2_CC0_PA5 SILABS_DBUS_TIMER2_CC0(0x0, 0x5) +#define TIMER2_CC0_PA6 SILABS_DBUS_TIMER2_CC0(0x0, 0x6) +#define TIMER2_CC0_PA7 SILABS_DBUS_TIMER2_CC0(0x0, 0x7) +#define TIMER2_CC0_PA8 SILABS_DBUS_TIMER2_CC0(0x0, 0x8) +#define TIMER2_CC0_PB0 SILABS_DBUS_TIMER2_CC0(0x1, 0x0) +#define TIMER2_CC0_PB1 SILABS_DBUS_TIMER2_CC0(0x1, 0x1) +#define TIMER2_CC0_PB2 SILABS_DBUS_TIMER2_CC0(0x1, 0x2) +#define TIMER2_CC0_PB3 SILABS_DBUS_TIMER2_CC0(0x1, 0x3) +#define TIMER2_CC0_PB4 SILABS_DBUS_TIMER2_CC0(0x1, 0x4) +#define TIMER2_CC1_PA0 SILABS_DBUS_TIMER2_CC1(0x0, 0x0) +#define TIMER2_CC1_PA1 SILABS_DBUS_TIMER2_CC1(0x0, 0x1) +#define TIMER2_CC1_PA2 SILABS_DBUS_TIMER2_CC1(0x0, 0x2) +#define TIMER2_CC1_PA3 SILABS_DBUS_TIMER2_CC1(0x0, 0x3) +#define TIMER2_CC1_PA4 SILABS_DBUS_TIMER2_CC1(0x0, 0x4) +#define TIMER2_CC1_PA5 SILABS_DBUS_TIMER2_CC1(0x0, 0x5) +#define TIMER2_CC1_PA6 SILABS_DBUS_TIMER2_CC1(0x0, 0x6) +#define TIMER2_CC1_PA7 SILABS_DBUS_TIMER2_CC1(0x0, 0x7) +#define TIMER2_CC1_PA8 SILABS_DBUS_TIMER2_CC1(0x0, 0x8) +#define TIMER2_CC1_PB0 SILABS_DBUS_TIMER2_CC1(0x1, 0x0) +#define TIMER2_CC1_PB1 SILABS_DBUS_TIMER2_CC1(0x1, 0x1) +#define TIMER2_CC1_PB2 SILABS_DBUS_TIMER2_CC1(0x1, 0x2) +#define TIMER2_CC1_PB3 SILABS_DBUS_TIMER2_CC1(0x1, 0x3) +#define TIMER2_CC1_PB4 SILABS_DBUS_TIMER2_CC1(0x1, 0x4) +#define TIMER2_CC2_PA0 SILABS_DBUS_TIMER2_CC2(0x0, 0x0) +#define TIMER2_CC2_PA1 SILABS_DBUS_TIMER2_CC2(0x0, 0x1) +#define TIMER2_CC2_PA2 SILABS_DBUS_TIMER2_CC2(0x0, 0x2) +#define TIMER2_CC2_PA3 SILABS_DBUS_TIMER2_CC2(0x0, 0x3) +#define TIMER2_CC2_PA4 SILABS_DBUS_TIMER2_CC2(0x0, 0x4) +#define TIMER2_CC2_PA5 SILABS_DBUS_TIMER2_CC2(0x0, 0x5) +#define TIMER2_CC2_PA6 SILABS_DBUS_TIMER2_CC2(0x0, 0x6) +#define TIMER2_CC2_PA7 SILABS_DBUS_TIMER2_CC2(0x0, 0x7) +#define TIMER2_CC2_PA8 SILABS_DBUS_TIMER2_CC2(0x0, 0x8) +#define TIMER2_CC2_PB0 SILABS_DBUS_TIMER2_CC2(0x1, 0x0) +#define TIMER2_CC2_PB1 SILABS_DBUS_TIMER2_CC2(0x1, 0x1) +#define TIMER2_CC2_PB2 SILABS_DBUS_TIMER2_CC2(0x1, 0x2) +#define TIMER2_CC2_PB3 SILABS_DBUS_TIMER2_CC2(0x1, 0x3) +#define TIMER2_CC2_PB4 SILABS_DBUS_TIMER2_CC2(0x1, 0x4) +#define TIMER2_CDTI0_PA0 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x0) +#define TIMER2_CDTI0_PA1 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x1) +#define TIMER2_CDTI0_PA2 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x2) +#define TIMER2_CDTI0_PA3 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x3) +#define TIMER2_CDTI0_PA4 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x4) +#define TIMER2_CDTI0_PA5 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x5) +#define TIMER2_CDTI0_PA6 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x6) +#define TIMER2_CDTI0_PA7 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x7) +#define TIMER2_CDTI0_PA8 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x8) +#define TIMER2_CDTI0_PB0 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x0) +#define TIMER2_CDTI0_PB1 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x1) +#define TIMER2_CDTI0_PB2 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x2) +#define TIMER2_CDTI0_PB3 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x3) +#define TIMER2_CDTI0_PB4 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x4) +#define TIMER2_CDTI1_PA0 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x0) +#define TIMER2_CDTI1_PA1 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x1) +#define TIMER2_CDTI1_PA2 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x2) +#define TIMER2_CDTI1_PA3 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x3) +#define TIMER2_CDTI1_PA4 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x4) +#define TIMER2_CDTI1_PA5 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x5) +#define TIMER2_CDTI1_PA6 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x6) +#define TIMER2_CDTI1_PA7 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x7) +#define TIMER2_CDTI1_PA8 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x8) +#define TIMER2_CDTI1_PB0 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x0) +#define TIMER2_CDTI1_PB1 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x1) +#define TIMER2_CDTI1_PB2 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x2) +#define TIMER2_CDTI1_PB3 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x3) +#define TIMER2_CDTI1_PB4 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x4) +#define TIMER2_CDTI2_PA0 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x0) +#define TIMER2_CDTI2_PA1 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x1) +#define TIMER2_CDTI2_PA2 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x2) +#define TIMER2_CDTI2_PA3 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x3) +#define TIMER2_CDTI2_PA4 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x4) +#define TIMER2_CDTI2_PA5 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x5) +#define TIMER2_CDTI2_PA6 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x6) +#define TIMER2_CDTI2_PA7 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x7) +#define TIMER2_CDTI2_PA8 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x8) +#define TIMER2_CDTI2_PB0 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x0) +#define TIMER2_CDTI2_PB1 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x1) +#define TIMER2_CDTI2_PB2 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x2) +#define TIMER2_CDTI2_PB3 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x3) +#define TIMER2_CDTI2_PB4 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x4) + +#define TIMER3_CC0_PC0 SILABS_DBUS_TIMER3_CC0(0x2, 0x0) +#define TIMER3_CC0_PC1 SILABS_DBUS_TIMER3_CC0(0x2, 0x1) +#define TIMER3_CC0_PC2 SILABS_DBUS_TIMER3_CC0(0x2, 0x2) +#define TIMER3_CC0_PC3 SILABS_DBUS_TIMER3_CC0(0x2, 0x3) +#define TIMER3_CC0_PC4 SILABS_DBUS_TIMER3_CC0(0x2, 0x4) +#define TIMER3_CC0_PC5 SILABS_DBUS_TIMER3_CC0(0x2, 0x5) +#define TIMER3_CC0_PC6 SILABS_DBUS_TIMER3_CC0(0x2, 0x6) +#define TIMER3_CC0_PC7 SILABS_DBUS_TIMER3_CC0(0x2, 0x7) +#define TIMER3_CC0_PD0 SILABS_DBUS_TIMER3_CC0(0x3, 0x0) +#define TIMER3_CC0_PD1 SILABS_DBUS_TIMER3_CC0(0x3, 0x1) +#define TIMER3_CC0_PD2 SILABS_DBUS_TIMER3_CC0(0x3, 0x2) +#define TIMER3_CC0_PD3 SILABS_DBUS_TIMER3_CC0(0x3, 0x3) +#define TIMER3_CC1_PC0 SILABS_DBUS_TIMER3_CC1(0x2, 0x0) +#define TIMER3_CC1_PC1 SILABS_DBUS_TIMER3_CC1(0x2, 0x1) +#define TIMER3_CC1_PC2 SILABS_DBUS_TIMER3_CC1(0x2, 0x2) +#define TIMER3_CC1_PC3 SILABS_DBUS_TIMER3_CC1(0x2, 0x3) +#define TIMER3_CC1_PC4 SILABS_DBUS_TIMER3_CC1(0x2, 0x4) +#define TIMER3_CC1_PC5 SILABS_DBUS_TIMER3_CC1(0x2, 0x5) +#define TIMER3_CC1_PC6 SILABS_DBUS_TIMER3_CC1(0x2, 0x6) +#define TIMER3_CC1_PC7 SILABS_DBUS_TIMER3_CC1(0x2, 0x7) +#define TIMER3_CC1_PD0 SILABS_DBUS_TIMER3_CC1(0x3, 0x0) +#define TIMER3_CC1_PD1 SILABS_DBUS_TIMER3_CC1(0x3, 0x1) +#define TIMER3_CC1_PD2 SILABS_DBUS_TIMER3_CC1(0x3, 0x2) +#define TIMER3_CC1_PD3 SILABS_DBUS_TIMER3_CC1(0x3, 0x3) +#define TIMER3_CC2_PC0 SILABS_DBUS_TIMER3_CC2(0x2, 0x0) +#define TIMER3_CC2_PC1 SILABS_DBUS_TIMER3_CC2(0x2, 0x1) +#define TIMER3_CC2_PC2 SILABS_DBUS_TIMER3_CC2(0x2, 0x2) +#define TIMER3_CC2_PC3 SILABS_DBUS_TIMER3_CC2(0x2, 0x3) +#define TIMER3_CC2_PC4 SILABS_DBUS_TIMER3_CC2(0x2, 0x4) +#define TIMER3_CC2_PC5 SILABS_DBUS_TIMER3_CC2(0x2, 0x5) +#define TIMER3_CC2_PC6 SILABS_DBUS_TIMER3_CC2(0x2, 0x6) +#define TIMER3_CC2_PC7 SILABS_DBUS_TIMER3_CC2(0x2, 0x7) +#define TIMER3_CC2_PD0 SILABS_DBUS_TIMER3_CC2(0x3, 0x0) +#define TIMER3_CC2_PD1 SILABS_DBUS_TIMER3_CC2(0x3, 0x1) +#define TIMER3_CC2_PD2 SILABS_DBUS_TIMER3_CC2(0x3, 0x2) +#define TIMER3_CC2_PD3 SILABS_DBUS_TIMER3_CC2(0x3, 0x3) +#define TIMER3_CDTI0_PC0 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x0) +#define TIMER3_CDTI0_PC1 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x1) +#define TIMER3_CDTI0_PC2 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x2) +#define TIMER3_CDTI0_PC3 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x3) +#define TIMER3_CDTI0_PC4 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x4) +#define TIMER3_CDTI0_PC5 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x5) +#define TIMER3_CDTI0_PC6 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x6) +#define TIMER3_CDTI0_PC7 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x7) +#define TIMER3_CDTI0_PD0 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x0) +#define TIMER3_CDTI0_PD1 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x1) +#define TIMER3_CDTI0_PD2 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x2) +#define TIMER3_CDTI0_PD3 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x3) +#define TIMER3_CDTI1_PC0 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x0) +#define TIMER3_CDTI1_PC1 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x1) +#define TIMER3_CDTI1_PC2 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x2) +#define TIMER3_CDTI1_PC3 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x3) +#define TIMER3_CDTI1_PC4 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x4) +#define TIMER3_CDTI1_PC5 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x5) +#define TIMER3_CDTI1_PC6 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x6) +#define TIMER3_CDTI1_PC7 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x7) +#define TIMER3_CDTI1_PD0 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x0) +#define TIMER3_CDTI1_PD1 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x1) +#define TIMER3_CDTI1_PD2 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x2) +#define TIMER3_CDTI1_PD3 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x3) +#define TIMER3_CDTI2_PC0 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x0) +#define TIMER3_CDTI2_PC1 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x1) +#define TIMER3_CDTI2_PC2 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x2) +#define TIMER3_CDTI2_PC3 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x3) +#define TIMER3_CDTI2_PC4 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x4) +#define TIMER3_CDTI2_PC5 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x5) +#define TIMER3_CDTI2_PC6 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x6) +#define TIMER3_CDTI2_PC7 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x7) +#define TIMER3_CDTI2_PD0 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x0) +#define TIMER3_CDTI2_PD1 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x1) +#define TIMER3_CDTI2_PD2 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x2) +#define TIMER3_CDTI2_PD3 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x3) + +#define TIMER4_CC0_PA0 SILABS_DBUS_TIMER4_CC0(0x0, 0x0) +#define TIMER4_CC0_PA1 SILABS_DBUS_TIMER4_CC0(0x0, 0x1) +#define TIMER4_CC0_PA2 SILABS_DBUS_TIMER4_CC0(0x0, 0x2) +#define TIMER4_CC0_PA3 SILABS_DBUS_TIMER4_CC0(0x0, 0x3) +#define TIMER4_CC0_PA4 SILABS_DBUS_TIMER4_CC0(0x0, 0x4) +#define TIMER4_CC0_PA5 SILABS_DBUS_TIMER4_CC0(0x0, 0x5) +#define TIMER4_CC0_PA6 SILABS_DBUS_TIMER4_CC0(0x0, 0x6) +#define TIMER4_CC0_PA7 SILABS_DBUS_TIMER4_CC0(0x0, 0x7) +#define TIMER4_CC0_PA8 SILABS_DBUS_TIMER4_CC0(0x0, 0x8) +#define TIMER4_CC0_PB0 SILABS_DBUS_TIMER4_CC0(0x1, 0x0) +#define TIMER4_CC0_PB1 SILABS_DBUS_TIMER4_CC0(0x1, 0x1) +#define TIMER4_CC0_PB2 SILABS_DBUS_TIMER4_CC0(0x1, 0x2) +#define TIMER4_CC0_PB3 SILABS_DBUS_TIMER4_CC0(0x1, 0x3) +#define TIMER4_CC0_PB4 SILABS_DBUS_TIMER4_CC0(0x1, 0x4) +#define TIMER4_CC1_PA0 SILABS_DBUS_TIMER4_CC1(0x0, 0x0) +#define TIMER4_CC1_PA1 SILABS_DBUS_TIMER4_CC1(0x0, 0x1) +#define TIMER4_CC1_PA2 SILABS_DBUS_TIMER4_CC1(0x0, 0x2) +#define TIMER4_CC1_PA3 SILABS_DBUS_TIMER4_CC1(0x0, 0x3) +#define TIMER4_CC1_PA4 SILABS_DBUS_TIMER4_CC1(0x0, 0x4) +#define TIMER4_CC1_PA5 SILABS_DBUS_TIMER4_CC1(0x0, 0x5) +#define TIMER4_CC1_PA6 SILABS_DBUS_TIMER4_CC1(0x0, 0x6) +#define TIMER4_CC1_PA7 SILABS_DBUS_TIMER4_CC1(0x0, 0x7) +#define TIMER4_CC1_PA8 SILABS_DBUS_TIMER4_CC1(0x0, 0x8) +#define TIMER4_CC1_PB0 SILABS_DBUS_TIMER4_CC1(0x1, 0x0) +#define TIMER4_CC1_PB1 SILABS_DBUS_TIMER4_CC1(0x1, 0x1) +#define TIMER4_CC1_PB2 SILABS_DBUS_TIMER4_CC1(0x1, 0x2) +#define TIMER4_CC1_PB3 SILABS_DBUS_TIMER4_CC1(0x1, 0x3) +#define TIMER4_CC1_PB4 SILABS_DBUS_TIMER4_CC1(0x1, 0x4) +#define TIMER4_CC2_PA0 SILABS_DBUS_TIMER4_CC2(0x0, 0x0) +#define TIMER4_CC2_PA1 SILABS_DBUS_TIMER4_CC2(0x0, 0x1) +#define TIMER4_CC2_PA2 SILABS_DBUS_TIMER4_CC2(0x0, 0x2) +#define TIMER4_CC2_PA3 SILABS_DBUS_TIMER4_CC2(0x0, 0x3) +#define TIMER4_CC2_PA4 SILABS_DBUS_TIMER4_CC2(0x0, 0x4) +#define TIMER4_CC2_PA5 SILABS_DBUS_TIMER4_CC2(0x0, 0x5) +#define TIMER4_CC2_PA6 SILABS_DBUS_TIMER4_CC2(0x0, 0x6) +#define TIMER4_CC2_PA7 SILABS_DBUS_TIMER4_CC2(0x0, 0x7) +#define TIMER4_CC2_PA8 SILABS_DBUS_TIMER4_CC2(0x0, 0x8) +#define TIMER4_CC2_PB0 SILABS_DBUS_TIMER4_CC2(0x1, 0x0) +#define TIMER4_CC2_PB1 SILABS_DBUS_TIMER4_CC2(0x1, 0x1) +#define TIMER4_CC2_PB2 SILABS_DBUS_TIMER4_CC2(0x1, 0x2) +#define TIMER4_CC2_PB3 SILABS_DBUS_TIMER4_CC2(0x1, 0x3) +#define TIMER4_CC2_PB4 SILABS_DBUS_TIMER4_CC2(0x1, 0x4) +#define TIMER4_CDTI0_PA0 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x0) +#define TIMER4_CDTI0_PA1 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x1) +#define TIMER4_CDTI0_PA2 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x2) +#define TIMER4_CDTI0_PA3 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x3) +#define TIMER4_CDTI0_PA4 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x4) +#define TIMER4_CDTI0_PA5 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x5) +#define TIMER4_CDTI0_PA6 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x6) +#define TIMER4_CDTI0_PA7 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x7) +#define TIMER4_CDTI0_PA8 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x8) +#define TIMER4_CDTI0_PB0 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x0) +#define TIMER4_CDTI0_PB1 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x1) +#define TIMER4_CDTI0_PB2 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x2) +#define TIMER4_CDTI0_PB3 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x3) +#define TIMER4_CDTI0_PB4 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x4) +#define TIMER4_CDTI1_PA0 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x0) +#define TIMER4_CDTI1_PA1 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x1) +#define TIMER4_CDTI1_PA2 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x2) +#define TIMER4_CDTI1_PA3 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x3) +#define TIMER4_CDTI1_PA4 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x4) +#define TIMER4_CDTI1_PA5 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x5) +#define TIMER4_CDTI1_PA6 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x6) +#define TIMER4_CDTI1_PA7 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x7) +#define TIMER4_CDTI1_PA8 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x8) +#define TIMER4_CDTI1_PB0 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x0) +#define TIMER4_CDTI1_PB1 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x1) +#define TIMER4_CDTI1_PB2 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x2) +#define TIMER4_CDTI1_PB3 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x3) +#define TIMER4_CDTI1_PB4 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x4) +#define TIMER4_CDTI2_PA0 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x0) +#define TIMER4_CDTI2_PA1 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x1) +#define TIMER4_CDTI2_PA2 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x2) +#define TIMER4_CDTI2_PA3 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x3) +#define TIMER4_CDTI2_PA4 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x4) +#define TIMER4_CDTI2_PA5 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x5) +#define TIMER4_CDTI2_PA6 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x6) +#define TIMER4_CDTI2_PA7 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x7) +#define TIMER4_CDTI2_PA8 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x8) +#define TIMER4_CDTI2_PB0 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x0) +#define TIMER4_CDTI2_PB1 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x1) +#define TIMER4_CDTI2_PB2 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x2) +#define TIMER4_CDTI2_PB3 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x3) +#define TIMER4_CDTI2_PB4 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x4) + +#define USART0_CS_PA0 SILABS_DBUS_USART0_CS(0x0, 0x0) +#define USART0_CS_PA1 SILABS_DBUS_USART0_CS(0x0, 0x1) +#define USART0_CS_PA2 SILABS_DBUS_USART0_CS(0x0, 0x2) +#define USART0_CS_PA3 SILABS_DBUS_USART0_CS(0x0, 0x3) +#define USART0_CS_PA4 SILABS_DBUS_USART0_CS(0x0, 0x4) +#define USART0_CS_PA5 SILABS_DBUS_USART0_CS(0x0, 0x5) +#define USART0_CS_PA6 SILABS_DBUS_USART0_CS(0x0, 0x6) +#define USART0_CS_PA7 SILABS_DBUS_USART0_CS(0x0, 0x7) +#define USART0_CS_PA8 SILABS_DBUS_USART0_CS(0x0, 0x8) +#define USART0_CS_PB0 SILABS_DBUS_USART0_CS(0x1, 0x0) +#define USART0_CS_PB1 SILABS_DBUS_USART0_CS(0x1, 0x1) +#define USART0_CS_PB2 SILABS_DBUS_USART0_CS(0x1, 0x2) +#define USART0_CS_PB3 SILABS_DBUS_USART0_CS(0x1, 0x3) +#define USART0_CS_PB4 SILABS_DBUS_USART0_CS(0x1, 0x4) +#define USART0_CS_PC0 SILABS_DBUS_USART0_CS(0x2, 0x0) +#define USART0_CS_PC1 SILABS_DBUS_USART0_CS(0x2, 0x1) +#define USART0_CS_PC2 SILABS_DBUS_USART0_CS(0x2, 0x2) +#define USART0_CS_PC3 SILABS_DBUS_USART0_CS(0x2, 0x3) +#define USART0_CS_PC4 SILABS_DBUS_USART0_CS(0x2, 0x4) +#define USART0_CS_PC5 SILABS_DBUS_USART0_CS(0x2, 0x5) +#define USART0_CS_PC6 SILABS_DBUS_USART0_CS(0x2, 0x6) +#define USART0_CS_PC7 SILABS_DBUS_USART0_CS(0x2, 0x7) +#define USART0_CS_PD0 SILABS_DBUS_USART0_CS(0x3, 0x0) +#define USART0_CS_PD1 SILABS_DBUS_USART0_CS(0x3, 0x1) +#define USART0_CS_PD2 SILABS_DBUS_USART0_CS(0x3, 0x2) +#define USART0_CS_PD3 SILABS_DBUS_USART0_CS(0x3, 0x3) +#define USART0_RTS_PA0 SILABS_DBUS_USART0_RTS(0x0, 0x0) +#define USART0_RTS_PA1 SILABS_DBUS_USART0_RTS(0x0, 0x1) +#define USART0_RTS_PA2 SILABS_DBUS_USART0_RTS(0x0, 0x2) +#define USART0_RTS_PA3 SILABS_DBUS_USART0_RTS(0x0, 0x3) +#define USART0_RTS_PA4 SILABS_DBUS_USART0_RTS(0x0, 0x4) +#define USART0_RTS_PA5 SILABS_DBUS_USART0_RTS(0x0, 0x5) +#define USART0_RTS_PA6 SILABS_DBUS_USART0_RTS(0x0, 0x6) +#define USART0_RTS_PA7 SILABS_DBUS_USART0_RTS(0x0, 0x7) +#define USART0_RTS_PA8 SILABS_DBUS_USART0_RTS(0x0, 0x8) +#define USART0_RTS_PB0 SILABS_DBUS_USART0_RTS(0x1, 0x0) +#define USART0_RTS_PB1 SILABS_DBUS_USART0_RTS(0x1, 0x1) +#define USART0_RTS_PB2 SILABS_DBUS_USART0_RTS(0x1, 0x2) +#define USART0_RTS_PB3 SILABS_DBUS_USART0_RTS(0x1, 0x3) +#define USART0_RTS_PB4 SILABS_DBUS_USART0_RTS(0x1, 0x4) +#define USART0_RTS_PC0 SILABS_DBUS_USART0_RTS(0x2, 0x0) +#define USART0_RTS_PC1 SILABS_DBUS_USART0_RTS(0x2, 0x1) +#define USART0_RTS_PC2 SILABS_DBUS_USART0_RTS(0x2, 0x2) +#define USART0_RTS_PC3 SILABS_DBUS_USART0_RTS(0x2, 0x3) +#define USART0_RTS_PC4 SILABS_DBUS_USART0_RTS(0x2, 0x4) +#define USART0_RTS_PC5 SILABS_DBUS_USART0_RTS(0x2, 0x5) +#define USART0_RTS_PC6 SILABS_DBUS_USART0_RTS(0x2, 0x6) +#define USART0_RTS_PC7 SILABS_DBUS_USART0_RTS(0x2, 0x7) +#define USART0_RTS_PD0 SILABS_DBUS_USART0_RTS(0x3, 0x0) +#define USART0_RTS_PD1 SILABS_DBUS_USART0_RTS(0x3, 0x1) +#define USART0_RTS_PD2 SILABS_DBUS_USART0_RTS(0x3, 0x2) +#define USART0_RTS_PD3 SILABS_DBUS_USART0_RTS(0x3, 0x3) +#define USART0_RX_PA0 SILABS_DBUS_USART0_RX(0x0, 0x0) +#define USART0_RX_PA1 SILABS_DBUS_USART0_RX(0x0, 0x1) +#define USART0_RX_PA2 SILABS_DBUS_USART0_RX(0x0, 0x2) +#define USART0_RX_PA3 SILABS_DBUS_USART0_RX(0x0, 0x3) +#define USART0_RX_PA4 SILABS_DBUS_USART0_RX(0x0, 0x4) +#define USART0_RX_PA5 SILABS_DBUS_USART0_RX(0x0, 0x5) +#define USART0_RX_PA6 SILABS_DBUS_USART0_RX(0x0, 0x6) +#define USART0_RX_PA7 SILABS_DBUS_USART0_RX(0x0, 0x7) +#define USART0_RX_PA8 SILABS_DBUS_USART0_RX(0x0, 0x8) +#define USART0_RX_PB0 SILABS_DBUS_USART0_RX(0x1, 0x0) +#define USART0_RX_PB1 SILABS_DBUS_USART0_RX(0x1, 0x1) +#define USART0_RX_PB2 SILABS_DBUS_USART0_RX(0x1, 0x2) +#define USART0_RX_PB3 SILABS_DBUS_USART0_RX(0x1, 0x3) +#define USART0_RX_PB4 SILABS_DBUS_USART0_RX(0x1, 0x4) +#define USART0_RX_PC0 SILABS_DBUS_USART0_RX(0x2, 0x0) +#define USART0_RX_PC1 SILABS_DBUS_USART0_RX(0x2, 0x1) +#define USART0_RX_PC2 SILABS_DBUS_USART0_RX(0x2, 0x2) +#define USART0_RX_PC3 SILABS_DBUS_USART0_RX(0x2, 0x3) +#define USART0_RX_PC4 SILABS_DBUS_USART0_RX(0x2, 0x4) +#define USART0_RX_PC5 SILABS_DBUS_USART0_RX(0x2, 0x5) +#define USART0_RX_PC6 SILABS_DBUS_USART0_RX(0x2, 0x6) +#define USART0_RX_PC7 SILABS_DBUS_USART0_RX(0x2, 0x7) +#define USART0_RX_PD0 SILABS_DBUS_USART0_RX(0x3, 0x0) +#define USART0_RX_PD1 SILABS_DBUS_USART0_RX(0x3, 0x1) +#define USART0_RX_PD2 SILABS_DBUS_USART0_RX(0x3, 0x2) +#define USART0_RX_PD3 SILABS_DBUS_USART0_RX(0x3, 0x3) +#define USART0_CLK_PA0 SILABS_DBUS_USART0_CLK(0x0, 0x0) +#define USART0_CLK_PA1 SILABS_DBUS_USART0_CLK(0x0, 0x1) +#define USART0_CLK_PA2 SILABS_DBUS_USART0_CLK(0x0, 0x2) +#define USART0_CLK_PA3 SILABS_DBUS_USART0_CLK(0x0, 0x3) +#define USART0_CLK_PA4 SILABS_DBUS_USART0_CLK(0x0, 0x4) +#define USART0_CLK_PA5 SILABS_DBUS_USART0_CLK(0x0, 0x5) +#define USART0_CLK_PA6 SILABS_DBUS_USART0_CLK(0x0, 0x6) +#define USART0_CLK_PA7 SILABS_DBUS_USART0_CLK(0x0, 0x7) +#define USART0_CLK_PA8 SILABS_DBUS_USART0_CLK(0x0, 0x8) +#define USART0_CLK_PB0 SILABS_DBUS_USART0_CLK(0x1, 0x0) +#define USART0_CLK_PB1 SILABS_DBUS_USART0_CLK(0x1, 0x1) +#define USART0_CLK_PB2 SILABS_DBUS_USART0_CLK(0x1, 0x2) +#define USART0_CLK_PB3 SILABS_DBUS_USART0_CLK(0x1, 0x3) +#define USART0_CLK_PB4 SILABS_DBUS_USART0_CLK(0x1, 0x4) +#define USART0_CLK_PC0 SILABS_DBUS_USART0_CLK(0x2, 0x0) +#define USART0_CLK_PC1 SILABS_DBUS_USART0_CLK(0x2, 0x1) +#define USART0_CLK_PC2 SILABS_DBUS_USART0_CLK(0x2, 0x2) +#define USART0_CLK_PC3 SILABS_DBUS_USART0_CLK(0x2, 0x3) +#define USART0_CLK_PC4 SILABS_DBUS_USART0_CLK(0x2, 0x4) +#define USART0_CLK_PC5 SILABS_DBUS_USART0_CLK(0x2, 0x5) +#define USART0_CLK_PC6 SILABS_DBUS_USART0_CLK(0x2, 0x6) +#define USART0_CLK_PC7 SILABS_DBUS_USART0_CLK(0x2, 0x7) +#define USART0_CLK_PD0 SILABS_DBUS_USART0_CLK(0x3, 0x0) +#define USART0_CLK_PD1 SILABS_DBUS_USART0_CLK(0x3, 0x1) +#define USART0_CLK_PD2 SILABS_DBUS_USART0_CLK(0x3, 0x2) +#define USART0_CLK_PD3 SILABS_DBUS_USART0_CLK(0x3, 0x3) +#define USART0_TX_PA0 SILABS_DBUS_USART0_TX(0x0, 0x0) +#define USART0_TX_PA1 SILABS_DBUS_USART0_TX(0x0, 0x1) +#define USART0_TX_PA2 SILABS_DBUS_USART0_TX(0x0, 0x2) +#define USART0_TX_PA3 SILABS_DBUS_USART0_TX(0x0, 0x3) +#define USART0_TX_PA4 SILABS_DBUS_USART0_TX(0x0, 0x4) +#define USART0_TX_PA5 SILABS_DBUS_USART0_TX(0x0, 0x5) +#define USART0_TX_PA6 SILABS_DBUS_USART0_TX(0x0, 0x6) +#define USART0_TX_PA7 SILABS_DBUS_USART0_TX(0x0, 0x7) +#define USART0_TX_PA8 SILABS_DBUS_USART0_TX(0x0, 0x8) +#define USART0_TX_PB0 SILABS_DBUS_USART0_TX(0x1, 0x0) +#define USART0_TX_PB1 SILABS_DBUS_USART0_TX(0x1, 0x1) +#define USART0_TX_PB2 SILABS_DBUS_USART0_TX(0x1, 0x2) +#define USART0_TX_PB3 SILABS_DBUS_USART0_TX(0x1, 0x3) +#define USART0_TX_PB4 SILABS_DBUS_USART0_TX(0x1, 0x4) +#define USART0_TX_PC0 SILABS_DBUS_USART0_TX(0x2, 0x0) +#define USART0_TX_PC1 SILABS_DBUS_USART0_TX(0x2, 0x1) +#define USART0_TX_PC2 SILABS_DBUS_USART0_TX(0x2, 0x2) +#define USART0_TX_PC3 SILABS_DBUS_USART0_TX(0x2, 0x3) +#define USART0_TX_PC4 SILABS_DBUS_USART0_TX(0x2, 0x4) +#define USART0_TX_PC5 SILABS_DBUS_USART0_TX(0x2, 0x5) +#define USART0_TX_PC6 SILABS_DBUS_USART0_TX(0x2, 0x6) +#define USART0_TX_PC7 SILABS_DBUS_USART0_TX(0x2, 0x7) +#define USART0_TX_PD0 SILABS_DBUS_USART0_TX(0x3, 0x0) +#define USART0_TX_PD1 SILABS_DBUS_USART0_TX(0x3, 0x1) +#define USART0_TX_PD2 SILABS_DBUS_USART0_TX(0x3, 0x2) +#define USART0_TX_PD3 SILABS_DBUS_USART0_TX(0x3, 0x3) +#define USART0_CTS_PA0 SILABS_DBUS_USART0_CTS(0x0, 0x0) +#define USART0_CTS_PA1 SILABS_DBUS_USART0_CTS(0x0, 0x1) +#define USART0_CTS_PA2 SILABS_DBUS_USART0_CTS(0x0, 0x2) +#define USART0_CTS_PA3 SILABS_DBUS_USART0_CTS(0x0, 0x3) +#define USART0_CTS_PA4 SILABS_DBUS_USART0_CTS(0x0, 0x4) +#define USART0_CTS_PA5 SILABS_DBUS_USART0_CTS(0x0, 0x5) +#define USART0_CTS_PA6 SILABS_DBUS_USART0_CTS(0x0, 0x6) +#define USART0_CTS_PA7 SILABS_DBUS_USART0_CTS(0x0, 0x7) +#define USART0_CTS_PA8 SILABS_DBUS_USART0_CTS(0x0, 0x8) +#define USART0_CTS_PB0 SILABS_DBUS_USART0_CTS(0x1, 0x0) +#define USART0_CTS_PB1 SILABS_DBUS_USART0_CTS(0x1, 0x1) +#define USART0_CTS_PB2 SILABS_DBUS_USART0_CTS(0x1, 0x2) +#define USART0_CTS_PB3 SILABS_DBUS_USART0_CTS(0x1, 0x3) +#define USART0_CTS_PB4 SILABS_DBUS_USART0_CTS(0x1, 0x4) +#define USART0_CTS_PC0 SILABS_DBUS_USART0_CTS(0x2, 0x0) +#define USART0_CTS_PC1 SILABS_DBUS_USART0_CTS(0x2, 0x1) +#define USART0_CTS_PC2 SILABS_DBUS_USART0_CTS(0x2, 0x2) +#define USART0_CTS_PC3 SILABS_DBUS_USART0_CTS(0x2, 0x3) +#define USART0_CTS_PC4 SILABS_DBUS_USART0_CTS(0x2, 0x4) +#define USART0_CTS_PC5 SILABS_DBUS_USART0_CTS(0x2, 0x5) +#define USART0_CTS_PC6 SILABS_DBUS_USART0_CTS(0x2, 0x6) +#define USART0_CTS_PC7 SILABS_DBUS_USART0_CTS(0x2, 0x7) +#define USART0_CTS_PD0 SILABS_DBUS_USART0_CTS(0x3, 0x0) +#define USART0_CTS_PD1 SILABS_DBUS_USART0_CTS(0x3, 0x1) +#define USART0_CTS_PD2 SILABS_DBUS_USART0_CTS(0x3, 0x2) +#define USART0_CTS_PD3 SILABS_DBUS_USART0_CTS(0x3, 0x3) + +#define USART1_CS_PA0 SILABS_DBUS_USART1_CS(0x0, 0x0) +#define USART1_CS_PA1 SILABS_DBUS_USART1_CS(0x0, 0x1) +#define USART1_CS_PA2 SILABS_DBUS_USART1_CS(0x0, 0x2) +#define USART1_CS_PA3 SILABS_DBUS_USART1_CS(0x0, 0x3) +#define USART1_CS_PA4 SILABS_DBUS_USART1_CS(0x0, 0x4) +#define USART1_CS_PA5 SILABS_DBUS_USART1_CS(0x0, 0x5) +#define USART1_CS_PA6 SILABS_DBUS_USART1_CS(0x0, 0x6) +#define USART1_CS_PA7 SILABS_DBUS_USART1_CS(0x0, 0x7) +#define USART1_CS_PA8 SILABS_DBUS_USART1_CS(0x0, 0x8) +#define USART1_CS_PB0 SILABS_DBUS_USART1_CS(0x1, 0x0) +#define USART1_CS_PB1 SILABS_DBUS_USART1_CS(0x1, 0x1) +#define USART1_CS_PB2 SILABS_DBUS_USART1_CS(0x1, 0x2) +#define USART1_CS_PB3 SILABS_DBUS_USART1_CS(0x1, 0x3) +#define USART1_CS_PB4 SILABS_DBUS_USART1_CS(0x1, 0x4) +#define USART1_RTS_PA0 SILABS_DBUS_USART1_RTS(0x0, 0x0) +#define USART1_RTS_PA1 SILABS_DBUS_USART1_RTS(0x0, 0x1) +#define USART1_RTS_PA2 SILABS_DBUS_USART1_RTS(0x0, 0x2) +#define USART1_RTS_PA3 SILABS_DBUS_USART1_RTS(0x0, 0x3) +#define USART1_RTS_PA4 SILABS_DBUS_USART1_RTS(0x0, 0x4) +#define USART1_RTS_PA5 SILABS_DBUS_USART1_RTS(0x0, 0x5) +#define USART1_RTS_PA6 SILABS_DBUS_USART1_RTS(0x0, 0x6) +#define USART1_RTS_PA7 SILABS_DBUS_USART1_RTS(0x0, 0x7) +#define USART1_RTS_PA8 SILABS_DBUS_USART1_RTS(0x0, 0x8) +#define USART1_RTS_PB0 SILABS_DBUS_USART1_RTS(0x1, 0x0) +#define USART1_RTS_PB1 SILABS_DBUS_USART1_RTS(0x1, 0x1) +#define USART1_RTS_PB2 SILABS_DBUS_USART1_RTS(0x1, 0x2) +#define USART1_RTS_PB3 SILABS_DBUS_USART1_RTS(0x1, 0x3) +#define USART1_RTS_PB4 SILABS_DBUS_USART1_RTS(0x1, 0x4) +#define USART1_RX_PA0 SILABS_DBUS_USART1_RX(0x0, 0x0) +#define USART1_RX_PA1 SILABS_DBUS_USART1_RX(0x0, 0x1) +#define USART1_RX_PA2 SILABS_DBUS_USART1_RX(0x0, 0x2) +#define USART1_RX_PA3 SILABS_DBUS_USART1_RX(0x0, 0x3) +#define USART1_RX_PA4 SILABS_DBUS_USART1_RX(0x0, 0x4) +#define USART1_RX_PA5 SILABS_DBUS_USART1_RX(0x0, 0x5) +#define USART1_RX_PA6 SILABS_DBUS_USART1_RX(0x0, 0x6) +#define USART1_RX_PA7 SILABS_DBUS_USART1_RX(0x0, 0x7) +#define USART1_RX_PA8 SILABS_DBUS_USART1_RX(0x0, 0x8) +#define USART1_RX_PB0 SILABS_DBUS_USART1_RX(0x1, 0x0) +#define USART1_RX_PB1 SILABS_DBUS_USART1_RX(0x1, 0x1) +#define USART1_RX_PB2 SILABS_DBUS_USART1_RX(0x1, 0x2) +#define USART1_RX_PB3 SILABS_DBUS_USART1_RX(0x1, 0x3) +#define USART1_RX_PB4 SILABS_DBUS_USART1_RX(0x1, 0x4) +#define USART1_CLK_PA0 SILABS_DBUS_USART1_CLK(0x0, 0x0) +#define USART1_CLK_PA1 SILABS_DBUS_USART1_CLK(0x0, 0x1) +#define USART1_CLK_PA2 SILABS_DBUS_USART1_CLK(0x0, 0x2) +#define USART1_CLK_PA3 SILABS_DBUS_USART1_CLK(0x0, 0x3) +#define USART1_CLK_PA4 SILABS_DBUS_USART1_CLK(0x0, 0x4) +#define USART1_CLK_PA5 SILABS_DBUS_USART1_CLK(0x0, 0x5) +#define USART1_CLK_PA6 SILABS_DBUS_USART1_CLK(0x0, 0x6) +#define USART1_CLK_PA7 SILABS_DBUS_USART1_CLK(0x0, 0x7) +#define USART1_CLK_PA8 SILABS_DBUS_USART1_CLK(0x0, 0x8) +#define USART1_CLK_PB0 SILABS_DBUS_USART1_CLK(0x1, 0x0) +#define USART1_CLK_PB1 SILABS_DBUS_USART1_CLK(0x1, 0x1) +#define USART1_CLK_PB2 SILABS_DBUS_USART1_CLK(0x1, 0x2) +#define USART1_CLK_PB3 SILABS_DBUS_USART1_CLK(0x1, 0x3) +#define USART1_CLK_PB4 SILABS_DBUS_USART1_CLK(0x1, 0x4) +#define USART1_TX_PA0 SILABS_DBUS_USART1_TX(0x0, 0x0) +#define USART1_TX_PA1 SILABS_DBUS_USART1_TX(0x0, 0x1) +#define USART1_TX_PA2 SILABS_DBUS_USART1_TX(0x0, 0x2) +#define USART1_TX_PA3 SILABS_DBUS_USART1_TX(0x0, 0x3) +#define USART1_TX_PA4 SILABS_DBUS_USART1_TX(0x0, 0x4) +#define USART1_TX_PA5 SILABS_DBUS_USART1_TX(0x0, 0x5) +#define USART1_TX_PA6 SILABS_DBUS_USART1_TX(0x0, 0x6) +#define USART1_TX_PA7 SILABS_DBUS_USART1_TX(0x0, 0x7) +#define USART1_TX_PA8 SILABS_DBUS_USART1_TX(0x0, 0x8) +#define USART1_TX_PB0 SILABS_DBUS_USART1_TX(0x1, 0x0) +#define USART1_TX_PB1 SILABS_DBUS_USART1_TX(0x1, 0x1) +#define USART1_TX_PB2 SILABS_DBUS_USART1_TX(0x1, 0x2) +#define USART1_TX_PB3 SILABS_DBUS_USART1_TX(0x1, 0x3) +#define USART1_TX_PB4 SILABS_DBUS_USART1_TX(0x1, 0x4) +#define USART1_CTS_PA0 SILABS_DBUS_USART1_CTS(0x0, 0x0) +#define USART1_CTS_PA1 SILABS_DBUS_USART1_CTS(0x0, 0x1) +#define USART1_CTS_PA2 SILABS_DBUS_USART1_CTS(0x0, 0x2) +#define USART1_CTS_PA3 SILABS_DBUS_USART1_CTS(0x0, 0x3) +#define USART1_CTS_PA4 SILABS_DBUS_USART1_CTS(0x0, 0x4) +#define USART1_CTS_PA5 SILABS_DBUS_USART1_CTS(0x0, 0x5) +#define USART1_CTS_PA6 SILABS_DBUS_USART1_CTS(0x0, 0x6) +#define USART1_CTS_PA7 SILABS_DBUS_USART1_CTS(0x0, 0x7) +#define USART1_CTS_PA8 SILABS_DBUS_USART1_CTS(0x0, 0x8) +#define USART1_CTS_PB0 SILABS_DBUS_USART1_CTS(0x1, 0x0) +#define USART1_CTS_PB1 SILABS_DBUS_USART1_CTS(0x1, 0x1) +#define USART1_CTS_PB2 SILABS_DBUS_USART1_CTS(0x1, 0x2) +#define USART1_CTS_PB3 SILABS_DBUS_USART1_CTS(0x1, 0x3) +#define USART1_CTS_PB4 SILABS_DBUS_USART1_CTS(0x1, 0x4) + +#endif /* ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG29_PINCTRL_H_ */ diff --git a/soc/silabs/Kconfig b/soc/silabs/Kconfig index dbdda491926..07c20603780 100644 --- a/soc/silabs/Kconfig +++ b/soc/silabs/Kconfig @@ -129,7 +129,7 @@ config SOC_GECKO_TRNG config SOC_SILABS_SLEEPTIMER bool select SOC_GECKO_PRS - select SOC_GECKO_RTCC if SOC_SERIES_EFR32BG22 || SOC_SERIES_EFR32BG27 || SOC_SERIES_EFR32MG21 + select SOC_GECKO_RTCC if SOC_FAMILY_SILABS_S2 && $(dt_nodelabel_enabled,rtcc0) help Set if the Sleeptimer HAL module is used. diff --git a/soc/silabs/silabs_s2/xg29/Kconfig b/soc/silabs/silabs_s2/xg29/Kconfig new file mode 100644 index 00000000000..c74a892fa65 --- /dev/null +++ b/soc/silabs/silabs_s2/xg29/Kconfig @@ -0,0 +1,43 @@ +# Copyright (c) 2025 Silicon Laboratories Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFR32BG29 + select ARM + select CPU_CORTEX_M33 + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select CPU_HAS_ARM_SAU + select CPU_CORTEX_M_HAS_DWT + select ARMV8_M_DSP + select ARM_TRUSTZONE_M + select SOC_GECKO_HAS_RADIO + select HAS_SILABS_GECKO + select HAS_SWO + select SOC_GECKO_CMU + select SOC_GECKO_EMU + select SOC_GECKO_GPIO + select SOC_GECKO_DEV_INIT + select SOC_GECKO_SE + select HAS_PM + +config SOC_SERIES_EFR32MG29 + select ARM + select CPU_CORTEX_M33 + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select CPU_HAS_ARM_SAU + select CPU_CORTEX_M_HAS_DWT + select ARMV8_M_DSP + select ARM_TRUSTZONE_M + select SOC_GECKO_HAS_RADIO + select HAS_SILABS_GECKO + select HAS_SWO + select SOC_GECKO_CMU + select SOC_GECKO_EMU + select SOC_GECKO_GPIO + select SOC_GECKO_DEV_INIT + select SOC_GECKO_SE + select HAS_PM + +config SOC_GECKO_SDID + default 240 if SOC_SERIES_EFR32BG29 || SOC_SERIES_EFR32MG29 diff --git a/soc/silabs/silabs_s2/xg29/Kconfig.defconfig b/soc/silabs/silabs_s2/xg29/Kconfig.defconfig new file mode 100644 index 00000000000..84949e8912c --- /dev/null +++ b/soc/silabs/silabs_s2/xg29/Kconfig.defconfig @@ -0,0 +1,19 @@ +# Copyright (c) 2025 Silicon Laboratories Inc. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_EFR32BG29 || SOC_SERIES_EFR32MG29 + +config NUM_IRQS + # must be >= the highest interrupt number used + default 70 + +config PM + default n + select UART_INTERRUPT_DRIVEN if SERIAL_SUPPORT_INTERRUPT + +choice PM_POLICY + default PM_POLICY_DEFAULT + depends on PM +endchoice + +endif diff --git a/soc/silabs/silabs_s2/xg29/Kconfig.soc b/soc/silabs/silabs_s2/xg29/Kconfig.soc new file mode 100644 index 00000000000..f17bd7e5033 --- /dev/null +++ b/soc/silabs/silabs_s2/xg29/Kconfig.soc @@ -0,0 +1,58 @@ +# Copyright (c) 2025 Silicon Laboratories Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFR32BG29 + bool + select SOC_FAMILY_SILABS_S2 + help + Silicon Labs EFR32BG29 (Blue Gecko) Series MCU + +config SOC_SERIES_EFR32MG29 + bool + select SOC_FAMILY_SILABS_S2 + help + Silicon Labs EFR32MG29 (Mighty Gecko) Series MCU + +config SOC_PART_NUMBER_EFR32BG29B140F1024IM40 + bool + select SOC_SERIES_EFR32BG29 + +config SOC_PART_NUMBER_EFR32BG29B220F1024CJ45 + bool + select SOC_SERIES_EFR32BG29 + +config SOC_PART_NUMBER_EFR32BG29B221F1024CJ45 + bool + select SOC_SERIES_EFR32BG29 + +config SOC_PART_NUMBER_EFR32BG29B230F1024CM40 + bool + select SOC_SERIES_EFR32BG29 + +config SOC_PART_NUMBER_EFR32MG29B140F1024IM40 + bool + select SOC_SERIES_EFR32MG29 + +config SOC_PART_NUMBER_EFR32MG29B230F1024CM40 + bool + select SOC_SERIES_EFR32MG29 + +config SOC_SERIES + default "efr32bg29" if SOC_SERIES_EFR32BG29 + default "efr32mg29" if SOC_SERIES_EFR32MG29 + +config SOC + default "efr32bg29b140f1024im40" if SOC_PART_NUMBER_EFR32BG29B140F1024IM40 + default "efr32bg29b220f1024cj45" if SOC_PART_NUMBER_EFR32BG29B220F1024CJ45 + default "efr32bg29b221f1024cj45" if SOC_PART_NUMBER_EFR32BG29B221F1024CJ45 + default "efr32bg29b230f1024cm40" if SOC_PART_NUMBER_EFR32BG29B230F1024CM40 + default "efr32mg29b140f1024im40" if SOC_PART_NUMBER_EFR32MG29B140F1024IM40 + default "efr32mg29b230f1024cm40" if SOC_PART_NUMBER_EFR32MG29B230F1024CM40 + +config SOC_PART_NUMBER + default "EFR32BG29B140F1024IM40" if SOC_PART_NUMBER_EFR32BG29B140F1024IM40 + default "EFR32BG29B220F1024CJ45" if SOC_PART_NUMBER_EFR32BG29B220F1024CJ45 + default "EFR32BG29B221F1024CJ45" if SOC_PART_NUMBER_EFR32BG29B221F1024CJ45 + default "EFR32BG29B230F1024CM40" if SOC_PART_NUMBER_EFR32BG29B230F1024CM40 + default "EFR32MG29B140F1024IM40" if SOC_PART_NUMBER_EFR32MG29B140F1024IM40 + default "EFR32MG29B230F1024CM40" if SOC_PART_NUMBER_EFR32MG29B230F1024CM40 diff --git a/soc/silabs/soc.yml b/soc/silabs/soc.yml index bb933cca30e..a2e5bd96930 100644 --- a/soc/silabs/soc.yml +++ b/soc/silabs/soc.yml @@ -59,6 +59,16 @@ family: - name: efr32zg23 socs: - name: efr32zg23b020f512im48 + - name: efr32bg29 + socs: + - name: efr32bg29b140f1024im40 + - name: efr32bg29b220f1024cj45 + - name: efr32bg29b221f1024cj45 + - name: efr32bg29b230f1024cm40 + - name: efr32mg29 + socs: + - name: efr32mg29b140f1024im40 + - name: efr32mg29b230f1024cm40 - name: silabs_sim3 series: - name: sim3u diff --git a/west.yml b/west.yml index 82b2b88e3ac..03be7558420 100644 --- a/west.yml +++ b/west.yml @@ -228,7 +228,7 @@ manifest: groups: - hal - name: hal_silabs - revision: 220aac68ab8abaf5b0cf157ddb590a326f656e50 + revision: 5719804e682e9e4ba1d1f60c824af92a58ce1c2b path: modules/hal/silabs groups: - hal