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soc: silabs: siwx91x: Allow alternative memory partition

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Chip siwx91x has 672kB of SRAM shared between the Cortex-M4 (Zephyr) and
the NWP (Network Processor). 3 memory configurations are possible for
the Cortex-M4:
  - 196kB
  - 256kB
  - 320kB

Less memory is allocated to Zephyr, more memory is allocated to NWP,
better are the WiFi and BLE performances.

Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
This commit is contained in:
Jérôme Pouiller 2025-04-07 17:26:59 +02:00 • committed by Benjamin Cabé
commit 2bbafa7072
2 changed files with 27 additions and 6 deletions
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14
dts/arm/silabs/siwg917.dtsi
View file

@ -11,6 +11,7 @@
/ { / {
chosen { chosen {
zephyr,sram = &sram0;
zephyr,entropy = &rng0; zephyr,entropy = &rng0;
zephyr,flash = &flash0; zephyr,flash = &flash0;
zephyr,flash-controller = &flashctrl0; zephyr,flash-controller = &flashctrl0;
@ -28,8 +29,17 @@
sram0: memory@0 { sram0: memory@0 {
compatible = "mmio-sram"; compatible = "mmio-sram";
/* remove sram_dma0 region at the end of the sram */ /* siwx91x has 672kB of SRAM shared between the Cortex-M4
reg = <0x00000000 DT_SIZE_K(191)>; * (Zephyr) and the NWP (Network Processor). 3 memory
* configurations are
* possible:
* - 196kB
* - 256kB
* - 320kB
* Less memory is allocated to Zephyr, more memory is allocated
* to NWP, better are the WiFi and BLE performances.
*/
reg = <0x00000000 DT_SIZE_K(196)>;
}; };
sram_dma1: memory-dma@24061c00 { sram_dma1: memory-dma@24061c00 {

19
soc/silabs/silabs_siwx91x/siwg917/nwp.c
View file

@ -22,6 +22,10 @@
LOG_MODULE_REGISTER(siwx91x_nwp); LOG_MODULE_REGISTER(siwx91x_nwp);
BUILD_ASSERT(DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) == KB(196) ||
DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) == KB(256) ||
DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) == KB(320));
int siwg91x_get_nwp_config(int wifi_oper_mode, sl_wifi_device_configuration_t *get_config) int siwg91x_get_nwp_config(int wifi_oper_mode, sl_wifi_device_configuration_t *get_config)
{ {
sl_wifi_device_configuration_t default_config = { sl_wifi_device_configuration_t default_config = {
@ -32,15 +36,22 @@ int siwg91x_get_nwp_config(int wifi_oper_mode, sl_wifi_device_configuration_t *g
.feature_bit_map = SL_SI91X_FEAT_SECURITY_OPEN | SL_SI91X_FEAT_WPS_DISABLE, .feature_bit_map = SL_SI91X_FEAT_SECURITY_OPEN | SL_SI91X_FEAT_WPS_DISABLE,
.tcp_ip_feature_bit_map = SL_SI91X_TCP_IP_FEAT_EXTENSION_VALID, .tcp_ip_feature_bit_map = SL_SI91X_TCP_IP_FEAT_EXTENSION_VALID,
.custom_feature_bit_map = SL_SI91X_CUSTOM_FEAT_EXTENSION_VALID, .custom_feature_bit_map = SL_SI91X_CUSTOM_FEAT_EXTENSION_VALID,
.ext_custom_feature_bit_map = .ext_custom_feature_bit_map = SL_SI91X_EXT_FEAT_XTAL_CLK,
MEMORY_CONFIG |
SL_SI91X_EXT_FEAT_XTAL_CLK,
} }
}; };
sl_si91x_boot_configuration_t *boot_config = &default_config.boot_config;
__ASSERT(get_config, "get_config cannot be NULL"); __ASSERT(get_config, "get_config cannot be NULL");
sl_si91x_boot_configuration_t *boot_config = &default_config.boot_config; if (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) == KB(196)) {
boot_config->ext_custom_feature_bit_map |= SL_SI91X_EXT_FEAT_480K_M4SS_192K;
} else if (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) == KB(256)) {
boot_config->ext_custom_feature_bit_map |= SL_SI91X_EXT_FEAT_416K_M4SS_256K;
} else if (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) == KB(320)) {
boot_config->ext_custom_feature_bit_map |= SL_SI91X_EXT_FEAT_352K_M4SS_320K;
} else {
k_panic();
}
if (wifi_oper_mode == SL_SI91X_CLIENT_MODE) { if (wifi_oper_mode == SL_SI91X_CLIENT_MODE) {
boot_config->oper_mode = SL_SI91X_CLIENT_MODE; boot_config->oper_mode = SL_SI91X_CLIENT_MODE;