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drivers: nxp_enet: Re-add EXT RMII CLK config

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This config was missed when converting from eth_mcux to nxp_enet driver,
re-add it and use new one instead of old one.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
This commit is contained in:
Declan Snyder 2025-01-28 09:15:56 -06:00 • committed by Fabio Baltieri
commit 2ba6ba8494
6 changed files with 13 additions and 10 deletions
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2
boards/nxp/vmu_rt1170/Kconfig.defconfig
View file

@ -17,7 +17,7 @@ if NETWORKING
config NET_L2_ETHERNET config NET_L2_ETHERNET
default y if CPU_CORTEX_M7 # No cache memory support is required for driver default y if CPU_CORTEX_M7 # No cache memory support is required for driver
config ETH_MCUX_RMII_EXT_CLK config ETH_NXP_ENET_RMII_EXT_CLK
default y default y
endif # NETWORKING endif # NETWORKING

7
boards/segger/ip_k66f/Kconfig.defconfig
View file

@ -22,11 +22,8 @@ if NETWORKING
config NET_L2_ETHERNET config NET_L2_ETHERNET
default y default y
config ETH_MCUX_RMII_EXT_CLK config ETH_NXP_ENET_RMII_EXT_CLK
default y if ETH_MCUX default y
config ETH_MCUX_NO_PHY_SMI
default y if ETH_MCUX
endif # NETWORKING endif # NETWORKING

6
drivers/ethernet/nxp_enet/Kconfig
View file

@ -88,6 +88,12 @@ config ETH_NXP_ENET_RX_THREAD_PRIORITY
ENET MAC Driver handles RX in cooperative workqueue thread. ENET MAC Driver handles RX in cooperative workqueue thread.
This options sets the priority of that thread. This options sets the priority of that thread.
config ETH_NXP_ENET_RMII_EXT_CLK
bool "RMII clock from external sources"
help
Setting this option will configure ENET clock block to feed RMII
reference clock from external source (ENET_1588_CLKIN)
endif # ETH_NXP_ENET endif # ETH_NXP_ENET
if ETH_MCUX if ETH_MCUX

2
soc/nxp/imxrt/imxrt10xx/soc.c
View file

@ -227,7 +227,7 @@ __weak void clock_init(void)
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(enet)) && CONFIG_NET_L2_ETHERNET #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(enet)) && CONFIG_NET_L2_ETHERNET
#if CONFIG_ETH_MCUX_RMII_EXT_CLK #if CONFIG_ETH_NXP_ENET_RMII_EXT_CLK
/* Enable clock input for ENET1 */ /* Enable clock input for ENET1 */
IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, false); IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, false);
#else #else

4
soc/nxp/imxrt/imxrt11xx/soc.c
View file

@ -414,7 +414,7 @@ __weak void clock_init(void)
rootCfg.mux = kCLOCK_ENET1_ClockRoot_MuxSysPll1Div2; rootCfg.mux = kCLOCK_ENET1_ClockRoot_MuxSysPll1Div2;
rootCfg.div = 10; rootCfg.div = 10;
CLOCK_SetRootClock(kCLOCK_Root_Enet1, &rootCfg); CLOCK_SetRootClock(kCLOCK_Root_Enet1, &rootCfg);
#if CONFIG_ETH_MCUX_RMII_EXT_CLK #if CONFIG_ETH_NXP_ENET_RMII_EXT_CLK
/* Set ENET_REF_CLK as an input driven by PHY */ /* Set ENET_REF_CLK as an input driven by PHY */
IOMUXC_GPR->GPR4 &= ~IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR(0x01U); IOMUXC_GPR->GPR4 &= ~IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR(0x01U);
IOMUXC_GPR->GPR4 |= IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL(0x1U); IOMUXC_GPR->GPR4 |= IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL(0x1U);
@ -442,7 +442,7 @@ __weak void clock_init(void)
*/ */
rootCfg.div = 10; rootCfg.div = 10;
CLOCK_SetRootClock(kCLOCK_Root_Enet2, &rootCfg); CLOCK_SetRootClock(kCLOCK_Root_Enet2, &rootCfg);
#if CONFIG_ETH_MCUX_RMII_EXT_CLK #if CONFIG_ETH_NXP_ENET_RMII_EXT_CLK
/* Set ENET1G_REF_CLK as an input driven by PHY */ /* Set ENET1G_REF_CLK as an input driven by PHY */
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR(0x01U); IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR(0x01U);
IOMUXC_GPR->GPR5 |= IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL(0x1U); IOMUXC_GPR->GPR5 |= IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL(0x1U);

2
soc/nxp/kinetis/k6x/soc.c
View file

@ -108,7 +108,7 @@ __weak void clock_init(void)
#if CONFIG_ETH_MCUX || CONFIG_ETH_NXP_ENET #if CONFIG_ETH_MCUX || CONFIG_ETH_NXP_ENET
CLOCK_SetEnetTime0Clock(TIMESRC_OSCERCLK); CLOCK_SetEnetTime0Clock(TIMESRC_OSCERCLK);
#endif #endif
#if CONFIG_ETH_MCUX_RMII_EXT_CLK #if CONFIG_ETH_NXP_ENET_RMII_EXT_CLK
CLOCK_SetRmii0Clock(1); CLOCK_SetRmii0Clock(1);
#endif #endif
#if CONFIG_USB_KINETIS || CONFIG_UDC_KINETIS #if CONFIG_USB_KINETIS || CONFIG_UDC_KINETIS