2ba6ba8494
This config was missed when converting from eth_mcux to nxp_enet driver, re-add it and use new one instead of old one. Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
173 lines
4.4 KiB
C
173 lines
4.4 KiB
C
/*
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* Copyright (c) 2014-2015 Wind River Systems, Inc.
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief System/hardware module for fsl_frdm_k64f platform
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*
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* This module provides routines to initialize and support board-level
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* hardware for the fsl_frdm_k64f platform.
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <soc.h>
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#include <zephyr/drivers/uart.h>
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#include <fsl_common.h>
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#include <fsl_clock.h>
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#include <cmsis_core.h>
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#define LPUART0SRC_OSCERCLK (1)
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#define TIMESRC_OSCERCLK (2)
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#define RUNM_HSRUN (3)
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#define CLOCK_NODEID(clk) \
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DT_CHILD(DT_INST(0, nxp_kinetis_sim), clk)
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#define CLOCK_DIVIDER(clk) \
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DT_PROP_OR(CLOCK_NODEID(clk), clock_div, 1) - 1
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static const osc_config_t oscConfig = {
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.freq = CONFIG_OSC_XTAL0_FREQ,
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.capLoad = 0,
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#if defined(CONFIG_OSC_EXTERNAL)
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.workMode = kOSC_ModeExt,
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#elif defined(CONFIG_OSC_LOW_POWER)
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.workMode = kOSC_ModeOscLowPower,
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#elif defined(CONFIG_OSC_HIGH_GAIN)
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.workMode = kOSC_ModeOscHighGain,
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#else
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#error "An oscillator mode must be defined"
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#endif
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.oscerConfig = {
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.enableMode = kOSC_ErClkEnable,
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#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && \
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FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
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.erclkDiv = 0U,
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#endif
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},
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};
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static const mcg_pll_config_t pll0Config = {
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.enableMode = 0U,
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.prdiv = CONFIG_MCG_PRDIV0,
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.vdiv = CONFIG_MCG_VDIV0,
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};
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static const sim_clock_config_t simConfig = {
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.pllFllSel = DT_PROP(DT_INST(0, nxp_kinetis_sim), pllfll_select),
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.er32kSrc = DT_PROP(DT_INST(0, nxp_kinetis_sim), er32k_select),
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.clkdiv1 = SIM_CLKDIV1_OUTDIV1(CLOCK_DIVIDER(core_clk)) |
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SIM_CLKDIV1_OUTDIV2(CLOCK_DIVIDER(bus_clk)) |
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SIM_CLKDIV1_OUTDIV3(CLOCK_DIVIDER(flexbus_clk)) |
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SIM_CLKDIV1_OUTDIV4(CLOCK_DIVIDER(flash_clk)),
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};
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/**
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*
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* @brief Initialize the system clock
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*
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* This routine will configure the multipurpose clock generator (MCG) to
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* set up the system clock.
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* The MCG has nine possible modes, including Stop mode. This routine assumes
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* that the current MCG mode is FLL Engaged Internal (FEI), as from reset.
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* It transitions through the FLL Bypassed External (FBE) and
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* PLL Bypassed External (PBE) modes to get to the desired
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* PLL Engaged External (PEE) mode and generate the maximum 120 MHz system
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* clock.
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*
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*/
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__weak void clock_init(void)
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{
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CLOCK_SetSimSafeDivs();
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CLOCK_InitOsc0(&oscConfig);
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CLOCK_SetXtal0Freq(CONFIG_OSC_XTAL0_FREQ);
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CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &pll0Config);
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CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow,
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CONFIG_MCG_FCRDIV);
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CLOCK_SetSimConfig(&simConfig);
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#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart0))
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CLOCK_SetLpuartClock(LPUART0SRC_OSCERCLK);
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#endif
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#if CONFIG_ETH_MCUX || CONFIG_ETH_NXP_ENET
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CLOCK_SetEnetTime0Clock(TIMESRC_OSCERCLK);
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#endif
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#if CONFIG_ETH_NXP_ENET_RMII_EXT_CLK
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CLOCK_SetRmii0Clock(1);
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#endif
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#if CONFIG_USB_KINETIS || CONFIG_UDC_KINETIS
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CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcPll0,
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DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency));
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#endif
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}
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/**
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*
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* @brief Perform basic hardware initialization
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*
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* Initialize the interrupt controller device drivers.
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* Also initialize the timer device driver, if required.
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*
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*/
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void soc_early_init_hook(void)
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{
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#if !defined(CONFIG_ARM_MPU)
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uint32_t temp_reg;
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#endif /* !CONFIG_ARM_MPU */
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/* release I/O power hold to allow normal run state */
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PMC->REGSC |= PMC_REGSC_ACKISO_MASK;
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#ifdef CONFIG_TEMP_KINETIS
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/* enable bandgap buffer */
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PMC->REGSC |= PMC_REGSC_BGBE_MASK;
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#endif /* CONFIG_TEMP_KINETIS */
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#if !defined(CONFIG_ARM_MPU)
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/*
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* Disable memory protection and clear slave port errors.
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* Note that the K64F does not implement the optional ARMv7-M memory
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* protection unit (MPU), specified by the architecture (PMSAv7), in the
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* Cortex-M4 core. Instead, the processor includes its own MPU module.
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*/
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temp_reg = SYSMPU->CESR;
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temp_reg &= ~SYSMPU_CESR_VLD_MASK;
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temp_reg |= SYSMPU_CESR_SPERR_MASK;
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SYSMPU->CESR = temp_reg;
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#endif /* !CONFIG_ARM_MPU */
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#ifdef CONFIG_K6X_HSRUN
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/* Switch to HSRUN mode */
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SMC->PMPROT |= SMC_PMPROT_AHSRUN_MASK;
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SMC->PMCTRL = (SMC->PMCTRL & ~SMC_PMCTRL_RUNM_MASK) |
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SMC_PMCTRL_RUNM(RUNM_HSRUN);
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#endif
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/* Initialize PLL/system clock up to 180 MHz */
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clock_init();
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}
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#ifdef CONFIG_SOC_RESET_HOOK
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void soc_reset_hook(void)
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{
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SystemInit();
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}
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#endif /* CONFIG_SOC_RESET_HOOK */
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