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cavs_v25: switch over to Tigerlake H configuration

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Tigerlake H has less RAM and fewer cores. Both should be
supported, selectable at the board level. For now use the H
configuration as more readily available for testing.

Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
This commit is contained in:
Guennadi Liakhovetski 2021-01-04 16:30:47 +01:00 • committed by Anas Nashif
commit 2a6c70ab19
4 changed files with 6 additions and 6 deletions
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2
dts/xtensa/intel/intel_cavs25.dtsi
View file

@ -41,7 +41,7 @@
sram0: memory@be000000 { sram0: memory@be000000 {
device_type = "memory"; device_type = "memory";
compatible = "mmio-sram"; compatible = "mmio-sram";
reg = <0xbe000000 DT_SIZE_K(3008)>; reg = <0xbe000000 DT_SIZE_K(1920)>;
}; };
sram1: memory@be800000 { sram1: memory@be800000 {

3
samples/audio/sof/boards/intel_adsp_cavs25.conf
View file

@ -3,4 +3,5 @@ CONFIG_INTEL_DMIC=y
CONFIG_INTEL_SSP=y CONFIG_INTEL_SSP=y
CONFIG_INTEL_ALH=y CONFIG_INTEL_ALH=y
CONFIG_LP_MEMORY_BANKS=1 CONFIG_LP_MEMORY_BANKS=1
CONFIG_HP_MEMORY_BANKS=46 CONFIG_HP_MEMORY_BANKS=30
CONFIG_RIMAGE_SIGNING_SCHEMA="tgl-h"

5
soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h
View file

@ -97,11 +97,12 @@
/* low power ram where DMA buffers are typically placed */ /* low power ram where DMA buffers are typically placed */
#define LPRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1))) #define LPRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1)))
#define LPRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1))) #define LPRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1)))
#define SRAM_BANK_SIZE (64 * 1024)
/* bootloader */ /* bootloader */
#define HP_SRAM_BASE 0xbe000000 #define HP_SRAM_BASE 0xbe000000
#define HP_SRAM_SIZE (3008 * 1024) #define HP_SRAM_SIZE (30 * SRAM_BANK_SIZE)
#define SOF_STACK_BASE (HP_SRAM_BASE + HP_SRAM_SIZE) #define SOF_STACK_BASE (HP_SRAM_BASE + HP_SRAM_SIZE)
/* boot loader in IMR */ /* boot loader in IMR */
@ -224,8 +225,6 @@
/* Host page size */ /* Host page size */
#define HOST_PAGE_SIZE 4096 #define HOST_PAGE_SIZE 4096
#define SRAM_BANK_SIZE (64 * 1024)
/* LP SRAM */ /* LP SRAM */
#define LP_SRAM_BASE 0xBE800000 #define LP_SRAM_BASE 0xBE800000

2
soc/xtensa/intel_adsp/cavs_v25/include/soc/platform.h
View file

@ -19,7 +19,7 @@
#define MAX_CORE_COUNT 4 #define MAX_CORE_COUNT 4
#define PLATFORM_HPSRAM_EBB_COUNT 47 #define PLATFORM_HPSRAM_EBB_COUNT 30
#define EBB_SEGMENT_SIZE 32 #define EBB_SEGMENT_SIZE 32