From 2a6c70ab19fe06da486d390787fd07c5f8f96a82 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Mon, 4 Jan 2021 16:30:47 +0100 Subject: [PATCH] cavs_v25: switch over to Tigerlake H configuration Tigerlake H has less RAM and fewer cores. Both should be supported, selectable at the board level. For now use the H configuration as more readily available for testing. Signed-off-by: Guennadi Liakhovetski --- dts/xtensa/intel/intel_cavs25.dtsi | 2 +- samples/audio/sof/boards/intel_adsp_cavs25.conf | 3 ++- soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h | 5 ++--- soc/xtensa/intel_adsp/cavs_v25/include/soc/platform.h | 2 +- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/dts/xtensa/intel/intel_cavs25.dtsi b/dts/xtensa/intel/intel_cavs25.dtsi index c5ca9fd0b0a..63216316406 100644 --- a/dts/xtensa/intel/intel_cavs25.dtsi +++ b/dts/xtensa/intel/intel_cavs25.dtsi @@ -41,7 +41,7 @@ sram0: memory@be000000 { device_type = "memory"; compatible = "mmio-sram"; - reg = <0xbe000000 DT_SIZE_K(3008)>; + reg = <0xbe000000 DT_SIZE_K(1920)>; }; sram1: memory@be800000 { diff --git a/samples/audio/sof/boards/intel_adsp_cavs25.conf b/samples/audio/sof/boards/intel_adsp_cavs25.conf index 8c5d4e912b5..7ec23d23729 100644 --- a/samples/audio/sof/boards/intel_adsp_cavs25.conf +++ b/samples/audio/sof/boards/intel_adsp_cavs25.conf @@ -3,4 +3,5 @@ CONFIG_INTEL_DMIC=y CONFIG_INTEL_SSP=y CONFIG_INTEL_ALH=y CONFIG_LP_MEMORY_BANKS=1 -CONFIG_HP_MEMORY_BANKS=46 +CONFIG_HP_MEMORY_BANKS=30 +CONFIG_RIMAGE_SIGNING_SCHEMA="tgl-h" diff --git a/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h b/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h index cd365bf539f..42b9ca81d53 100644 --- a/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h +++ b/soc/xtensa/intel_adsp/cavs_v25/include/soc/memory.h @@ -97,11 +97,12 @@ /* low power ram where DMA buffers are typically placed */ #define LPRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram1))) #define LPRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram1))) +#define SRAM_BANK_SIZE (64 * 1024) /* bootloader */ #define HP_SRAM_BASE 0xbe000000 -#define HP_SRAM_SIZE (3008 * 1024) +#define HP_SRAM_SIZE (30 * SRAM_BANK_SIZE) #define SOF_STACK_BASE (HP_SRAM_BASE + HP_SRAM_SIZE) /* boot loader in IMR */ @@ -224,8 +225,6 @@ /* Host page size */ #define HOST_PAGE_SIZE 4096 -#define SRAM_BANK_SIZE (64 * 1024) - /* LP SRAM */ #define LP_SRAM_BASE 0xBE800000 diff --git a/soc/xtensa/intel_adsp/cavs_v25/include/soc/platform.h b/soc/xtensa/intel_adsp/cavs_v25/include/soc/platform.h index 9db1670f6b7..767c609a2ae 100644 --- a/soc/xtensa/intel_adsp/cavs_v25/include/soc/platform.h +++ b/soc/xtensa/intel_adsp/cavs_v25/include/soc/platform.h @@ -19,7 +19,7 @@ #define MAX_CORE_COUNT 4 -#define PLATFORM_HPSRAM_EBB_COUNT 47 +#define PLATFORM_HPSRAM_EBB_COUNT 30 #define EBB_SEGMENT_SIZE 32