boards: nxp: frdm_ke17z512: update dts to update bus_clk divider
Update the bus_clk divider value from 4 to 2 for frdm_ke17z512 platform. The bus and flash clocks are raised to 16Mhz to ensure that `tests.kernel.timer.timer_jitter_drift` sample passes. Signed-off-by: Anke Xiao <anke.xiao@nxp.com>
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@ -100,6 +100,12 @@
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status = "okay";
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};
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&scg {
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bus_clk {
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clock-div = <2>;
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};
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};
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&gpioe {
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status = "okay";
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};
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