From 2a1b924aa0f43481b7c12d1397ba749a5c621f57 Mon Sep 17 00:00:00 2001
From: Anke Xiao <anke.xiao@nxp.com>
Date: Tue, 13 Aug 2024 14:44:45 +0800
Subject: [PATCH] boards: nxp: frdm_ke17z512: update dts to update bus_clk
 divider

Update the bus_clk divider value from 4 to 2 for frdm_ke17z512
platform. The bus and flash clocks are raised to 16Mhz to ensure
that `tests.kernel.timer.timer_jitter_drift` sample passes.

Signed-off-by: Anke Xiao <anke.xiao@nxp.com>
---
 boards/nxp/frdm_ke17z512/frdm_ke17z512.dts | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/boards/nxp/frdm_ke17z512/frdm_ke17z512.dts b/boards/nxp/frdm_ke17z512/frdm_ke17z512.dts
index 7273431d51e..2212682f1f4 100644
--- a/boards/nxp/frdm_ke17z512/frdm_ke17z512.dts
+++ b/boards/nxp/frdm_ke17z512/frdm_ke17z512.dts
@@ -100,6 +100,12 @@
 	status = "okay";
 };
 
+&scg {
+	bus_clk {
+		clock-div = <2>;
+	};
+};
+
 &gpioe {
 	status = "okay";
 };