soc: renesas: ra: Move configs from board deconfig into SoC deconfig

- Move config BUILD_OUTPUT_HEX and CLOK_CONTROL from board deconfig
into SoC deconfig
- Add clock-frequency in dts to get config
SYS_CLOCK_HW_CYCLES_PER_SEC from dts

Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
This commit is contained in:
Quy Tran 2025-01-21 13:23:08 +07:00 committed by Benjamin Cabé
commit 292f7454d4
46 changed files with 180 additions and 82 deletions

View file

@ -6,4 +6,15 @@ if SOC_SERIES_RA2A1
config NUM_IRQS
default 32
DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
config BUILD_OUTPUT_HEX
default y
config CLOCK_CONTROL
default y
endif # SOC_SERIES_RA2A1

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@ -6,6 +6,17 @@ if SOC_SERIES_RA4E2
config NUM_IRQS
default 96
DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
config BUILD_OUTPUT_HEX
default y
config CLOCK_CONTROL
default y
# Set to the minimal size of data which can be written.
config FLASH_FILL_BUFFER_SIZE
default 128

View file

@ -6,6 +6,17 @@ if SOC_SERIES_RA4M2
config NUM_IRQS
default 96
DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
config BUILD_OUTPUT_HEX
default y
config CLOCK_CONTROL
default y
# Set to the minimal size of data which can be written.
config FLASH_FILL_BUFFER_SIZE
default 128

View file

@ -6,6 +6,17 @@ if SOC_SERIES_RA4M3
config NUM_IRQS
default 96
DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
config BUILD_OUTPUT_HEX
default y
config CLOCK_CONTROL
default y
# Set to the minimal size of data which can be written.
config FLASH_FILL_BUFFER_SIZE
default 128

View file

@ -6,4 +6,15 @@ if SOC_SERIES_RA4W1
config NUM_IRQS
default 32
DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
config BUILD_OUTPUT_HEX
default y
config CLOCK_CONTROL
default y
endif # SOC_SERIES_RA4W1

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@ -6,6 +6,17 @@ if SOC_SERIES_RA6E1
config NUM_IRQS
default 96
DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
config BUILD_OUTPUT_HEX
default y
config CLOCK_CONTROL
default y
# Set to the minimal size of data which can be written.
config FLASH_FILL_BUFFER_SIZE
default 128

View file

@ -6,6 +6,17 @@ if SOC_SERIES_RA6E2
config NUM_IRQS
default 96
DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
config BUILD_OUTPUT_HEX
default y
config CLOCK_CONTROL
default y
# Set to the minimal size of data which can be written.
config FLASH_FILL_BUFFER_SIZE
default 128

View file

@ -6,6 +6,17 @@ if SOC_SERIES_RA6M1
config NUM_IRQS
default 96
DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
config BUILD_OUTPUT_HEX
default y
config CLOCK_CONTROL
default y
# Set to the minimal size of data which can be written.
config FLASH_FILL_BUFFER_SIZE
default 128

View file

@ -6,6 +6,17 @@ if SOC_SERIES_RA6M2
config NUM_IRQS
default 96
DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
config BUILD_OUTPUT_HEX
default y
config CLOCK_CONTROL
default y
# Set to the minimal size of data which can be written.
config FLASH_FILL_BUFFER_SIZE
default 128

View file

@ -6,6 +6,17 @@ if SOC_SERIES_RA6M3
config NUM_IRQS
default 96
DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
config BUILD_OUTPUT_HEX
default y
config CLOCK_CONTROL
default y
# Set to the minimal size of data which can be written.
config FLASH_FILL_BUFFER_SIZE
default 128

View file

@ -6,6 +6,17 @@ if SOC_SERIES_RA6M4
config NUM_IRQS
default 96
DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
config BUILD_OUTPUT_HEX
default y
config CLOCK_CONTROL
default y
# Set to the minimal size of data which can be written.
config FLASH_FILL_BUFFER_SIZE
default 128

View file

@ -6,6 +6,17 @@ if SOC_SERIES_RA6M5
config NUM_IRQS
default 96
DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
config BUILD_OUTPUT_HEX
default y
config CLOCK_CONTROL
default y
# Set to the minimal size of data which can be written.
config FLASH_FILL_BUFFER_SIZE
default 128

View file

@ -6,6 +6,17 @@ if SOC_SERIES_RA8D1
config NUM_IRQS
default 96
DT_ICLK_PATH := $(dt_nodelabel_path,cpuclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
config BUILD_OUTPUT_HEX
default y
config CLOCK_CONTROL
default y
# Set to the minimal size of data which can be written.
config FLASH_FILL_BUFFER_SIZE
default 128

View file

@ -6,6 +6,17 @@ if SOC_SERIES_RA8M1
config NUM_IRQS
default 96
DT_ICLK_PATH := $(dt_nodelabel_path,cpuclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
config BUILD_OUTPUT_HEX
default y
config CLOCK_CONTROL
default y
# Set to the minimal size of data which can be written.
config FLASH_FILL_BUFFER_SIZE
default 128

View file

@ -6,6 +6,17 @@ if SOC_SERIES_RA8T1
config NUM_IRQS
default 96
DT_ICLK_PATH := $(dt_nodelabel_path,cpuclk)
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
config BUILD_OUTPUT_HEX
default y
config CLOCK_CONTROL
default y
# Set to the minimal size of data which can be written.
config FLASH_FILL_BUFFER_SIZE
default 128