clock: esp32: unify clock control for all espressif socs
This joins all clock control handling to same source by using hal clock functions. It also brings ESP32C3 clock support. Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This commit is contained in:
Sylvio Alves
Christopher Friedt
parent
2c08114c27
commit
27e44acda1
17 changed files with 116 additions and 479 deletions
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@ -32,6 +32,10 @@
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};
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};
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&cpu0 {
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clock-frequency = <ESP32_CLK_CPU_160M>;
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};
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&uart0 {
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status = "okay";
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current-speed = <115200>;
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@ -4,8 +4,6 @@ zephyr_library()
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_BEETLE beetle_clock_control.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_ESP32 clock_control_esp32.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_ESP32S2 clock_control_esp32s2.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_ESP32C3 clock_control_esp32c3.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_LITEX clock_control_litex.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_LPC11U6X clock_control_lpc11u6x.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCHP_XEC clock_control_mchp_xec.c)
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@ -54,10 +54,6 @@ source "drivers/clock_control/Kconfig.rv32m1"
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source "drivers/clock_control/Kconfig.esp32"
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source "drivers/clock_control/Kconfig.esp32s2"
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source "drivers/clock_control/Kconfig.esp32c3"
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source "drivers/clock_control/Kconfig.litex"
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source "drivers/clock_control/Kconfig.rcar"
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@ -5,6 +5,6 @@
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config CLOCK_CONTROL_ESP32
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bool "ESP32 Clock driver"
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depends on SOC_ESP32
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depends on SOC_ESP32 || SOC_ESP32S2 || SOC_ESP32C3
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help
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Enable support for ESP32 clock driver.
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@ -1,10 +0,0 @@
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# ESP32S2 Clock Driver configuration options
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# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
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# SPDX-License-Identifier: Apache-2.0
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config CLOCK_CONTROL_ESP32S2
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bool "ESP32S2 Clock driver"
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depends on SOC_ESP32S2
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help
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Enable support for ESP32S2 clock driver.
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@ -7,124 +7,60 @@
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#define DT_DRV_COMPAT espressif_esp32_rtc
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#define CPU_RESET_REASON RTC_SW_CPU_RESET
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#ifdef CONFIG_SOC_ESP32
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#define DT_CPU_COMPAT cdns_tensilica_xtensa_lx6
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#undef CPU_RESET_REASON
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#define CPU_RESET_REASON SW_CPU_RESET
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#include <dt-bindings/clock/esp32_clock.h>
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#include "esp32/rom/rtc.h"
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#include "soc/dport_reg.h"
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#elif defined(CONFIG_SOC_ESP32S2)
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#define DT_CPU_COMPAT cdns_tensilica_xtensa_lx7
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#include <dt-bindings/clock/esp32s2_clock.h>
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#include "esp32s2/rom/rtc.h"
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#elif CONFIG_IDF_TARGET_ESP32C3
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#define DT_CPU_COMPAT esp_riscv
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#include <dt-bindings/clock/esp32c3_clock.h>
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#include "esp32c3/rom/rtc.h"
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#include <soc/soc_caps.h>
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#include <soc/soc.h>
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#include <soc/rtc.h>
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#endif
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#include <soc/rtc.h>
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#include <soc/apb_ctrl_reg.h>
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#include <soc/timer_group_reg.h>
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#include <regi2c_ctrl.h>
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#include <hal/clk_gate_ll.h>
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#include <soc.h>
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#include <drivers/clock_control.h>
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#include <driver/periph_ctrl.h>
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#include "clock_control_esp32.h"
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#include <hal/cpu_hal.h>
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struct esp32_clock_config {
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uint32_t clk_src_sel;
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int clk_src_sel;
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uint32_t cpu_freq;
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uint32_t xtal_freq_sel;
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uint32_t xtal_div;
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int xtal_div;
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};
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#define DEV_CFG(dev) ((struct esp32_clock_config *)(dev->config))
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static uint32_t const xtal_freq[] = {
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static uint8_t const xtal_freq[] = {
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#ifdef CONFIG_SOC_ESP32
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[ESP32_CLK_XTAL_24M] = 24,
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[ESP32_CLK_XTAL_26M] = 26,
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[ESP32_CLK_XTAL_40M] = 40,
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[ESP32_CLK_XTAL_AUTO] = 0
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#elif defined(CONFIG_SOC_ESP32S2)
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[ESP32_CLK_XTAL_40M] = 40,
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#elif defined(CONFIG_SOC_ESP32C3)
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[ESP32_CLK_XTAL_32M] = 32,
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[ESP32_CLK_XTAL_40M] = 40,
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#endif
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};
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/* function prototypes */
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extern void rtc_clk_cpu_freq_to_xtal(int freq, int div);
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extern void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq);
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static inline uint32_t clk_val_to_reg_val(uint32_t val)
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{
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return (val & UINT16_MAX) | ((val & UINT16_MAX) << 16);
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}
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static void esp_clk_cpu_freq_to_8m(void)
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{
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ets_update_cpu_frequency(8);
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REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL);
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REG_SET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT, 0);
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REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_8M);
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rtc_clk_apb_freq_update(ESP32_FAST_CLK_FREQ_8M);
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}
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static void esp_clk_bbpll_disable(void)
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{
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SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG,
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RTC_CNTL_BB_I2C_FORCE_PD | RTC_CNTL_BBPLL_FORCE_PD |
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RTC_CNTL_BBPLL_I2C_FORCE_PD);
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/* is APLL under force power down? */
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uint32_t apll_fpd = REG_GET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD);
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if (apll_fpd) {
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/* then also power down the internal I2C bus */
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SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD);
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}
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}
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static void esp_clk_bbpll_enable(void)
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{
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CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG,
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RTC_CNTL_BIAS_I2C_FORCE_PD |
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RTC_CNTL_BB_I2C_FORCE_PD |
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RTC_CNTL_BBPLL_FORCE_PD |
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RTC_CNTL_BBPLL_I2C_FORCE_PD);
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/* reset BBPLL configuration */
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REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_IR_CAL_DELAY, BBPLL_IR_CAL_DELAY_VAL);
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REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_IR_CAL_EXT_CAP, BBPLL_IR_CAL_EXT_CAP_VAL);
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REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_ENB_FCAL, BBPLL_OC_ENB_FCAL_VAL);
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REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_ENB_VCON, BBPLL_OC_ENB_VCON_VAL);
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REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_BBADC_CAL_7_0, BBPLL_BBADC_CAL_7_0_VAL);
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}
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static void esp_clk_wait_for_slow_cycle(void)
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{
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REG_CLR_BIT(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING | TIMG_RTC_CALI_START);
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REG_CLR_BIT(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY);
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REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, RTC_CAL_RTC_MUX);
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/*
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* Request to run calibration for 0 slow clock cycles.
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* RDY bit will be set on the nearest slow clock cycle.
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*/
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REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, 0);
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REG_SET_BIT(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
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esp_rom_ets_delay_us(1); /* RDY needs some time to go low */
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while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)) {
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esp_rom_ets_delay_us(1);
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}
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}
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static int esp_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
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{
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int dbias = DIG_DBIAS_80M_160M;
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int per_conf = DPORT_CPUPERIOD_SEL_80;
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if (cpu_freq_mhz == 80) {
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/* nothing to do */
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} else if (cpu_freq_mhz == 160) {
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per_conf = DPORT_CPUPERIOD_SEL_160;
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} else if (cpu_freq_mhz == 240) {
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dbias = DIG_DBIAS_240M;
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per_conf = DPORT_CPUPERIOD_SEL_240;
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} else {
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return -EINVAL;
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}
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DPORT_REG_WRITE(DPORT_CPU_PER_CONF_REG, per_conf);
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REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, dbias);
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REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_PLL);
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rtc_clk_apb_freq_update(MHZ(80));
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ets_update_cpu_frequency(cpu_freq_mhz);
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esp_clk_wait_for_slow_cycle();
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return 0;
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}
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static int clock_control_esp32_on(const struct device *dev,
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clock_control_subsys_t sys)
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{
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@ -172,55 +108,62 @@ static int clock_control_esp32_get_rate(const struct device *dev,
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{
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ARG_UNUSED(sub_system);
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uint32_t xtal_freq_sel = DEV_CFG(dev)->xtal_freq_sel;
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uint32_t soc_clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL);
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rtc_cpu_freq_config_t config;
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rtc_clk_cpu_freq_get_config(&config);
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*rate = config.freq_mhz;
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switch (soc_clk_sel) {
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case RTC_CNTL_SOC_CLK_SEL_XTL:
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*rate = xtal_freq[xtal_freq_sel];
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return 0;
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case RTC_CNTL_SOC_CLK_SEL_PLL:
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*rate = MHZ(80);
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return 0;
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default:
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*rate = 0;
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return -ENOTSUP;
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}
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}
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static int clock_control_esp32_init(const struct device *dev)
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{
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struct esp32_clock_config *cfg = DEV_CFG(dev);
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uint32_t soc_clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL);
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rtc_cpu_freq_config_t old_config;
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rtc_cpu_freq_config_t new_config;
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bool res;
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if (soc_clk_sel != RTC_CNTL_SOC_CLK_SEL_XTL) {
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rtc_clk_cpu_freq_to_xtal(xtal_freq[cfg->xtal_freq_sel], 1);
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esp_clk_wait_for_slow_cycle();
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/* reset default config to use dts config */
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if (rtc_clk_apb_freq_get() < APB_CLK_FREQ || rtc_get_reset_reason(0) != CPU_RESET_REASON) {
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rtc_clk_config_t clk_cfg = RTC_CLK_CONFIG_DEFAULT();
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clk_cfg.xtal_freq = xtal_freq[cfg->xtal_freq_sel];
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clk_cfg.cpu_freq_mhz = cfg->cpu_freq;
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clk_cfg.slow_freq = rtc_clk_slow_freq_get();
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clk_cfg.fast_freq = rtc_clk_fast_freq_get();
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rtc_clk_init(clk_cfg);
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}
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if (soc_clk_sel == RTC_CNTL_SOC_CLK_SEL_PLL) {
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esp_clk_bbpll_disable();
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rtc_clk_fast_freq_set(RTC_FAST_FREQ_8M);
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rtc_clk_cpu_freq_get_config(&old_config);
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const uint32_t old_freq_mhz = old_config.freq_mhz;
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const uint32_t new_freq_mhz = cfg->cpu_freq;
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res = rtc_clk_cpu_freq_mhz_to_config(cfg->cpu_freq, &new_config);
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if (!res) {
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return -ENOTSUP;
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}
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switch (cfg->clk_src_sel) {
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case ESP32_CLK_SRC_XTAL:
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if (cfg->xtal_div > 1) {
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rtc_clk_cpu_freq_to_xtal(xtal_freq[cfg->xtal_freq_sel], cfg->xtal_div);
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/* wait uart output to be cleared */
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esp_rom_uart_tx_wait_idle(0);
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if (cfg->xtal_div >= 0) {
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new_config.div = cfg->xtal_div;
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}
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break;
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case ESP32_CLK_SRC_PLL:
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esp_clk_bbpll_enable();
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esp_clk_wait_for_slow_cycle();
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rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), cfg->cpu_freq);
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esp_clk_cpu_freq_to_pll_mhz(cfg->cpu_freq);
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break;
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case ESP32_CLK_SRC_RTC8M:
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esp_clk_cpu_freq_to_8m();
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break;
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default:
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return -EINVAL;
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if (cfg->clk_src_sel >= 0) {
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new_config.source = cfg->clk_src_sel;
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}
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/* set new configuration */
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rtc_clk_cpu_freq_set_config(&new_config);
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/* Re-calculate the ccount to make time calculation correct */
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cpu_hal_set_cycle_count((uint64_t)cpu_hal_get_cycle_count() * new_freq_mhz / old_freq_mhz);
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/* Enable RNG clock. */
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periph_module_enable(PERIPH_RNG_MODULE);
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@ -235,11 +178,19 @@ static const struct clock_control_driver_api clock_control_esp32_api = {
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.get_status = clock_control_esp32_get_status,
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};
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#define ESP32_CLOCK_SOURCE \
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COND_CODE_1(DT_NODE_HAS_PROP(DT_INST(0, DT_CPU_COMPAT), clock_source), \
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(DT_PROP(DT_INST(0, DT_CPU_COMPAT), clock_source)), (-1))
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#define ESP32_CLOCK_XTAL_DIV \
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COND_CODE_1(DT_NODE_HAS_PROP(0, xtal_div), \
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(DT_INST_PROP(0, xtal_div)), (-1))
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static const struct esp32_clock_config esp32_clock_config0 = {
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.clk_src_sel = DT_PROP(DT_INST(0, cdns_tensilica_xtensa_lx6), clock_source),
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.cpu_freq = DT_PROP(DT_INST(0, cdns_tensilica_xtensa_lx6), clock_frequency),
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.clk_src_sel = ESP32_CLOCK_SOURCE,
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.cpu_freq = DT_PROP(DT_INST(0, DT_CPU_COMPAT), clock_frequency),
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.xtal_freq_sel = DT_INST_PROP(0, xtal_freq),
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.xtal_div = DT_INST_PROP(0, xtal_div)
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.xtal_div = ESP32_CLOCK_XTAL_DIV
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};
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DEVICE_DT_DEFINE(DT_NODELABEL(rtc),
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@ -251,9 +202,8 @@ DEVICE_DT_DEFINE(DT_NODELABEL(rtc),
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CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
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&clock_control_esp32_api);
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#ifndef CONFIG_SOC_ESP32C3
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BUILD_ASSERT((CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) ==
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MHZ(DT_PROP(DT_INST(0, cdns_tensilica_xtensa_lx6), clock_frequency)),
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MHZ(DT_PROP(DT_INST(0, DT_CPU_COMPAT), clock_frequency)),
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"SYS_CLOCK_HW_CYCLES_PER_SEC Value must be equal to CPU_Freq");
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BUILD_ASSERT(DT_NODE_HAS_PROP(DT_INST(0, cdns_tensilica_xtensa_lx6), clock_source),
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"CPU clock-source property must be set to ESP32_CLK_SRC_XTAL or ESP32_CLK_SRC_PLL");
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#endif
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@ -1,72 +0,0 @@
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/*
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* Copyright (c) 2020 Mohamed ElShahawi.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_CLOCK_CONTROL_ESP32_CLOCK_H_
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#define ZEPHYR_DRIVERS_CLOCK_CONTROL_ESP32_CLOCK_H_
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#include <soc/efuse_reg.h>
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/*
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* Convenience macros for the above functions.
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*/
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#define I2C_WRITEREG_RTC(block, reg_add, indata) \
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esp_rom_i2c_writeReg(block, block##_HOSTID, reg_add, indata)
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#define I2C_READREG_RTC(block, reg_add) \
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esp_rom_i2c_readReg(block, block##_HOSTID, reg_add)
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/*
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* Get voltage level for CPU to run at 240 MHz, or for flash/PSRAM to run at 80 MHz.
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* 0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO)
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*/
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#define RTC_CNTL_DBIAS_HP_VOLT (RTC_CNTL_DBIAS_1V25 - (REG_GET_FIELD(EFUSE_BLK0_RDATA5_REG, EFUSE_RD_VOL_LEVEL_HP_INV)))
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#ifdef CONFIG_ESPTOOLPY_FLASHFREQ_80M
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#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_HP_VOLT
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#else
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#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_1V10
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#endif
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#define DIG_DBIAS_240M RTC_CNTL_DBIAS_HP_VOLT
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#define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10
|
||||
#define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00
|
||||
|
||||
#define DELAY_PLL_DBIAS_RAISE 3
|
||||
|
||||
/**
|
||||
* Register definitions for digital PLL (BBPLL)
|
||||
* This file lists register fields of BBPLL, located on an internal configuration
|
||||
* bus.
|
||||
*/
|
||||
#define I2C_BBPLL 0x66
|
||||
#define I2C_BBPLL_HOSTID 4
|
||||
#define I2C_BBPLL_IR_CAL_DELAY 0
|
||||
#define I2C_BBPLL_IR_CAL_EXT_CAP 1
|
||||
#define I2C_BBPLL_OC_LREF 2
|
||||
#define I2C_BBPLL_OC_DIV_7_0 3
|
||||
#define I2C_BBPLL_OC_ENB_FCAL 4
|
||||
#define I2C_BBPLL_OC_DCUR 5
|
||||
#define I2C_BBPLL_BBADC_DSMP 9
|
||||
#define I2C_BBPLL_OC_ENB_VCON 10
|
||||
#define I2C_BBPLL_ENDIV5 11
|
||||
#define I2C_BBPLL_BBADC_CAL_7_0 12
|
||||
|
||||
/* BBPLL configuration values */
|
||||
#define BBPLL_ENDIV5_VAL_320M 0x43
|
||||
#define BBPLL_BBADC_DSMP_VAL_320M 0x84
|
||||
#define BBPLL_ENDIV5_VAL_480M 0xc3
|
||||
#define BBPLL_BBADC_DSMP_VAL_480M 0x74
|
||||
#define BBPLL_IR_CAL_DELAY_VAL 0x18
|
||||
#define BBPLL_IR_CAL_EXT_CAP_VAL 0x20
|
||||
#define BBPLL_OC_ENB_FCAL_VAL 0x9a
|
||||
#define BBPLL_OC_ENB_VCON_VAL 0x00
|
||||
#define BBPLL_BBADC_CAL_7_0_VAL 0x00
|
||||
|
||||
#define ESP32_FAST_CLK_FREQ_8M 8500000
|
||||
|
||||
extern uint32_t esp_rom_g_ticks_per_us_pro;
|
||||
extern uint32_t esp_rom_g_ticks_per_us_app;
|
||||
extern void esp_rom_ets_delay_us(uint32_t us);
|
||||
|
||||
#endif /* ZEPHYR_DRIVERS_CLOCK_CONTROL_ESP32_CLOCK_H_ */
|
||||
|
|
@ -1,238 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#define DT_DRV_COMPAT espressif_esp32_rtc
|
||||
|
||||
#include <dt-bindings/clock/esp32s2_clock.h>
|
||||
#include <soc/rtc.h>
|
||||
#include <soc/apb_ctrl_reg.h>
|
||||
#include <soc/timer_group_reg.h>
|
||||
#include <regi2c_ctrl.h>
|
||||
#include <hal/clk_gate_ll.h>
|
||||
#include <rtc_clk_common.h>
|
||||
|
||||
#include <soc.h>
|
||||
#include <drivers/clock_control.h>
|
||||
#include <driver/periph_ctrl.h>
|
||||
|
||||
struct esp32_clock_config {
|
||||
uint32_t clk_src_sel;
|
||||
uint32_t cpu_freq;
|
||||
uint32_t xtal_freq_sel;
|
||||
uint32_t xtal_div;
|
||||
};
|
||||
|
||||
#define DEV_CFG(dev) ((struct esp32_clock_config *)(dev->config))
|
||||
|
||||
/*
|
||||
* Current PLL frequency, in MHZ (320 or 480). Zero if PLL is not enabled.
|
||||
* On the ESP32-S2, 480MHz PLL is enabled at reset.
|
||||
*/
|
||||
static uint32_t s_cur_pll_freq = 480U;
|
||||
|
||||
/* function prototypes */
|
||||
extern void rtc_clk_cpu_freq_to_xtal(int freq, int div);
|
||||
extern void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq);
|
||||
|
||||
static void esp_clk_cpu_freq_to_8m(void)
|
||||
{
|
||||
ets_update_cpu_frequency(8);
|
||||
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL);
|
||||
REG_SET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_PRE_DIV_CNT, 0);
|
||||
REG_SET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_SOC_CLK_SEL, DPORT_SOC_CLK_SEL_8M);
|
||||
rtc_clk_apb_freq_update(RTC_FAST_CLK_FREQ_8M);
|
||||
}
|
||||
|
||||
static void esp_clk_bbpll_disable(void)
|
||||
{
|
||||
SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PD |
|
||||
RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD);
|
||||
|
||||
s_cur_pll_freq = 0;
|
||||
}
|
||||
|
||||
static void esp_clk_bbpll_enable(void)
|
||||
{
|
||||
CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PD |
|
||||
RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD);
|
||||
}
|
||||
|
||||
static int esp_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
|
||||
{
|
||||
int dbias = DIG_DBIAS_80M_160M;
|
||||
int per_conf = DPORT_CPUPERIOD_SEL_80;
|
||||
|
||||
if (cpu_freq_mhz == 80) {
|
||||
/* nothing to do */
|
||||
} else if (cpu_freq_mhz == 160) {
|
||||
per_conf = DPORT_CPUPERIOD_SEL_160;
|
||||
} else if (cpu_freq_mhz == 240) {
|
||||
dbias = DIG_DBIAS_240M;
|
||||
per_conf = DPORT_CPUPERIOD_SEL_240;
|
||||
} else {
|
||||
return -EINVAL;
|
||||
}
|
||||
REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, per_conf);
|
||||
REG_SET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_PRE_DIV_CNT, 0);
|
||||
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, dbias);
|
||||
REG_SET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_SOC_CLK_SEL, DPORT_SOC_CLK_SEL_PLL);
|
||||
rtc_clk_apb_freq_update(MHZ(80));
|
||||
ets_update_cpu_frequency(cpu_freq_mhz);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int clock_control_esp32_on(const struct device *dev,
|
||||
clock_control_subsys_t sys)
|
||||
{
|
||||
ARG_UNUSED(dev);
|
||||
periph_module_enable((periph_module_t)sys);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int clock_control_esp32_off(const struct device *dev,
|
||||
clock_control_subsys_t sys)
|
||||
{
|
||||
ARG_UNUSED(dev);
|
||||
periph_module_disable((periph_module_t)sys);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int clock_control_esp32_async_on(const struct device *dev,
|
||||
clock_control_subsys_t sys,
|
||||
clock_control_cb_t cb,
|
||||
void *user_data)
|
||||
{
|
||||
ARG_UNUSED(dev);
|
||||
ARG_UNUSED(sys);
|
||||
ARG_UNUSED(cb);
|
||||
ARG_UNUSED(user_data);
|
||||
return -ENOTSUP;
|
||||
}
|
||||
|
||||
static enum clock_control_status clock_control_esp32_get_status(const struct device *dev,
|
||||
clock_control_subsys_t sys)
|
||||
{
|
||||
ARG_UNUSED(dev);
|
||||
uint32_t clk_en_reg = periph_ll_get_clk_en_reg((periph_module_t)sys);
|
||||
uint32_t clk_en_mask = periph_ll_get_clk_en_mask((periph_module_t)sys);
|
||||
|
||||
if (DPORT_GET_PERI_REG_MASK(clk_en_reg, clk_en_mask)) {
|
||||
return CLOCK_CONTROL_STATUS_ON;
|
||||
}
|
||||
return CLOCK_CONTROL_STATUS_OFF;
|
||||
}
|
||||
|
||||
static int clock_control_esp32_get_rate(const struct device *dev,
|
||||
clock_control_subsys_t sub_system,
|
||||
uint32_t *rate)
|
||||
{
|
||||
ARG_UNUSED(dev);
|
||||
ARG_UNUSED(sub_system);
|
||||
|
||||
uint32_t soc_clk_sel = REG_GET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_SOC_CLK_SEL);
|
||||
uint32_t cpuperiod_sel;
|
||||
uint32_t source_freq_mhz;
|
||||
uint32_t clk_div;
|
||||
|
||||
switch (soc_clk_sel) {
|
||||
case DPORT_SOC_CLK_SEL_XTAL:
|
||||
clk_div = REG_GET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_PRE_DIV_CNT) + 1;
|
||||
source_freq_mhz = (uint32_t) rtc_clk_xtal_freq_get();
|
||||
*rate = MHZ(source_freq_mhz / clk_div);
|
||||
return 0;
|
||||
case DPORT_SOC_CLK_SEL_PLL:
|
||||
cpuperiod_sel = DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL);
|
||||
if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_80) {
|
||||
*rate = MHZ(80);
|
||||
} else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_160) {
|
||||
*rate = MHZ(160);
|
||||
} else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_240) {
|
||||
*rate = MHZ(240);
|
||||
} else {
|
||||
*rate = 0;
|
||||
return -ENOTSUP;
|
||||
}
|
||||
return 0;
|
||||
case DPORT_SOC_CLK_SEL_8M:
|
||||
*rate = MHZ(8);
|
||||
return 0;
|
||||
default:
|
||||
*rate = 0;
|
||||
return -ENOTSUP;
|
||||
}
|
||||
}
|
||||
|
||||
static int clock_control_esp32_init(const struct device *dev)
|
||||
{
|
||||
struct esp32_clock_config *cfg = DEV_CFG(dev);
|
||||
uint32_t soc_clk_sel = cfg->clk_src_sel;
|
||||
rtc_cpu_freq_config_t cpu_freq_conf;
|
||||
|
||||
if (soc_clk_sel != DPORT_SOC_CLK_SEL_XTAL) {
|
||||
rtc_clk_cpu_freq_to_xtal(ESP32_CLK_CPU_40M, 1);
|
||||
}
|
||||
|
||||
if (soc_clk_sel == DPORT_SOC_CLK_SEL_PLL && cfg->cpu_freq != s_cur_pll_freq) {
|
||||
esp_clk_bbpll_disable();
|
||||
}
|
||||
|
||||
switch (cfg->clk_src_sel) {
|
||||
case ESP32_CLK_SRC_XTAL:
|
||||
if (cfg->xtal_freq_sel != ESP32_CLK_XTAL_40M) {
|
||||
return -ENOTSUP;
|
||||
}
|
||||
if (cfg->xtal_div > 1) {
|
||||
rtc_clk_cpu_freq_to_xtal(ESP32_CLK_CPU_40M, cfg->xtal_div);
|
||||
}
|
||||
break;
|
||||
case ESP32_CLK_SRC_PLL:
|
||||
esp_clk_bbpll_enable();
|
||||
rtc_clk_cpu_freq_mhz_to_config(cfg->cpu_freq, &cpu_freq_conf);
|
||||
rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), cpu_freq_conf.source_freq_mhz);
|
||||
s_cur_pll_freq = cfg->cpu_freq;
|
||||
esp_clk_cpu_freq_to_pll_mhz(cfg->cpu_freq);
|
||||
break;
|
||||
case ESP32_CLK_SRC_RTC8M:
|
||||
esp_clk_cpu_freq_to_8m();
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct clock_control_driver_api clock_control_esp32_api = {
|
||||
.on = clock_control_esp32_on,
|
||||
.off = clock_control_esp32_off,
|
||||
.async_on = clock_control_esp32_async_on,
|
||||
.get_rate = clock_control_esp32_get_rate,
|
||||
.get_status = clock_control_esp32_get_status,
|
||||
};
|
||||
|
||||
static const struct esp32_clock_config esp32_clock_config0 = {
|
||||
.clk_src_sel = DT_PROP(DT_INST(0, cdns_tensilica_xtensa_lx7), clock_source),
|
||||
.cpu_freq = DT_PROP(DT_INST(0, cdns_tensilica_xtensa_lx7), clock_frequency),
|
||||
.xtal_freq_sel = DT_INST_PROP(0, xtal_freq),
|
||||
.xtal_div = DT_INST_PROP(0, xtal_div)
|
||||
};
|
||||
|
||||
DEVICE_DT_DEFINE(DT_NODELABEL(rtc),
|
||||
&clock_control_esp32_init,
|
||||
NULL,
|
||||
NULL,
|
||||
&esp32_clock_config0,
|
||||
PRE_KERNEL_1,
|
||||
CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
|
||||
&clock_control_esp32_api);
|
||||
|
||||
BUILD_ASSERT((CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) ==
|
||||
MHZ(DT_PROP(DT_INST(0, cdns_tensilica_xtensa_lx7), clock_frequency)),
|
||||
"SYS_CLOCK_HW_CYCLES_PER_SEC Value must be equal to CPU_Freq");
|
||||
|
||||
BUILD_ASSERT(DT_NODE_HAS_PROP(DT_INST(0, cdns_tensilica_xtensa_lx7), clock_source),
|
||||
"CPU clock-source property must be set to ESP32_CLK_SRC_XTAL or ESP32_CLK_SRC_PLL");
|
||||
|
|
@ -17,11 +17,11 @@ properties:
|
|||
xtal-freq:
|
||||
type: int
|
||||
required: true
|
||||
description: Value of the extrernal XTAL connected to ESP32, Supported values 40M,26M
|
||||
description: Value of the external XTAL connected to ESP32.
|
||||
|
||||
xtal-div:
|
||||
type: int
|
||||
required: true
|
||||
required: false
|
||||
description: Divisor value for XTAL Clock, CPU_CLK = XTAL_FREQ / xtal-div
|
||||
|
||||
"#clock-cells":
|
||||
|
|
|
|||
14
dts/bindings/cpu/espressif,riscv.yml
Normal file
14
dts/bindings/cpu/espressif,riscv.yml
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Espressif RISC-V CPU
|
||||
|
||||
compatible: "esp,riscv"
|
||||
|
||||
include: cpu.yaml
|
||||
|
||||
properties:
|
||||
clock-source:
|
||||
type: int
|
||||
description: cpu clock source
|
||||
required: false
|
||||
|
|
@ -22,7 +22,7 @@
|
|||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "riscv";
|
||||
compatible = "esp,riscv";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
|
@ -66,7 +66,6 @@
|
|||
reg = <0x60008000 0x1000>;
|
||||
label = "RTC";
|
||||
xtal-freq = <ESP32_CLK_XTAL_40M>;
|
||||
xtal-div = <0>;
|
||||
#clock-cells = <1>;
|
||||
status = "ok";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -24,14 +24,12 @@
|
|||
device_type = "cpu";
|
||||
compatible = "cdns,tensilica-xtensa-lx6";
|
||||
reg = <0>;
|
||||
clock-source = <ESP32_CLK_SRC_PLL>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "cdns,tensilica-xtensa-lx6";
|
||||
reg = <1>;
|
||||
clock-source = <ESP32_CLK_SRC_PLL>;
|
||||
};
|
||||
|
||||
};
|
||||
|
|
@ -61,7 +59,6 @@
|
|||
reg = <0x3ff48000 0x0D8>;
|
||||
label = "RTC";
|
||||
xtal-freq = <ESP32_CLK_XTAL_40M>;
|
||||
xtal-div = <0>;
|
||||
#clock-cells = <1>;
|
||||
status = "ok";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -26,7 +26,6 @@
|
|||
device_type = "cpu";
|
||||
compatible = "cdns,tensilica-xtensa-lx7";
|
||||
reg = <0>;
|
||||
clock-source = <ESP32_CLK_SRC_PLL>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -60,7 +59,6 @@
|
|||
reg = <0x3f408000 0x0D8>;
|
||||
label = "RTC";
|
||||
xtal-freq = <ESP32_CLK_XTAL_40M>;
|
||||
xtal-div = <0>;
|
||||
#clock-cells = <1>;
|
||||
status = "ok";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -18,7 +18,8 @@
|
|||
#define ESP32_CLK_CPU_160M 160U
|
||||
|
||||
/* Supported XTAL Frequencies */
|
||||
#define ESP32_CLK_XTAL_40M 0U
|
||||
#define ESP32_CLK_XTAL_32M 0U
|
||||
#define ESP32_CLK_XTAL_40M 1U
|
||||
|
||||
/* Modules IDs
|
||||
* These IDs are actually offsets in CLK and RST Control registers.
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ config SOC_ESP32C3
|
|||
select RISCV_GP
|
||||
select DYNAMIC_INTERRUPTS
|
||||
select CLOCK_CONTROL
|
||||
select CLOCK_CONTROL_ESP32C3
|
||||
select CLOCK_CONTROL_ESP32
|
||||
|
||||
config IDF_TARGET_ESP32C3
|
||||
bool "ESP32C3 as target board"
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ config SOC_ESP32S2
|
|||
select ATOMIC_OPERATIONS_C
|
||||
select DYNAMIC_INTERRUPTS
|
||||
select CLOCK_CONTROL
|
||||
select CLOCK_CONTROL_ESP32S2
|
||||
select CLOCK_CONTROL_ESP32
|
||||
|
||||
if SOC_ESP32S2
|
||||
|
||||
|
|
|
|||
2
west.yml
2
west.yml
|
|
@ -67,7 +67,7 @@ manifest:
|
|||
groups:
|
||||
- hal
|
||||
- name: hal_espressif
|
||||
revision: 2bb8d91a5e82418ff673090ca1feb18eb82c5e5c
|
||||
revision: 5c2062876f86fbf3aa30f3e2539a88b56b8fd461
|
||||
path: modules/hal/espressif
|
||||
west-commands: west/west-commands.yml
|
||||
groups:
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue