From 27e44acda185dde92243e056d77d0e21441c96ef Mon Sep 17 00:00:00 2001 From: Sylvio Alves Date: Wed, 20 Oct 2021 20:11:53 -0300 Subject: [PATCH] clock: esp32: unify clock control for all espressif socs This joins all clock control handling to same source by using hal clock functions. It also brings ESP32C3 clock support. Signed-off-by: Sylvio Alves --- .../riscv/esp32c3_devkitm/esp32c3_devkitm.dts | 4 + drivers/clock_control/CMakeLists.txt | 2 - drivers/clock_control/Kconfig | 4 - drivers/clock_control/Kconfig.esp32 | 2 +- drivers/clock_control/Kconfig.esp32s2 | 10 - drivers/clock_control/clock_control_esp32.c | 228 +++++++---------- drivers/clock_control/clock_control_esp32.h | 72 ------ drivers/clock_control/clock_control_esp32s2.c | 238 ------------------ dts/bindings/clock/espressif,esp32-rtc.yaml | 4 +- dts/bindings/cpu/espressif,riscv.yml | 14 ++ dts/riscv/espressif/esp32c3.dtsi | 3 +- dts/xtensa/espressif/esp32.dtsi | 3 - dts/xtensa/espressif/esp32s2.dtsi | 2 - include/dt-bindings/clock/esp32c3_clock.h | 3 +- soc/riscv/esp32c3/Kconfig.soc | 2 +- soc/xtensa/esp32s2/Kconfig.soc | 2 +- west.yml | 2 +- 17 files changed, 116 insertions(+), 479 deletions(-) delete mode 100644 drivers/clock_control/Kconfig.esp32s2 delete mode 100644 drivers/clock_control/clock_control_esp32.h delete mode 100644 drivers/clock_control/clock_control_esp32s2.c create mode 100644 dts/bindings/cpu/espressif,riscv.yml diff --git a/boards/riscv/esp32c3_devkitm/esp32c3_devkitm.dts b/boards/riscv/esp32c3_devkitm/esp32c3_devkitm.dts index 4cced405970..995659a5398 100644 --- a/boards/riscv/esp32c3_devkitm/esp32c3_devkitm.dts +++ b/boards/riscv/esp32c3_devkitm/esp32c3_devkitm.dts @@ -32,6 +32,10 @@ }; }; +&cpu0 { + clock-frequency = ; +}; + &uart0 { status = "okay"; current-speed = <115200>; diff --git a/drivers/clock_control/CMakeLists.txt b/drivers/clock_control/CMakeLists.txt index 74d813e8ca8..058c5a0cc94 100644 --- a/drivers/clock_control/CMakeLists.txt +++ b/drivers/clock_control/CMakeLists.txt @@ -4,8 +4,6 @@ zephyr_library() zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_BEETLE beetle_clock_control.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_ESP32 clock_control_esp32.c) -zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_ESP32S2 clock_control_esp32s2.c) -zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_ESP32C3 clock_control_esp32c3.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_LITEX clock_control_litex.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_LPC11U6X clock_control_lpc11u6x.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCHP_XEC clock_control_mchp_xec.c) diff --git a/drivers/clock_control/Kconfig b/drivers/clock_control/Kconfig index 3912a83b85b..b68d1f14e6c 100644 --- a/drivers/clock_control/Kconfig +++ b/drivers/clock_control/Kconfig @@ -54,10 +54,6 @@ source "drivers/clock_control/Kconfig.rv32m1" source "drivers/clock_control/Kconfig.esp32" -source "drivers/clock_control/Kconfig.esp32s2" - -source "drivers/clock_control/Kconfig.esp32c3" - source "drivers/clock_control/Kconfig.litex" source "drivers/clock_control/Kconfig.rcar" diff --git a/drivers/clock_control/Kconfig.esp32 b/drivers/clock_control/Kconfig.esp32 index 9dc77aa24b8..d9f9031b356 100644 --- a/drivers/clock_control/Kconfig.esp32 +++ b/drivers/clock_control/Kconfig.esp32 @@ -5,6 +5,6 @@ config CLOCK_CONTROL_ESP32 bool "ESP32 Clock driver" - depends on SOC_ESP32 + depends on SOC_ESP32 || SOC_ESP32S2 || SOC_ESP32C3 help Enable support for ESP32 clock driver. diff --git a/drivers/clock_control/Kconfig.esp32s2 b/drivers/clock_control/Kconfig.esp32s2 deleted file mode 100644 index 50821cfd1e0..00000000000 --- a/drivers/clock_control/Kconfig.esp32s2 +++ /dev/null @@ -1,10 +0,0 @@ -# ESP32S2 Clock Driver configuration options - -# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config CLOCK_CONTROL_ESP32S2 - bool "ESP32S2 Clock driver" - depends on SOC_ESP32S2 - help - Enable support for ESP32S2 clock driver. diff --git a/drivers/clock_control/clock_control_esp32.c b/drivers/clock_control/clock_control_esp32.c index 04e4f61a2a3..b91f2f1e41b 100644 --- a/drivers/clock_control/clock_control_esp32.c +++ b/drivers/clock_control/clock_control_esp32.c @@ -7,124 +7,60 @@ #define DT_DRV_COMPAT espressif_esp32_rtc +#define CPU_RESET_REASON RTC_SW_CPU_RESET + +#ifdef CONFIG_SOC_ESP32 +#define DT_CPU_COMPAT cdns_tensilica_xtensa_lx6 +#undef CPU_RESET_REASON +#define CPU_RESET_REASON SW_CPU_RESET #include +#include "esp32/rom/rtc.h" +#include "soc/dport_reg.h" +#elif defined(CONFIG_SOC_ESP32S2) +#define DT_CPU_COMPAT cdns_tensilica_xtensa_lx7 +#include +#include "esp32s2/rom/rtc.h" +#elif CONFIG_IDF_TARGET_ESP32C3 +#define DT_CPU_COMPAT esp_riscv +#include +#include "esp32c3/rom/rtc.h" +#include +#include +#include +#endif + #include #include #include -#include #include - #include #include #include -#include "clock_control_esp32.h" +#include struct esp32_clock_config { - uint32_t clk_src_sel; + int clk_src_sel; uint32_t cpu_freq; uint32_t xtal_freq_sel; - uint32_t xtal_div; + int xtal_div; }; #define DEV_CFG(dev) ((struct esp32_clock_config *)(dev->config)) -static uint32_t const xtal_freq[] = { +static uint8_t const xtal_freq[] = { +#ifdef CONFIG_SOC_ESP32 [ESP32_CLK_XTAL_24M] = 24, [ESP32_CLK_XTAL_26M] = 26, [ESP32_CLK_XTAL_40M] = 40, [ESP32_CLK_XTAL_AUTO] = 0 +#elif defined(CONFIG_SOC_ESP32S2) + [ESP32_CLK_XTAL_40M] = 40, +#elif defined(CONFIG_SOC_ESP32C3) + [ESP32_CLK_XTAL_32M] = 32, + [ESP32_CLK_XTAL_40M] = 40, +#endif }; -/* function prototypes */ -extern void rtc_clk_cpu_freq_to_xtal(int freq, int div); -extern void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq); - -static inline uint32_t clk_val_to_reg_val(uint32_t val) -{ - return (val & UINT16_MAX) | ((val & UINT16_MAX) << 16); -} - -static void esp_clk_cpu_freq_to_8m(void) -{ - ets_update_cpu_frequency(8); - REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL); - REG_SET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT, 0); - REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_8M); - rtc_clk_apb_freq_update(ESP32_FAST_CLK_FREQ_8M); -} - -static void esp_clk_bbpll_disable(void) -{ - SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, - RTC_CNTL_BB_I2C_FORCE_PD | RTC_CNTL_BBPLL_FORCE_PD | - RTC_CNTL_BBPLL_I2C_FORCE_PD); - - /* is APLL under force power down? */ - uint32_t apll_fpd = REG_GET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD); - - if (apll_fpd) { - /* then also power down the internal I2C bus */ - SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD); - } -} - -static void esp_clk_bbpll_enable(void) -{ - CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, - RTC_CNTL_BIAS_I2C_FORCE_PD | - RTC_CNTL_BB_I2C_FORCE_PD | - RTC_CNTL_BBPLL_FORCE_PD | - RTC_CNTL_BBPLL_I2C_FORCE_PD); - - /* reset BBPLL configuration */ - REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_IR_CAL_DELAY, BBPLL_IR_CAL_DELAY_VAL); - REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_IR_CAL_EXT_CAP, BBPLL_IR_CAL_EXT_CAP_VAL); - REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_ENB_FCAL, BBPLL_OC_ENB_FCAL_VAL); - REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_ENB_VCON, BBPLL_OC_ENB_VCON_VAL); - REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_BBADC_CAL_7_0, BBPLL_BBADC_CAL_7_0_VAL); -} - -static void esp_clk_wait_for_slow_cycle(void) -{ - REG_CLR_BIT(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING | TIMG_RTC_CALI_START); - REG_CLR_BIT(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY); - REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, RTC_CAL_RTC_MUX); - /* - * Request to run calibration for 0 slow clock cycles. - * RDY bit will be set on the nearest slow clock cycle. - */ - REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, 0); - REG_SET_BIT(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START); - esp_rom_ets_delay_us(1); /* RDY needs some time to go low */ - while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)) { - esp_rom_ets_delay_us(1); - } -} - -static int esp_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz) -{ - int dbias = DIG_DBIAS_80M_160M; - int per_conf = DPORT_CPUPERIOD_SEL_80; - - if (cpu_freq_mhz == 80) { - /* nothing to do */ - } else if (cpu_freq_mhz == 160) { - per_conf = DPORT_CPUPERIOD_SEL_160; - } else if (cpu_freq_mhz == 240) { - dbias = DIG_DBIAS_240M; - per_conf = DPORT_CPUPERIOD_SEL_240; - } else { - return -EINVAL; - } - DPORT_REG_WRITE(DPORT_CPU_PER_CONF_REG, per_conf); - REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, dbias); - REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_PLL); - rtc_clk_apb_freq_update(MHZ(80)); - ets_update_cpu_frequency(cpu_freq_mhz); - esp_clk_wait_for_slow_cycle(); - return 0; -} - static int clock_control_esp32_on(const struct device *dev, clock_control_subsys_t sys) { @@ -172,55 +108,62 @@ static int clock_control_esp32_get_rate(const struct device *dev, { ARG_UNUSED(sub_system); - uint32_t xtal_freq_sel = DEV_CFG(dev)->xtal_freq_sel; - uint32_t soc_clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL); + rtc_cpu_freq_config_t config; - switch (soc_clk_sel) { - case RTC_CNTL_SOC_CLK_SEL_XTL: - *rate = xtal_freq[xtal_freq_sel]; - return 0; - case RTC_CNTL_SOC_CLK_SEL_PLL: - *rate = MHZ(80); - return 0; - default: - *rate = 0; - return -ENOTSUP; - } + rtc_clk_cpu_freq_get_config(&config); + + *rate = config.freq_mhz; + + return 0; } static int clock_control_esp32_init(const struct device *dev) { struct esp32_clock_config *cfg = DEV_CFG(dev); - uint32_t soc_clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL); + rtc_cpu_freq_config_t old_config; + rtc_cpu_freq_config_t new_config; + bool res; - if (soc_clk_sel != RTC_CNTL_SOC_CLK_SEL_XTL) { - rtc_clk_cpu_freq_to_xtal(xtal_freq[cfg->xtal_freq_sel], 1); - esp_clk_wait_for_slow_cycle(); + /* reset default config to use dts config */ + if (rtc_clk_apb_freq_get() < APB_CLK_FREQ || rtc_get_reset_reason(0) != CPU_RESET_REASON) { + rtc_clk_config_t clk_cfg = RTC_CLK_CONFIG_DEFAULT(); + + clk_cfg.xtal_freq = xtal_freq[cfg->xtal_freq_sel]; + clk_cfg.cpu_freq_mhz = cfg->cpu_freq; + clk_cfg.slow_freq = rtc_clk_slow_freq_get(); + clk_cfg.fast_freq = rtc_clk_fast_freq_get(); + rtc_clk_init(clk_cfg); } - if (soc_clk_sel == RTC_CNTL_SOC_CLK_SEL_PLL) { - esp_clk_bbpll_disable(); + rtc_clk_fast_freq_set(RTC_FAST_FREQ_8M); + + rtc_clk_cpu_freq_get_config(&old_config); + + const uint32_t old_freq_mhz = old_config.freq_mhz; + const uint32_t new_freq_mhz = cfg->cpu_freq; + + res = rtc_clk_cpu_freq_mhz_to_config(cfg->cpu_freq, &new_config); + if (!res) { + return -ENOTSUP; } - switch (cfg->clk_src_sel) { - case ESP32_CLK_SRC_XTAL: - if (cfg->xtal_div > 1) { - rtc_clk_cpu_freq_to_xtal(xtal_freq[cfg->xtal_freq_sel], cfg->xtal_div); - } - break; - case ESP32_CLK_SRC_PLL: - esp_clk_bbpll_enable(); - esp_clk_wait_for_slow_cycle(); - rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), cfg->cpu_freq); - esp_clk_cpu_freq_to_pll_mhz(cfg->cpu_freq); - break; - case ESP32_CLK_SRC_RTC8M: - esp_clk_cpu_freq_to_8m(); - break; - default: - return -EINVAL; + /* wait uart output to be cleared */ + esp_rom_uart_tx_wait_idle(0); + + if (cfg->xtal_div >= 0) { + new_config.div = cfg->xtal_div; } + if (cfg->clk_src_sel >= 0) { + new_config.source = cfg->clk_src_sel; + } + + /* set new configuration */ + rtc_clk_cpu_freq_set_config(&new_config); + + /* Re-calculate the ccount to make time calculation correct */ + cpu_hal_set_cycle_count((uint64_t)cpu_hal_get_cycle_count() * new_freq_mhz / old_freq_mhz); + /* Enable RNG clock. */ periph_module_enable(PERIPH_RNG_MODULE); @@ -235,11 +178,19 @@ static const struct clock_control_driver_api clock_control_esp32_api = { .get_status = clock_control_esp32_get_status, }; +#define ESP32_CLOCK_SOURCE \ + COND_CODE_1(DT_NODE_HAS_PROP(DT_INST(0, DT_CPU_COMPAT), clock_source), \ + (DT_PROP(DT_INST(0, DT_CPU_COMPAT), clock_source)), (-1)) + +#define ESP32_CLOCK_XTAL_DIV \ + COND_CODE_1(DT_NODE_HAS_PROP(0, xtal_div), \ + (DT_INST_PROP(0, xtal_div)), (-1)) + static const struct esp32_clock_config esp32_clock_config0 = { - .clk_src_sel = DT_PROP(DT_INST(0, cdns_tensilica_xtensa_lx6), clock_source), - .cpu_freq = DT_PROP(DT_INST(0, cdns_tensilica_xtensa_lx6), clock_frequency), + .clk_src_sel = ESP32_CLOCK_SOURCE, + .cpu_freq = DT_PROP(DT_INST(0, DT_CPU_COMPAT), clock_frequency), .xtal_freq_sel = DT_INST_PROP(0, xtal_freq), - .xtal_div = DT_INST_PROP(0, xtal_div) + .xtal_div = ESP32_CLOCK_XTAL_DIV }; DEVICE_DT_DEFINE(DT_NODELABEL(rtc), @@ -251,9 +202,8 @@ DEVICE_DT_DEFINE(DT_NODELABEL(rtc), CONFIG_CLOCK_CONTROL_INIT_PRIORITY, &clock_control_esp32_api); +#ifndef CONFIG_SOC_ESP32C3 BUILD_ASSERT((CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) == - MHZ(DT_PROP(DT_INST(0, cdns_tensilica_xtensa_lx6), clock_frequency)), + MHZ(DT_PROP(DT_INST(0, DT_CPU_COMPAT), clock_frequency)), "SYS_CLOCK_HW_CYCLES_PER_SEC Value must be equal to CPU_Freq"); - -BUILD_ASSERT(DT_NODE_HAS_PROP(DT_INST(0, cdns_tensilica_xtensa_lx6), clock_source), - "CPU clock-source property must be set to ESP32_CLK_SRC_XTAL or ESP32_CLK_SRC_PLL"); +#endif diff --git a/drivers/clock_control/clock_control_esp32.h b/drivers/clock_control/clock_control_esp32.h deleted file mode 100644 index 4cb0a540bbb..00000000000 --- a/drivers/clock_control/clock_control_esp32.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright (c) 2020 Mohamed ElShahawi. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef ZEPHYR_DRIVERS_CLOCK_CONTROL_ESP32_CLOCK_H_ -#define ZEPHYR_DRIVERS_CLOCK_CONTROL_ESP32_CLOCK_H_ - -#include - -/* - * Convenience macros for the above functions. - */ -#define I2C_WRITEREG_RTC(block, reg_add, indata) \ - esp_rom_i2c_writeReg(block, block##_HOSTID, reg_add, indata) - -#define I2C_READREG_RTC(block, reg_add) \ - esp_rom_i2c_readReg(block, block##_HOSTID, reg_add) - -/* - * Get voltage level for CPU to run at 240 MHz, or for flash/PSRAM to run at 80 MHz. - * 0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO) - */ -#define RTC_CNTL_DBIAS_HP_VOLT (RTC_CNTL_DBIAS_1V25 - (REG_GET_FIELD(EFUSE_BLK0_RDATA5_REG, EFUSE_RD_VOL_LEVEL_HP_INV))) -#ifdef CONFIG_ESPTOOLPY_FLASHFREQ_80M -#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_HP_VOLT -#else -#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_1V10 -#endif -#define DIG_DBIAS_240M RTC_CNTL_DBIAS_HP_VOLT -#define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10 -#define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00 - -#define DELAY_PLL_DBIAS_RAISE 3 - -/** - * Register definitions for digital PLL (BBPLL) - * This file lists register fields of BBPLL, located on an internal configuration - * bus. - */ -#define I2C_BBPLL 0x66 -#define I2C_BBPLL_HOSTID 4 -#define I2C_BBPLL_IR_CAL_DELAY 0 -#define I2C_BBPLL_IR_CAL_EXT_CAP 1 -#define I2C_BBPLL_OC_LREF 2 -#define I2C_BBPLL_OC_DIV_7_0 3 -#define I2C_BBPLL_OC_ENB_FCAL 4 -#define I2C_BBPLL_OC_DCUR 5 -#define I2C_BBPLL_BBADC_DSMP 9 -#define I2C_BBPLL_OC_ENB_VCON 10 -#define I2C_BBPLL_ENDIV5 11 -#define I2C_BBPLL_BBADC_CAL_7_0 12 - -/* BBPLL configuration values */ -#define BBPLL_ENDIV5_VAL_320M 0x43 -#define BBPLL_BBADC_DSMP_VAL_320M 0x84 -#define BBPLL_ENDIV5_VAL_480M 0xc3 -#define BBPLL_BBADC_DSMP_VAL_480M 0x74 -#define BBPLL_IR_CAL_DELAY_VAL 0x18 -#define BBPLL_IR_CAL_EXT_CAP_VAL 0x20 -#define BBPLL_OC_ENB_FCAL_VAL 0x9a -#define BBPLL_OC_ENB_VCON_VAL 0x00 -#define BBPLL_BBADC_CAL_7_0_VAL 0x00 - -#define ESP32_FAST_CLK_FREQ_8M 8500000 - -extern uint32_t esp_rom_g_ticks_per_us_pro; -extern uint32_t esp_rom_g_ticks_per_us_app; -extern void esp_rom_ets_delay_us(uint32_t us); - -#endif /* ZEPHYR_DRIVERS_CLOCK_CONTROL_ESP32_CLOCK_H_ */ diff --git a/drivers/clock_control/clock_control_esp32s2.c b/drivers/clock_control/clock_control_esp32s2.c deleted file mode 100644 index 47f3baae557..00000000000 --- a/drivers/clock_control/clock_control_esp32s2.c +++ /dev/null @@ -1,238 +0,0 @@ -/* - * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#define DT_DRV_COMPAT espressif_esp32_rtc - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -struct esp32_clock_config { - uint32_t clk_src_sel; - uint32_t cpu_freq; - uint32_t xtal_freq_sel; - uint32_t xtal_div; -}; - -#define DEV_CFG(dev) ((struct esp32_clock_config *)(dev->config)) - -/* - * Current PLL frequency, in MHZ (320 or 480). Zero if PLL is not enabled. - * On the ESP32-S2, 480MHz PLL is enabled at reset. - */ -static uint32_t s_cur_pll_freq = 480U; - -/* function prototypes */ -extern void rtc_clk_cpu_freq_to_xtal(int freq, int div); -extern void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq); - -static void esp_clk_cpu_freq_to_8m(void) -{ - ets_update_cpu_frequency(8); - REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL); - REG_SET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_PRE_DIV_CNT, 0); - REG_SET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_SOC_CLK_SEL, DPORT_SOC_CLK_SEL_8M); - rtc_clk_apb_freq_update(RTC_FAST_CLK_FREQ_8M); -} - -static void esp_clk_bbpll_disable(void) -{ - SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PD | - RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD); - - s_cur_pll_freq = 0; -} - -static void esp_clk_bbpll_enable(void) -{ - CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PD | - RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD); -} - -static int esp_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz) -{ - int dbias = DIG_DBIAS_80M_160M; - int per_conf = DPORT_CPUPERIOD_SEL_80; - - if (cpu_freq_mhz == 80) { - /* nothing to do */ - } else if (cpu_freq_mhz == 160) { - per_conf = DPORT_CPUPERIOD_SEL_160; - } else if (cpu_freq_mhz == 240) { - dbias = DIG_DBIAS_240M; - per_conf = DPORT_CPUPERIOD_SEL_240; - } else { - return -EINVAL; - } - REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, per_conf); - REG_SET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_PRE_DIV_CNT, 0); - REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, dbias); - REG_SET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_SOC_CLK_SEL, DPORT_SOC_CLK_SEL_PLL); - rtc_clk_apb_freq_update(MHZ(80)); - ets_update_cpu_frequency(cpu_freq_mhz); - - return 0; -} - -static int clock_control_esp32_on(const struct device *dev, - clock_control_subsys_t sys) -{ - ARG_UNUSED(dev); - periph_module_enable((periph_module_t)sys); - return 0; -} - -static int clock_control_esp32_off(const struct device *dev, - clock_control_subsys_t sys) -{ - ARG_UNUSED(dev); - periph_module_disable((periph_module_t)sys); - return 0; -} - -static int clock_control_esp32_async_on(const struct device *dev, - clock_control_subsys_t sys, - clock_control_cb_t cb, - void *user_data) -{ - ARG_UNUSED(dev); - ARG_UNUSED(sys); - ARG_UNUSED(cb); - ARG_UNUSED(user_data); - return -ENOTSUP; -} - -static enum clock_control_status clock_control_esp32_get_status(const struct device *dev, - clock_control_subsys_t sys) -{ - ARG_UNUSED(dev); - uint32_t clk_en_reg = periph_ll_get_clk_en_reg((periph_module_t)sys); - uint32_t clk_en_mask = periph_ll_get_clk_en_mask((periph_module_t)sys); - - if (DPORT_GET_PERI_REG_MASK(clk_en_reg, clk_en_mask)) { - return CLOCK_CONTROL_STATUS_ON; - } - return CLOCK_CONTROL_STATUS_OFF; -} - -static int clock_control_esp32_get_rate(const struct device *dev, - clock_control_subsys_t sub_system, - uint32_t *rate) -{ - ARG_UNUSED(dev); - ARG_UNUSED(sub_system); - - uint32_t soc_clk_sel = REG_GET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_SOC_CLK_SEL); - uint32_t cpuperiod_sel; - uint32_t source_freq_mhz; - uint32_t clk_div; - - switch (soc_clk_sel) { - case DPORT_SOC_CLK_SEL_XTAL: - clk_div = REG_GET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_PRE_DIV_CNT) + 1; - source_freq_mhz = (uint32_t) rtc_clk_xtal_freq_get(); - *rate = MHZ(source_freq_mhz / clk_div); - return 0; - case DPORT_SOC_CLK_SEL_PLL: - cpuperiod_sel = DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL); - if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_80) { - *rate = MHZ(80); - } else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_160) { - *rate = MHZ(160); - } else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_240) { - *rate = MHZ(240); - } else { - *rate = 0; - return -ENOTSUP; - } - return 0; - case DPORT_SOC_CLK_SEL_8M: - *rate = MHZ(8); - return 0; - default: - *rate = 0; - return -ENOTSUP; - } -} - -static int clock_control_esp32_init(const struct device *dev) -{ - struct esp32_clock_config *cfg = DEV_CFG(dev); - uint32_t soc_clk_sel = cfg->clk_src_sel; - rtc_cpu_freq_config_t cpu_freq_conf; - - if (soc_clk_sel != DPORT_SOC_CLK_SEL_XTAL) { - rtc_clk_cpu_freq_to_xtal(ESP32_CLK_CPU_40M, 1); - } - - if (soc_clk_sel == DPORT_SOC_CLK_SEL_PLL && cfg->cpu_freq != s_cur_pll_freq) { - esp_clk_bbpll_disable(); - } - - switch (cfg->clk_src_sel) { - case ESP32_CLK_SRC_XTAL: - if (cfg->xtal_freq_sel != ESP32_CLK_XTAL_40M) { - return -ENOTSUP; - } - if (cfg->xtal_div > 1) { - rtc_clk_cpu_freq_to_xtal(ESP32_CLK_CPU_40M, cfg->xtal_div); - } - break; - case ESP32_CLK_SRC_PLL: - esp_clk_bbpll_enable(); - rtc_clk_cpu_freq_mhz_to_config(cfg->cpu_freq, &cpu_freq_conf); - rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), cpu_freq_conf.source_freq_mhz); - s_cur_pll_freq = cfg->cpu_freq; - esp_clk_cpu_freq_to_pll_mhz(cfg->cpu_freq); - break; - case ESP32_CLK_SRC_RTC8M: - esp_clk_cpu_freq_to_8m(); - break; - default: - return -EINVAL; - } - - return 0; -} - -static const struct clock_control_driver_api clock_control_esp32_api = { - .on = clock_control_esp32_on, - .off = clock_control_esp32_off, - .async_on = clock_control_esp32_async_on, - .get_rate = clock_control_esp32_get_rate, - .get_status = clock_control_esp32_get_status, -}; - -static const struct esp32_clock_config esp32_clock_config0 = { - .clk_src_sel = DT_PROP(DT_INST(0, cdns_tensilica_xtensa_lx7), clock_source), - .cpu_freq = DT_PROP(DT_INST(0, cdns_tensilica_xtensa_lx7), clock_frequency), - .xtal_freq_sel = DT_INST_PROP(0, xtal_freq), - .xtal_div = DT_INST_PROP(0, xtal_div) -}; - -DEVICE_DT_DEFINE(DT_NODELABEL(rtc), - &clock_control_esp32_init, - NULL, - NULL, - &esp32_clock_config0, - PRE_KERNEL_1, - CONFIG_CLOCK_CONTROL_INIT_PRIORITY, - &clock_control_esp32_api); - -BUILD_ASSERT((CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) == - MHZ(DT_PROP(DT_INST(0, cdns_tensilica_xtensa_lx7), clock_frequency)), - "SYS_CLOCK_HW_CYCLES_PER_SEC Value must be equal to CPU_Freq"); - -BUILD_ASSERT(DT_NODE_HAS_PROP(DT_INST(0, cdns_tensilica_xtensa_lx7), clock_source), - "CPU clock-source property must be set to ESP32_CLK_SRC_XTAL or ESP32_CLK_SRC_PLL"); diff --git a/dts/bindings/clock/espressif,esp32-rtc.yaml b/dts/bindings/clock/espressif,esp32-rtc.yaml index 9212072b948..38b694571ae 100644 --- a/dts/bindings/clock/espressif,esp32-rtc.yaml +++ b/dts/bindings/clock/espressif,esp32-rtc.yaml @@ -17,11 +17,11 @@ properties: xtal-freq: type: int required: true - description: Value of the extrernal XTAL connected to ESP32, Supported values 40M,26M + description: Value of the external XTAL connected to ESP32. xtal-div: type: int - required: true + required: false description: Divisor value for XTAL Clock, CPU_CLK = XTAL_FREQ / xtal-div "#clock-cells": diff --git a/dts/bindings/cpu/espressif,riscv.yml b/dts/bindings/cpu/espressif,riscv.yml new file mode 100644 index 00000000000..41dbb7481bc --- /dev/null +++ b/dts/bindings/cpu/espressif,riscv.yml @@ -0,0 +1,14 @@ +# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +description: Espressif RISC-V CPU + +compatible: "esp,riscv" + +include: cpu.yaml + +properties: + clock-source: + type: int + description: cpu clock source + required: false diff --git a/dts/riscv/espressif/esp32c3.dtsi b/dts/riscv/espressif/esp32c3.dtsi index a18d4672bea..c4e89e694fc 100644 --- a/dts/riscv/espressif/esp32c3.dtsi +++ b/dts/riscv/espressif/esp32c3.dtsi @@ -22,7 +22,7 @@ cpu0: cpu@0 { device_type = "cpu"; - compatible = "riscv"; + compatible = "esp,riscv"; reg = <0>; }; }; @@ -66,7 +66,6 @@ reg = <0x60008000 0x1000>; label = "RTC"; xtal-freq = ; - xtal-div = <0>; #clock-cells = <1>; status = "ok"; }; diff --git a/dts/xtensa/espressif/esp32.dtsi b/dts/xtensa/espressif/esp32.dtsi index 45f6851a53e..45b2061b16b 100644 --- a/dts/xtensa/espressif/esp32.dtsi +++ b/dts/xtensa/espressif/esp32.dtsi @@ -24,14 +24,12 @@ device_type = "cpu"; compatible = "cdns,tensilica-xtensa-lx6"; reg = <0>; - clock-source = ; }; cpu1: cpu@1 { device_type = "cpu"; compatible = "cdns,tensilica-xtensa-lx6"; reg = <1>; - clock-source = ; }; }; @@ -61,7 +59,6 @@ reg = <0x3ff48000 0x0D8>; label = "RTC"; xtal-freq = ; - xtal-div = <0>; #clock-cells = <1>; status = "ok"; }; diff --git a/dts/xtensa/espressif/esp32s2.dtsi b/dts/xtensa/espressif/esp32s2.dtsi index bfde3a4651e..7a389d048a4 100644 --- a/dts/xtensa/espressif/esp32s2.dtsi +++ b/dts/xtensa/espressif/esp32s2.dtsi @@ -26,7 +26,6 @@ device_type = "cpu"; compatible = "cdns,tensilica-xtensa-lx7"; reg = <0>; - clock-source = ; }; }; @@ -60,7 +59,6 @@ reg = <0x3f408000 0x0D8>; label = "RTC"; xtal-freq = ; - xtal-div = <0>; #clock-cells = <1>; status = "ok"; }; diff --git a/include/dt-bindings/clock/esp32c3_clock.h b/include/dt-bindings/clock/esp32c3_clock.h index d1245fb3410..a37841615c9 100644 --- a/include/dt-bindings/clock/esp32c3_clock.h +++ b/include/dt-bindings/clock/esp32c3_clock.h @@ -18,7 +18,8 @@ #define ESP32_CLK_CPU_160M 160U /* Supported XTAL Frequencies */ -#define ESP32_CLK_XTAL_40M 0U +#define ESP32_CLK_XTAL_32M 0U +#define ESP32_CLK_XTAL_40M 1U /* Modules IDs * These IDs are actually offsets in CLK and RST Control registers. diff --git a/soc/riscv/esp32c3/Kconfig.soc b/soc/riscv/esp32c3/Kconfig.soc index 9cc9ad56db7..eb97283c212 100644 --- a/soc/riscv/esp32c3/Kconfig.soc +++ b/soc/riscv/esp32c3/Kconfig.soc @@ -7,7 +7,7 @@ config SOC_ESP32C3 select RISCV_GP select DYNAMIC_INTERRUPTS select CLOCK_CONTROL - select CLOCK_CONTROL_ESP32C3 + select CLOCK_CONTROL_ESP32 config IDF_TARGET_ESP32C3 bool "ESP32C3 as target board" diff --git a/soc/xtensa/esp32s2/Kconfig.soc b/soc/xtensa/esp32s2/Kconfig.soc index 81675c0646f..db38c6edab8 100644 --- a/soc/xtensa/esp32s2/Kconfig.soc +++ b/soc/xtensa/esp32s2/Kconfig.soc @@ -7,7 +7,7 @@ config SOC_ESP32S2 select ATOMIC_OPERATIONS_C select DYNAMIC_INTERRUPTS select CLOCK_CONTROL - select CLOCK_CONTROL_ESP32S2 + select CLOCK_CONTROL_ESP32 if SOC_ESP32S2 diff --git a/west.yml b/west.yml index 364f319c0ed..a2afb363b26 100644 --- a/west.yml +++ b/west.yml @@ -67,7 +67,7 @@ manifest: groups: - hal - name: hal_espressif - revision: 2bb8d91a5e82418ff673090ca1feb18eb82c5e5c + revision: 5c2062876f86fbf3aa30f3e2539a88b56b8fd461 path: modules/hal/espressif west-commands: west/west-commands.yml groups: