clock: esp32: unify clock control for all espressif socs
This joins all clock control handling to same source by using hal clock functions. It also brings ESP32C3 clock support. Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This commit is contained in:
Sylvio Alves
Christopher Friedt
parent
2c08114c27
commit
27e44acda1
17 changed files with 116 additions and 479 deletions
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@ -7,124 +7,60 @@
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#define DT_DRV_COMPAT espressif_esp32_rtc
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#define CPU_RESET_REASON RTC_SW_CPU_RESET
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#ifdef CONFIG_SOC_ESP32
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#define DT_CPU_COMPAT cdns_tensilica_xtensa_lx6
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#undef CPU_RESET_REASON
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#define CPU_RESET_REASON SW_CPU_RESET
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#include <dt-bindings/clock/esp32_clock.h>
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#include "esp32/rom/rtc.h"
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#include "soc/dport_reg.h"
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#elif defined(CONFIG_SOC_ESP32S2)
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#define DT_CPU_COMPAT cdns_tensilica_xtensa_lx7
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#include <dt-bindings/clock/esp32s2_clock.h>
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#include "esp32s2/rom/rtc.h"
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#elif CONFIG_IDF_TARGET_ESP32C3
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#define DT_CPU_COMPAT esp_riscv
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#include <dt-bindings/clock/esp32c3_clock.h>
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#include "esp32c3/rom/rtc.h"
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#include <soc/soc_caps.h>
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#include <soc/soc.h>
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#include <soc/rtc.h>
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#endif
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#include <soc/rtc.h>
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#include <soc/apb_ctrl_reg.h>
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#include <soc/timer_group_reg.h>
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#include <regi2c_ctrl.h>
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#include <hal/clk_gate_ll.h>
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#include <soc.h>
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#include <drivers/clock_control.h>
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#include <driver/periph_ctrl.h>
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#include "clock_control_esp32.h"
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#include <hal/cpu_hal.h>
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struct esp32_clock_config {
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uint32_t clk_src_sel;
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int clk_src_sel;
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uint32_t cpu_freq;
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uint32_t xtal_freq_sel;
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uint32_t xtal_div;
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int xtal_div;
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};
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#define DEV_CFG(dev) ((struct esp32_clock_config *)(dev->config))
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static uint32_t const xtal_freq[] = {
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static uint8_t const xtal_freq[] = {
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#ifdef CONFIG_SOC_ESP32
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[ESP32_CLK_XTAL_24M] = 24,
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[ESP32_CLK_XTAL_26M] = 26,
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[ESP32_CLK_XTAL_40M] = 40,
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[ESP32_CLK_XTAL_AUTO] = 0
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#elif defined(CONFIG_SOC_ESP32S2)
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[ESP32_CLK_XTAL_40M] = 40,
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#elif defined(CONFIG_SOC_ESP32C3)
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[ESP32_CLK_XTAL_32M] = 32,
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[ESP32_CLK_XTAL_40M] = 40,
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#endif
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};
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/* function prototypes */
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extern void rtc_clk_cpu_freq_to_xtal(int freq, int div);
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extern void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq);
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static inline uint32_t clk_val_to_reg_val(uint32_t val)
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{
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return (val & UINT16_MAX) | ((val & UINT16_MAX) << 16);
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}
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static void esp_clk_cpu_freq_to_8m(void)
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{
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ets_update_cpu_frequency(8);
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REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL);
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REG_SET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT, 0);
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REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_8M);
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rtc_clk_apb_freq_update(ESP32_FAST_CLK_FREQ_8M);
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}
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static void esp_clk_bbpll_disable(void)
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{
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SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG,
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RTC_CNTL_BB_I2C_FORCE_PD | RTC_CNTL_BBPLL_FORCE_PD |
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RTC_CNTL_BBPLL_I2C_FORCE_PD);
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/* is APLL under force power down? */
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uint32_t apll_fpd = REG_GET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD);
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if (apll_fpd) {
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/* then also power down the internal I2C bus */
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SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD);
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}
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}
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static void esp_clk_bbpll_enable(void)
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{
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CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG,
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RTC_CNTL_BIAS_I2C_FORCE_PD |
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RTC_CNTL_BB_I2C_FORCE_PD |
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RTC_CNTL_BBPLL_FORCE_PD |
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RTC_CNTL_BBPLL_I2C_FORCE_PD);
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/* reset BBPLL configuration */
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REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_IR_CAL_DELAY, BBPLL_IR_CAL_DELAY_VAL);
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REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_IR_CAL_EXT_CAP, BBPLL_IR_CAL_EXT_CAP_VAL);
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REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_ENB_FCAL, BBPLL_OC_ENB_FCAL_VAL);
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REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_ENB_VCON, BBPLL_OC_ENB_VCON_VAL);
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REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_BBADC_CAL_7_0, BBPLL_BBADC_CAL_7_0_VAL);
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}
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static void esp_clk_wait_for_slow_cycle(void)
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{
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REG_CLR_BIT(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING | TIMG_RTC_CALI_START);
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REG_CLR_BIT(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY);
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REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, RTC_CAL_RTC_MUX);
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/*
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* Request to run calibration for 0 slow clock cycles.
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* RDY bit will be set on the nearest slow clock cycle.
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*/
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REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, 0);
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REG_SET_BIT(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
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esp_rom_ets_delay_us(1); /* RDY needs some time to go low */
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while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)) {
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esp_rom_ets_delay_us(1);
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}
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}
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static int esp_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
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{
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int dbias = DIG_DBIAS_80M_160M;
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int per_conf = DPORT_CPUPERIOD_SEL_80;
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if (cpu_freq_mhz == 80) {
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/* nothing to do */
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} else if (cpu_freq_mhz == 160) {
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per_conf = DPORT_CPUPERIOD_SEL_160;
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} else if (cpu_freq_mhz == 240) {
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dbias = DIG_DBIAS_240M;
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per_conf = DPORT_CPUPERIOD_SEL_240;
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} else {
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return -EINVAL;
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}
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DPORT_REG_WRITE(DPORT_CPU_PER_CONF_REG, per_conf);
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REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, dbias);
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REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_PLL);
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rtc_clk_apb_freq_update(MHZ(80));
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ets_update_cpu_frequency(cpu_freq_mhz);
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esp_clk_wait_for_slow_cycle();
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return 0;
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}
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static int clock_control_esp32_on(const struct device *dev,
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clock_control_subsys_t sys)
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{
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@ -172,55 +108,62 @@ static int clock_control_esp32_get_rate(const struct device *dev,
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{
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ARG_UNUSED(sub_system);
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uint32_t xtal_freq_sel = DEV_CFG(dev)->xtal_freq_sel;
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uint32_t soc_clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL);
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rtc_cpu_freq_config_t config;
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switch (soc_clk_sel) {
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case RTC_CNTL_SOC_CLK_SEL_XTL:
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*rate = xtal_freq[xtal_freq_sel];
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return 0;
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case RTC_CNTL_SOC_CLK_SEL_PLL:
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*rate = MHZ(80);
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return 0;
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default:
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*rate = 0;
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return -ENOTSUP;
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}
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rtc_clk_cpu_freq_get_config(&config);
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*rate = config.freq_mhz;
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return 0;
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}
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static int clock_control_esp32_init(const struct device *dev)
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{
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struct esp32_clock_config *cfg = DEV_CFG(dev);
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uint32_t soc_clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL);
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rtc_cpu_freq_config_t old_config;
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rtc_cpu_freq_config_t new_config;
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bool res;
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if (soc_clk_sel != RTC_CNTL_SOC_CLK_SEL_XTL) {
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rtc_clk_cpu_freq_to_xtal(xtal_freq[cfg->xtal_freq_sel], 1);
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esp_clk_wait_for_slow_cycle();
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/* reset default config to use dts config */
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if (rtc_clk_apb_freq_get() < APB_CLK_FREQ || rtc_get_reset_reason(0) != CPU_RESET_REASON) {
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rtc_clk_config_t clk_cfg = RTC_CLK_CONFIG_DEFAULT();
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clk_cfg.xtal_freq = xtal_freq[cfg->xtal_freq_sel];
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clk_cfg.cpu_freq_mhz = cfg->cpu_freq;
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clk_cfg.slow_freq = rtc_clk_slow_freq_get();
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clk_cfg.fast_freq = rtc_clk_fast_freq_get();
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rtc_clk_init(clk_cfg);
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}
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if (soc_clk_sel == RTC_CNTL_SOC_CLK_SEL_PLL) {
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esp_clk_bbpll_disable();
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rtc_clk_fast_freq_set(RTC_FAST_FREQ_8M);
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rtc_clk_cpu_freq_get_config(&old_config);
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const uint32_t old_freq_mhz = old_config.freq_mhz;
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const uint32_t new_freq_mhz = cfg->cpu_freq;
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res = rtc_clk_cpu_freq_mhz_to_config(cfg->cpu_freq, &new_config);
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if (!res) {
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return -ENOTSUP;
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}
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switch (cfg->clk_src_sel) {
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case ESP32_CLK_SRC_XTAL:
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if (cfg->xtal_div > 1) {
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rtc_clk_cpu_freq_to_xtal(xtal_freq[cfg->xtal_freq_sel], cfg->xtal_div);
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}
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break;
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case ESP32_CLK_SRC_PLL:
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esp_clk_bbpll_enable();
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esp_clk_wait_for_slow_cycle();
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rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), cfg->cpu_freq);
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esp_clk_cpu_freq_to_pll_mhz(cfg->cpu_freq);
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break;
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case ESP32_CLK_SRC_RTC8M:
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esp_clk_cpu_freq_to_8m();
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break;
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default:
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return -EINVAL;
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/* wait uart output to be cleared */
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esp_rom_uart_tx_wait_idle(0);
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if (cfg->xtal_div >= 0) {
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new_config.div = cfg->xtal_div;
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}
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if (cfg->clk_src_sel >= 0) {
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new_config.source = cfg->clk_src_sel;
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}
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/* set new configuration */
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rtc_clk_cpu_freq_set_config(&new_config);
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/* Re-calculate the ccount to make time calculation correct */
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cpu_hal_set_cycle_count((uint64_t)cpu_hal_get_cycle_count() * new_freq_mhz / old_freq_mhz);
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/* Enable RNG clock. */
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periph_module_enable(PERIPH_RNG_MODULE);
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@ -235,11 +178,19 @@ static const struct clock_control_driver_api clock_control_esp32_api = {
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.get_status = clock_control_esp32_get_status,
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};
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#define ESP32_CLOCK_SOURCE \
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COND_CODE_1(DT_NODE_HAS_PROP(DT_INST(0, DT_CPU_COMPAT), clock_source), \
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(DT_PROP(DT_INST(0, DT_CPU_COMPAT), clock_source)), (-1))
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#define ESP32_CLOCK_XTAL_DIV \
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COND_CODE_1(DT_NODE_HAS_PROP(0, xtal_div), \
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(DT_INST_PROP(0, xtal_div)), (-1))
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static const struct esp32_clock_config esp32_clock_config0 = {
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.clk_src_sel = DT_PROP(DT_INST(0, cdns_tensilica_xtensa_lx6), clock_source),
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.cpu_freq = DT_PROP(DT_INST(0, cdns_tensilica_xtensa_lx6), clock_frequency),
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.clk_src_sel = ESP32_CLOCK_SOURCE,
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.cpu_freq = DT_PROP(DT_INST(0, DT_CPU_COMPAT), clock_frequency),
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.xtal_freq_sel = DT_INST_PROP(0, xtal_freq),
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.xtal_div = DT_INST_PROP(0, xtal_div)
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.xtal_div = ESP32_CLOCK_XTAL_DIV
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};
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DEVICE_DT_DEFINE(DT_NODELABEL(rtc),
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@ -251,9 +202,8 @@ DEVICE_DT_DEFINE(DT_NODELABEL(rtc),
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CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
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&clock_control_esp32_api);
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#ifndef CONFIG_SOC_ESP32C3
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BUILD_ASSERT((CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) ==
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MHZ(DT_PROP(DT_INST(0, cdns_tensilica_xtensa_lx6), clock_frequency)),
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MHZ(DT_PROP(DT_INST(0, DT_CPU_COMPAT), clock_frequency)),
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"SYS_CLOCK_HW_CYCLES_PER_SEC Value must be equal to CPU_Freq");
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BUILD_ASSERT(DT_NODE_HAS_PROP(DT_INST(0, cdns_tensilica_xtensa_lx6), clock_source),
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"CPU clock-source property must be set to ESP32_CLK_SRC_XTAL or ESP32_CLK_SRC_PLL");
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#endif
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