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drivers: ethernet: xlnx_gem: Zynq-7000 support for the Xilinx GEM driver

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Add support for the Xilinx Zynq-7000 SoC family to this driver. This
includes some SoC-specific register accesses when setting an updated
TX clock divider, also, the device tree binding now supports higher
MDC clock divisor values when the current target SoC is a Zynq rather
than a ZynqMP.

With regards to the use of this driver in a QEMU simulation of the
Zynq-7000, the Kconfig file is modified so that the driver is not
enabled unless QEMU networking is set to Ethernet mode.

Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
This commit is contained in:
Immo Birnbaum 2021-07-15 13:10:33 +02:00 • committed by Carles Cufí
commit 266875ead0
4 changed files with 84 additions and 12 deletions
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14
include/dt-bindings/ethernet/xlnx_gem.h
View file

@ -10,14 +10,20 @@
#define XLNX_GEM_PHY_AUTO_DETECT 0
/* MDC divider values */
#define XLNX_GEM_MDC_DIVIDER_8 0 /* LPD_LSBUS_CLK < 20 MHz */
#define XLNX_GEM_MDC_DIVIDER_16 1 /* LPD_LSBUS_CLK 20 - 40 MHz */
#define XLNX_GEM_MDC_DIVIDER_32 2 /* LPD_LSBUS_CLK 40 - 80 MHz */
/* The following values are supported by both the Zynq-7000 and the ZynqMP */
#define XLNX_GEM_MDC_DIVIDER_8 0 /* cpu_1x or LPD_LSBUS_CLK < 20 MHz */
#define XLNX_GEM_MDC_DIVIDER_16 1 /* cpu_1x or LPD_LSBUS_CLK 20 - 40 MHz */
#define XLNX_GEM_MDC_DIVIDER_32 2 /* cpu_1x or LPD_LSBUS_CLK 40 - 80 MHz */
/*
* According to the ZynqMP's gem.network_config register documentation,
* divider /32 is to be used for a 100 MHz LPD LSBUS clock.
*/
#define XLNX_GEM_MDC_DIVIDER_48 3 /* LPD_LSBUS_CLK 80 - 120 MHz */
/* The following values are supported by the Zynq-7000 only */
#define XLNX_GEM_MDC_DIVIDER_48 3 /* cpu_1x 80 - 120 MHz */
#define XLNX_GEM_MDC_DIVIDER_64 4 /* cpu_1x 120 - 160 MHz */
#define XLNX_GEM_MDC_DIVIDER_96 5 /* cpu_1x 160 - 240 MHz */
#define XLNX_GEM_MDC_DIVIDER_128 6 /* cpu_1x 240 - 320 MHz */
#define XLNX_GEM_MDC_DIVIDER_224 7 /* cpu_1x 320 - 540 MHz */
/* Link speed values */
#define XLNX_GEM_LINK_SPEED_10MBIT 1