npcx: move scfg driver from pinctrl to soc/arm/nuvoton_npcx/common

In NPCX chips, System Configuration module can configure not only
pinctrl but also misc. functionality such as glue and flash write
protection. This change moves the scfg driver from the pinctrl folder
to soc/arm/nuvoton_npcx/common and renames it to avoid confusion.

Signed-off-by: Jun Lin <CHLin56@nuvoton.com>

boards/arm/npcx7m6fb_evb/npcx7m6fb_evb_defconfig

@@ -23,9 +23,6 @@ CONFIG_CLOCK_NPCX_APB1_PRESCALER=6
 CONFIG_CLOCK_NPCX_APB2_PRESCALER=6
 CONFIG_CLOCK_NPCX_APB3_PRESCALER=6
 
-# Pinmux Driver
-CONFIG_PINMUX=y
-
 # UART Driver
 CONFIG_SERIAL=y
 CONFIG_UART_INTERRUPT_DRIVEN=y

drivers/pinmux/CMakeLists.txt

@@ -9,7 +9,6 @@ zephyr_sources_ifdef(CONFIG_PINMUX_ITE_IT8XXX2     pinmux_ite_it8xxx2.c)
 zephyr_sources_ifdef(CONFIG_PINMUX_LPC11U6X        pinmux_lpc11u6x.c)
 zephyr_sources_ifdef(CONFIG_PINMUX_MCUX            pinmux_mcux.c)
 zephyr_sources_ifdef(CONFIG_PINMUX_MCUX_LPC        pinmux_mcux_lpc.c)
-zephyr_sources_ifdef(CONFIG_PINMUX_NPCX            pinmux_npcx.c)
 zephyr_sources_ifdef(CONFIG_PINMUX_RV32M1          pinmux_rv32m1.c)
 zephyr_sources_ifdef(CONFIG_PINMUX_SAM0            pinmux_sam0.c)
 zephyr_sources_ifdef(CONFIG_PINMUX_SIFIVE          pinmux_sifive.c)

drivers/pinmux/Kconfig

@@ -52,6 +52,4 @@ source "drivers/pinmux/Kconfig.stm32"
 
 source "drivers/pinmux/Kconfig.xec"
 
-source "drivers/pinmux/Kconfig.npcx"
-
 endif # PINMUX

drivers/pinmux/Kconfig.npcx

@@ -1,12 +0,0 @@
-# NPCX PINMUX driver configuration options
-
-# Copyright (c) 2020 Nuvoton Technology Corporation.
-# SPDX-License-Identifier: Apache-2.0
-
-config PINMUX_NPCX
-	bool "Nuvoton NPCX embedded controller (EC) pinmux driver"
-	depends on SOC_FAMILY_NPCX
-	help
-	  This option enables the pin-mux driver for NPCX family
-	  of processors.
-	  Say y if you wish to use pin-mux module on NPCX MCU.

dts/arm/nuvoton/npcx7.dtsi

@@ -121,8 +121,8 @@
 			label = "PMC_CDCG";
 		};
 
-		scfg: pin-controller@400c3000 {
+		scfg: scfg@400c3000 {
-			compatible = "nuvoton,npcx-pinctrl";
+			compatible = "nuvoton,npcx-scfg";
 			/* First reg region is System Configuration Device */
 			/* Second reg region is System Glue Device */
 			reg = <0x400c3000 0x70

dts/bindings/pinctrl/nuvoton,npcx-scfg.yaml

@@ -1,9 +1,9 @@
 # Copyright (c) 2020 Nuvoton Technology Corporation.
 # SPDX-License-Identifier: Apache-2.0
 
-description: Nuvoton, NPCX Pin-Controller (Pinmux, 1.8V support and so on) node
+description: Nuvoton, NPCX System Configuration (Pinmux, 1.8V support and so on) node
 
-compatible: "nuvoton,npcx-pinctrl"
+compatible: "nuvoton,npcx-scfg"
 
 include: [base.yaml]
 

soc/arm/nuvoton_npcx/common/CMakeLists.txt

@@ -1,3 +1,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 zephyr_include_directories(.)
+
+zephyr_sources(
+  scfg.c
+)

soc/arm/nuvoton_npcx/common/scfg.c

@@ -4,9 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#define DT_DRV_COMPAT nuvoton_npcx_pinctrl
+#include <device.h>
-
-#include <drivers/pinmux.h>
 #include <kernel.h>
 #include <soc.h>
 
@@ -14,7 +12,7 @@
 LOG_MODULE_REGISTER(pimux_npcx, LOG_LEVEL_ERR);
 
 /* Driver config */
-struct npcx_pinctrl_config {
+struct npcx_scfg_config {
 	/* scfg device base address */
 	uintptr_t base_scfg;
 	uintptr_t base_glue;
@@ -36,20 +34,20 @@ static const struct npcx_alt def_alts[] =
 
 static const struct npcx_lvol def_lvols[] = NPCX_DT_IO_LVOL_ITEMS_DEF_LIST;
 
-static const struct npcx_pinctrl_config npcx_pinctrl_cfg = {
+static const struct npcx_scfg_config npcx_scfg_cfg = {
-	.base_scfg = DT_INST_REG_ADDR_BY_NAME(0, scfg),
+	.base_scfg = DT_REG_ADDR_BY_NAME(DT_NODELABEL(scfg), scfg),
-	.base_glue = DT_INST_REG_ADDR_BY_NAME(0, glue),
+	.base_glue = DT_REG_ADDR_BY_NAME(DT_NODELABEL(scfg), glue),
 };
 
 /* Driver convenience defines */
-#define HAL_SFCG_INST() (struct scfg_reg *)(npcx_pinctrl_cfg.base_scfg)
+#define HAL_SFCG_INST() (struct scfg_reg *)(npcx_scfg_cfg.base_scfg)
 
-#define HAL_GLUE_INST() (struct glue_reg *)(npcx_pinctrl_cfg.base_glue)
+#define HAL_GLUE_INST() (struct glue_reg *)(npcx_scfg_cfg.base_glue)
 
 /* Pin-control local functions */
 static void npcx_pinctrl_alt_sel(const struct npcx_alt *alt, int alt_func)
 {
-	const uint32_t scfg_base = npcx_pinctrl_cfg.base_scfg;
+	const uint32_t scfg_base = npcx_scfg_cfg.base_scfg;
 	uint8_t alt_mask = BIT(alt->bit);
 
 	/*
@@ -79,7 +77,7 @@ void npcx_pinctrl_mux_configure(const struct npcx_alt *alts_list,
 
 void npcx_lvol_pads_configure(void)
 {
-	const uint32_t scfg_base = npcx_pinctrl_cfg.base_scfg;
+	const uint32_t scfg_base = npcx_scfg_cfg.base_scfg;
 
 	for (int i = 0; i < ARRAY_SIZE(def_lvols); i++) {
 		NPCX_LV_GPIO_CTL(scfg_base, def_lvols[i].ctrl)
@@ -101,7 +99,7 @@ void npcx_pinctrl_i2c_port_sel(int controller, int port)
 }
 
 /* Pin-control driver registration */
-static int npcx_pinctrl_init(const struct device *dev)
+static int npcx_scfg_init(const struct device *dev)
 {
 	struct scfg_reg *inst_scfg = HAL_SFCG_INST();
 
@@ -122,9 +120,4 @@ static int npcx_pinctrl_init(const struct device *dev)
 	return 0;
 }
 
-DEVICE_DT_DEFINE(DT_NODELABEL(scfg),
+SYS_INIT(npcx_scfg_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
-		    &npcx_pinctrl_init,
-		    device_pm_control_nop,
-		    NULL, &npcx_pinctrl_cfg,
-		    PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
-		    NULL);

soc/arm/nuvoton_npcx/npcx7/Kconfig.defconfig.series

@@ -22,12 +22,6 @@ config CLOCK_CONTROL_NPCX
 	help
 	  Enable support for NPCX clock controller driver.
 
-config PINMUX_NPCX
-	default y
-	depends on PINMUX
-	help
-	  Enable support for NPCX pinmux controller driver.
-
 config UART_NPCX
 	default y
 	depends on SERIAL