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Rename option CPU_CORTEXM to CPU_CORTEX_M

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Makes name more consistent with other CPU_CORTEX_M* options.

Change-Id: I65968cb300207ba0de6231d9a67f2720be77b6ba
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
This commit is contained in:
Peter Mitsis 2015-06-17 11:16:57 -04:00 • committed by Anas Nashif
commit 25fd37d9d5
12 changed files with 24 additions and 24 deletions
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6
arch/arm/bsp/CortexM/Kconfig
View file

@ -39,7 +39,7 @@ config CPU_CORTEX
help
This option signifies the use of a CPU of the Cortex family.
config CPU_CORTEXM
config CPU_CORTEX_M
bool "ARM Cortex-M"
default n
select CPU_CORTEX
@ -50,7 +50,7 @@ config CPU_CORTEXM
config CPU_CORTEX_M3_M4
bool "ARM Cortex-M3 or ARM Cortex-M4"
default n
select CPU_CORTEXM
select CPU_CORTEX_M
help
This option signifies the use of either a Cortex-M3 or Cortex-M4 CPU.
@ -73,7 +73,7 @@ config CPU_CORTEX_M4
endmenu
menu "ARM Cortex-M family options"
depends on CPU_CORTEXM
depends on CPU_CORTEX_M
config LDREX_STREX_AVAILABLE
bool

2
arch/arm/configs/micro_fsl_frdm_k64f_defconfig
View file

@ -83,7 +83,7 @@ CONFIG_BSP_FSL_FRDM_K64F=y
# ARM Cortex CPU options
#
CONFIG_CPU_CORTEX=y
CONFIG_CPU_CORTEXM=y
CONFIG_CPU_CORTEX_M=y
CONFIG_CPU_CORTEX_M3_M4=y
CONFIG_CPU_CORTEX_M3=y
CONFIG_CPU_CORTEX_M4=y

2
arch/arm/configs/micro_ti_lm3s6965_defconfig
View file

@ -83,7 +83,7 @@ CONFIG_BSP_TI_LM3S6965=y
# ARM Cortex CPU options
#
CONFIG_CPU_CORTEX=y
CONFIG_CPU_CORTEXM=y
CONFIG_CPU_CORTEX_M=y
CONFIG_CPU_CORTEX_M3_M4=y
CONFIG_CPU_CORTEX_M3=y
# CONFIG_CPU_CORTEX_M4 is not set

2
arch/arm/configs/nano_fsl_frdm_k64f_defconfig
View file

@ -62,7 +62,7 @@ CONFIG_BSP_FSL_FRDM_K64F=y
# ARM Cortex CPU options
#
CONFIG_CPU_CORTEX=y
CONFIG_CPU_CORTEXM=y
CONFIG_CPU_CORTEX_M=y
CONFIG_CPU_CORTEX_M3_M4=y
CONFIG_CPU_CORTEX_M3=y
CONFIG_CPU_CORTEX_M4=y

2
arch/arm/configs/nano_ti_lm3s6965_defconfig
View file

@ -62,7 +62,7 @@ CONFIG_BSP_TI_LM3S6965=y
# ARM Cortex CPU options
#
CONFIG_CPU_CORTEX=y
CONFIG_CPU_CORTEXM=y
CONFIG_CPU_CORTEX_M=y
CONFIG_CPU_CORTEX_M3_M4=y
CONFIG_CPU_CORTEX_M3=y
# CONFIG_CPU_CORTEX_M4 is not set

2
arch/arm/defconfig
View file

@ -83,7 +83,7 @@ CONFIG_BSP_FSL_FRDM_K64F=y
# ARM Cortex CPU options
#
CONFIG_CPU_CORTEX=y
CONFIG_CPU_CORTEXM=y
CONFIG_CPU_CORTEX_M=y
CONFIG_CPU_CORTEX_M3_M4=y
CONFIG_CPU_CORTEX_M3=y
CONFIG_CPU_CORTEX_M4=y

2
arch/arm/include/asm_inline.h
View file

@ -33,7 +33,7 @@
#ifndef _ASM_INLINE_H
#define _ASM_INLINE_H
#if !defined(CONFIG_ARM) || !defined(CONFIG_CPU_CORTEXM)
#if !defined(CONFIG_ARM) || !defined(CONFIG_CPU_CORTEX_M)
#error arch/arm/include/asm_inline.h is for ARM CortexM only
#endif

2
arch/arm/include/nanok.h
View file

@ -120,7 +120,7 @@ typedef struct preempt tPreempt;
#define STACK_ROUND_UP(x) ROUND_UP(x, STACK_ALIGN_SIZE)
#define STACK_ROUND_DOWN(x) ROUND_DOWN(x, STACK_ALIGN_SIZE)
#ifdef CONFIG_CPU_CORTEXM
#ifdef CONFIG_CPU_CORTEX_M
#include <CortexM/stack.h>
#include <CortexM/exc.h>
#endif

12
doc/doxygen/irq_test_common_commented.h
View file

@ -43,9 +43,9 @@ Interrupt stuff, abstracted across CPU architectures.
#if defined(CONFIG_X86_32)
#define IRQ_PRIORITY 3
#elif defined(CONFIG_ARM)
#if defined(CONFIG_CPU_CORTEXM)
#if defined(CONFIG_CPU_CORTEX_M)
#define IRQ_PRIORITY _EXC_PRIO(3)
#endif /* CONFIG_CPU_CORTEXM */
#endif /* CONFIG_CPU_CORTEX_M */
#endif
/*
@ -97,7 +97,7 @@ static char sw_isr_trigger_1[] =
#endif /* NUM_SW_IRQS >= 2 */
#elif defined(CONFIG_ARM)
#if defined(CONFIG_CPU_CORTEXM)
#if defined(CONFIG_CPU_CORTEX_M)
#include <nanokernel.h>
static inline void sw_isr_trigger_0(void)
{
@ -110,7 +110,7 @@ static inline void sw_isr_trigger_1(void)
_NvicSwInterruptTrigger(1);
}
#endif /* NUM_SW_IRQS >= 2 */
#endif /* CONFIG_CPU_CORTEXM */
#endif /* CONFIG_CPU_CORTEX_M */
#endif
/*! Defines the ISR initialization information. */
@ -161,7 +161,7 @@ static int initIRQ
}
#endif /* NUM_SW_IRQS >= 2 */
#elif defined(CONFIG_ARM)
#if defined(CONFIG_CPU_CORTEXM)
#if defined(CONFIG_CPU_CORTEX_M)
if (i->isr[0])
{
(void) irq_connect (0, IRQ_PRIORITY, i->isr[0], i->arg[0]);
@ -172,7 +172,7 @@ static int initIRQ
(void) irq_connect (1, IRQ_PRIORITY, i->isr[1], i->arg[1]);
irq_enable (1);
}
#endif /* CONFIG_CPU_CORTEXM */
#endif /* CONFIG_CPU_CORTEX_M */
#endif /* CONFIG_X86_32 */
return 0;

2
include/arch/arm/arch.h
View file

@ -49,7 +49,7 @@ extern "C" {
#define OCTET_TO_SIZEOFUNIT(X) (X)
#define SIZEOFUNIT_TO_OCTET(X) (X)
#ifdef CONFIG_CPU_CORTEXM
#ifdef CONFIG_CPU_CORTEX_M
#include <arch/arm/CortexM/exc.h>
#include <arch/arm/CortexM/irq.h>
#include <arch/arm/CortexM/ffs.h>

2
include/linker-tool-gcc.h
View file

@ -39,7 +39,7 @@ use with the GCC linker.
#ifndef __LINKER_TOOL_GCC_H
#define __LINKER_TOOL_GCC_H
#if defined(CONFIG_CPU_CORTEXM)
#if defined(CONFIG_CPU_CORTEX_M)
OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
#elif defined(CONFIG_ARC)
OUTPUT_FORMAT("elf32-littlearc", "elf32-bigarc", "elf32-littlearc")

12
samples/include/irq_test_common.h
View file

@ -42,9 +42,9 @@ Interrupt stuff, abstracted across CPU architectures.
#if defined(CONFIG_X86_32)
#define IRQ_PRIORITY 3
#elif defined(CONFIG_ARM)
#if defined(CONFIG_CPU_CORTEXM)
#if defined(CONFIG_CPU_CORTEX_M)
#define IRQ_PRIORITY _EXC_PRIO(3)
#endif /* CONFIG_CPU_CORTEXM */
#endif /* CONFIG_CPU_CORTEX_M */
#endif
/*
@ -91,7 +91,7 @@ static char sw_isr_trigger_1[] = {
#endif /* NUM_SW_IRQS >= 2 */
#elif defined(CONFIG_ARM)
#if defined(CONFIG_CPU_CORTEXM)
#if defined(CONFIG_CPU_CORTEX_M)
#include <nanokernel.h>
static inline void sw_isr_trigger_0(void)
{
@ -104,7 +104,7 @@ static inline void sw_isr_trigger_1(void)
_NvicSwInterruptTrigger(1);
}
#endif /* NUM_SW_IRQS >= 2 */
#endif /* CONFIG_CPU_CORTEXM */
#endif /* CONFIG_CPU_CORTEX_M */
#endif
struct isrInitInfo {
@ -143,7 +143,7 @@ static int initIRQ(struct isrInitInfo *i)
}
#endif /* NUM_SW_IRQS >= 2 */
#elif defined(CONFIG_ARM)
#if defined(CONFIG_CPU_CORTEXM)
#if defined(CONFIG_CPU_CORTEX_M)
if (i->isr[0]) {
(void) irq_connect(0, IRQ_PRIORITY, i->isr[0], i->arg[0]);
irq_enable(0);
@ -152,7 +152,7 @@ static int initIRQ(struct isrInitInfo *i)
(void) irq_connect(1, IRQ_PRIORITY, i->isr[1], i->arg[1]);
irq_enable(1);
}
#endif /* CONFIG_CPU_CORTEXM */
#endif /* CONFIG_CPU_CORTEX_M */
#endif /* CONFIG_X86_32 */
return 0;