From 25fd37d9d54e34d59bd8be0c53d8fbae382c1484 Mon Sep 17 00:00:00 2001 From: Peter Mitsis Date: Wed, 17 Jun 2015 11:16:57 -0400 Subject: [PATCH] Rename option CPU_CORTEXM to CPU_CORTEX_M Makes name more consistent with other CPU_CORTEX_M* options. Change-Id: I65968cb300207ba0de6231d9a67f2720be77b6ba Signed-off-by: Peter Mitsis --- arch/arm/bsp/CortexM/Kconfig | 6 +++--- arch/arm/configs/micro_fsl_frdm_k64f_defconfig | 2 +- arch/arm/configs/micro_ti_lm3s6965_defconfig | 2 +- arch/arm/configs/nano_fsl_frdm_k64f_defconfig | 2 +- arch/arm/configs/nano_ti_lm3s6965_defconfig | 2 +- arch/arm/defconfig | 2 +- arch/arm/include/asm_inline.h | 2 +- arch/arm/include/nanok.h | 2 +- doc/doxygen/irq_test_common_commented.h | 12 ++++++------ include/arch/arm/arch.h | 2 +- include/linker-tool-gcc.h | 2 +- samples/include/irq_test_common.h | 12 ++++++------ 12 files changed, 24 insertions(+), 24 deletions(-) diff --git a/arch/arm/bsp/CortexM/Kconfig b/arch/arm/bsp/CortexM/Kconfig index ac56d124997..759fe528e99 100644 --- a/arch/arm/bsp/CortexM/Kconfig +++ b/arch/arm/bsp/CortexM/Kconfig @@ -39,7 +39,7 @@ config CPU_CORTEX help This option signifies the use of a CPU of the Cortex family. -config CPU_CORTEXM +config CPU_CORTEX_M bool "ARM Cortex-M" default n select CPU_CORTEX @@ -50,7 +50,7 @@ config CPU_CORTEXM config CPU_CORTEX_M3_M4 bool "ARM Cortex-M3 or ARM Cortex-M4" default n - select CPU_CORTEXM + select CPU_CORTEX_M help This option signifies the use of either a Cortex-M3 or Cortex-M4 CPU. @@ -73,7 +73,7 @@ config CPU_CORTEX_M4 endmenu menu "ARM Cortex-M family options" - depends on CPU_CORTEXM + depends on CPU_CORTEX_M config LDREX_STREX_AVAILABLE bool diff --git a/arch/arm/configs/micro_fsl_frdm_k64f_defconfig b/arch/arm/configs/micro_fsl_frdm_k64f_defconfig index e2a9ee33a73..0432912137b 100644 --- a/arch/arm/configs/micro_fsl_frdm_k64f_defconfig +++ b/arch/arm/configs/micro_fsl_frdm_k64f_defconfig @@ -83,7 +83,7 @@ CONFIG_BSP_FSL_FRDM_K64F=y # ARM Cortex CPU options # CONFIG_CPU_CORTEX=y -CONFIG_CPU_CORTEXM=y +CONFIG_CPU_CORTEX_M=y CONFIG_CPU_CORTEX_M3_M4=y CONFIG_CPU_CORTEX_M3=y CONFIG_CPU_CORTEX_M4=y diff --git a/arch/arm/configs/micro_ti_lm3s6965_defconfig b/arch/arm/configs/micro_ti_lm3s6965_defconfig index e5e06b767f1..2af945f913d 100644 --- a/arch/arm/configs/micro_ti_lm3s6965_defconfig +++ b/arch/arm/configs/micro_ti_lm3s6965_defconfig @@ -83,7 +83,7 @@ CONFIG_BSP_TI_LM3S6965=y # ARM Cortex CPU options # CONFIG_CPU_CORTEX=y -CONFIG_CPU_CORTEXM=y +CONFIG_CPU_CORTEX_M=y CONFIG_CPU_CORTEX_M3_M4=y CONFIG_CPU_CORTEX_M3=y # CONFIG_CPU_CORTEX_M4 is not set diff --git a/arch/arm/configs/nano_fsl_frdm_k64f_defconfig b/arch/arm/configs/nano_fsl_frdm_k64f_defconfig index 070cbc478af..f1b84101a33 100644 --- a/arch/arm/configs/nano_fsl_frdm_k64f_defconfig +++ b/arch/arm/configs/nano_fsl_frdm_k64f_defconfig @@ -62,7 +62,7 @@ CONFIG_BSP_FSL_FRDM_K64F=y # ARM Cortex CPU options # CONFIG_CPU_CORTEX=y -CONFIG_CPU_CORTEXM=y +CONFIG_CPU_CORTEX_M=y CONFIG_CPU_CORTEX_M3_M4=y CONFIG_CPU_CORTEX_M3=y CONFIG_CPU_CORTEX_M4=y diff --git a/arch/arm/configs/nano_ti_lm3s6965_defconfig b/arch/arm/configs/nano_ti_lm3s6965_defconfig index a5da9aafb01..92209c9aed3 100644 --- a/arch/arm/configs/nano_ti_lm3s6965_defconfig +++ b/arch/arm/configs/nano_ti_lm3s6965_defconfig @@ -62,7 +62,7 @@ CONFIG_BSP_TI_LM3S6965=y # ARM Cortex CPU options # CONFIG_CPU_CORTEX=y -CONFIG_CPU_CORTEXM=y +CONFIG_CPU_CORTEX_M=y CONFIG_CPU_CORTEX_M3_M4=y CONFIG_CPU_CORTEX_M3=y # CONFIG_CPU_CORTEX_M4 is not set diff --git a/arch/arm/defconfig b/arch/arm/defconfig index e2a9ee33a73..0432912137b 100644 --- a/arch/arm/defconfig +++ b/arch/arm/defconfig @@ -83,7 +83,7 @@ CONFIG_BSP_FSL_FRDM_K64F=y # ARM Cortex CPU options # CONFIG_CPU_CORTEX=y -CONFIG_CPU_CORTEXM=y +CONFIG_CPU_CORTEX_M=y CONFIG_CPU_CORTEX_M3_M4=y CONFIG_CPU_CORTEX_M3=y CONFIG_CPU_CORTEX_M4=y diff --git a/arch/arm/include/asm_inline.h b/arch/arm/include/asm_inline.h index 72ae2c7b24f..e930b3a8be3 100644 --- a/arch/arm/include/asm_inline.h +++ b/arch/arm/include/asm_inline.h @@ -33,7 +33,7 @@ #ifndef _ASM_INLINE_H #define _ASM_INLINE_H -#if !defined(CONFIG_ARM) || !defined(CONFIG_CPU_CORTEXM) +#if !defined(CONFIG_ARM) || !defined(CONFIG_CPU_CORTEX_M) #error arch/arm/include/asm_inline.h is for ARM CortexM only #endif diff --git a/arch/arm/include/nanok.h b/arch/arm/include/nanok.h index c7c0fb0a321..17adc413486 100644 --- a/arch/arm/include/nanok.h +++ b/arch/arm/include/nanok.h @@ -120,7 +120,7 @@ typedef struct preempt tPreempt; #define STACK_ROUND_UP(x) ROUND_UP(x, STACK_ALIGN_SIZE) #define STACK_ROUND_DOWN(x) ROUND_DOWN(x, STACK_ALIGN_SIZE) -#ifdef CONFIG_CPU_CORTEXM +#ifdef CONFIG_CPU_CORTEX_M #include #include #endif diff --git a/doc/doxygen/irq_test_common_commented.h b/doc/doxygen/irq_test_common_commented.h index 7a31935366e..fba5a139378 100644 --- a/doc/doxygen/irq_test_common_commented.h +++ b/doc/doxygen/irq_test_common_commented.h @@ -43,9 +43,9 @@ Interrupt stuff, abstracted across CPU architectures. #if defined(CONFIG_X86_32) #define IRQ_PRIORITY 3 #elif defined(CONFIG_ARM) - #if defined(CONFIG_CPU_CORTEXM) + #if defined(CONFIG_CPU_CORTEX_M) #define IRQ_PRIORITY _EXC_PRIO(3) - #endif /* CONFIG_CPU_CORTEXM */ + #endif /* CONFIG_CPU_CORTEX_M */ #endif /* @@ -97,7 +97,7 @@ static char sw_isr_trigger_1[] = #endif /* NUM_SW_IRQS >= 2 */ #elif defined(CONFIG_ARM) -#if defined(CONFIG_CPU_CORTEXM) +#if defined(CONFIG_CPU_CORTEX_M) #include static inline void sw_isr_trigger_0(void) { @@ -110,7 +110,7 @@ static inline void sw_isr_trigger_1(void) _NvicSwInterruptTrigger(1); } #endif /* NUM_SW_IRQS >= 2 */ -#endif /* CONFIG_CPU_CORTEXM */ +#endif /* CONFIG_CPU_CORTEX_M */ #endif /*! Defines the ISR initialization information. */ @@ -161,7 +161,7 @@ static int initIRQ } #endif /* NUM_SW_IRQS >= 2 */ #elif defined(CONFIG_ARM) -#if defined(CONFIG_CPU_CORTEXM) +#if defined(CONFIG_CPU_CORTEX_M) if (i->isr[0]) { (void) irq_connect (0, IRQ_PRIORITY, i->isr[0], i->arg[0]); @@ -172,7 +172,7 @@ static int initIRQ (void) irq_connect (1, IRQ_PRIORITY, i->isr[1], i->arg[1]); irq_enable (1); } -#endif /* CONFIG_CPU_CORTEXM */ +#endif /* CONFIG_CPU_CORTEX_M */ #endif /* CONFIG_X86_32 */ return 0; diff --git a/include/arch/arm/arch.h b/include/arch/arm/arch.h index 980e5c30a00..a47559c7682 100644 --- a/include/arch/arm/arch.h +++ b/include/arch/arm/arch.h @@ -49,7 +49,7 @@ extern "C" { #define OCTET_TO_SIZEOFUNIT(X) (X) #define SIZEOFUNIT_TO_OCTET(X) (X) -#ifdef CONFIG_CPU_CORTEXM +#ifdef CONFIG_CPU_CORTEX_M #include #include #include diff --git a/include/linker-tool-gcc.h b/include/linker-tool-gcc.h index 41c711fcfaf..70f2e0542da 100644 --- a/include/linker-tool-gcc.h +++ b/include/linker-tool-gcc.h @@ -39,7 +39,7 @@ use with the GCC linker. #ifndef __LINKER_TOOL_GCC_H #define __LINKER_TOOL_GCC_H -#if defined(CONFIG_CPU_CORTEXM) +#if defined(CONFIG_CPU_CORTEX_M) OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") #elif defined(CONFIG_ARC) OUTPUT_FORMAT("elf32-littlearc", "elf32-bigarc", "elf32-littlearc") diff --git a/samples/include/irq_test_common.h b/samples/include/irq_test_common.h index 551f2528d39..0fb1c281a73 100644 --- a/samples/include/irq_test_common.h +++ b/samples/include/irq_test_common.h @@ -42,9 +42,9 @@ Interrupt stuff, abstracted across CPU architectures. #if defined(CONFIG_X86_32) #define IRQ_PRIORITY 3 #elif defined(CONFIG_ARM) - #if defined(CONFIG_CPU_CORTEXM) + #if defined(CONFIG_CPU_CORTEX_M) #define IRQ_PRIORITY _EXC_PRIO(3) - #endif /* CONFIG_CPU_CORTEXM */ + #endif /* CONFIG_CPU_CORTEX_M */ #endif /* @@ -91,7 +91,7 @@ static char sw_isr_trigger_1[] = { #endif /* NUM_SW_IRQS >= 2 */ #elif defined(CONFIG_ARM) -#if defined(CONFIG_CPU_CORTEXM) +#if defined(CONFIG_CPU_CORTEX_M) #include static inline void sw_isr_trigger_0(void) { @@ -104,7 +104,7 @@ static inline void sw_isr_trigger_1(void) _NvicSwInterruptTrigger(1); } #endif /* NUM_SW_IRQS >= 2 */ -#endif /* CONFIG_CPU_CORTEXM */ +#endif /* CONFIG_CPU_CORTEX_M */ #endif struct isrInitInfo { @@ -143,7 +143,7 @@ static int initIRQ(struct isrInitInfo *i) } #endif /* NUM_SW_IRQS >= 2 */ #elif defined(CONFIG_ARM) -#if defined(CONFIG_CPU_CORTEXM) +#if defined(CONFIG_CPU_CORTEX_M) if (i->isr[0]) { (void) irq_connect(0, IRQ_PRIORITY, i->isr[0], i->arg[0]); irq_enable(0); @@ -152,7 +152,7 @@ static int initIRQ(struct isrInitInfo *i) (void) irq_connect(1, IRQ_PRIORITY, i->isr[1], i->arg[1]); irq_enable(1); } -#endif /* CONFIG_CPU_CORTEXM */ +#endif /* CONFIG_CPU_CORTEX_M */ #endif /* CONFIG_X86_32 */ return 0;