Rename option CPU_CORTEXM to CPU_CORTEX_M

Makes name more consistent with other CPU_CORTEX_M* options.

Change-Id: I65968cb300207ba0de6231d9a67f2720be77b6ba
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
This commit is contained in:
Peter Mitsis 2015-06-17 11:16:57 -04:00 committed by Anas Nashif
commit 25fd37d9d5
12 changed files with 24 additions and 24 deletions

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@ -39,7 +39,7 @@ config CPU_CORTEX
help help
This option signifies the use of a CPU of the Cortex family. This option signifies the use of a CPU of the Cortex family.
config CPU_CORTEXM config CPU_CORTEX_M
bool "ARM Cortex-M" bool "ARM Cortex-M"
default n default n
select CPU_CORTEX select CPU_CORTEX
@ -50,7 +50,7 @@ config CPU_CORTEXM
config CPU_CORTEX_M3_M4 config CPU_CORTEX_M3_M4
bool "ARM Cortex-M3 or ARM Cortex-M4" bool "ARM Cortex-M3 or ARM Cortex-M4"
default n default n
select CPU_CORTEXM select CPU_CORTEX_M
help help
This option signifies the use of either a Cortex-M3 or Cortex-M4 CPU. This option signifies the use of either a Cortex-M3 or Cortex-M4 CPU.
@ -73,7 +73,7 @@ config CPU_CORTEX_M4
endmenu endmenu
menu "ARM Cortex-M family options" menu "ARM Cortex-M family options"
depends on CPU_CORTEXM depends on CPU_CORTEX_M
config LDREX_STREX_AVAILABLE config LDREX_STREX_AVAILABLE
bool bool

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@ -83,7 +83,7 @@ CONFIG_BSP_FSL_FRDM_K64F=y
# ARM Cortex CPU options # ARM Cortex CPU options
# #
CONFIG_CPU_CORTEX=y CONFIG_CPU_CORTEX=y
CONFIG_CPU_CORTEXM=y CONFIG_CPU_CORTEX_M=y
CONFIG_CPU_CORTEX_M3_M4=y CONFIG_CPU_CORTEX_M3_M4=y
CONFIG_CPU_CORTEX_M3=y CONFIG_CPU_CORTEX_M3=y
CONFIG_CPU_CORTEX_M4=y CONFIG_CPU_CORTEX_M4=y

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@ -83,7 +83,7 @@ CONFIG_BSP_TI_LM3S6965=y
# ARM Cortex CPU options # ARM Cortex CPU options
# #
CONFIG_CPU_CORTEX=y CONFIG_CPU_CORTEX=y
CONFIG_CPU_CORTEXM=y CONFIG_CPU_CORTEX_M=y
CONFIG_CPU_CORTEX_M3_M4=y CONFIG_CPU_CORTEX_M3_M4=y
CONFIG_CPU_CORTEX_M3=y CONFIG_CPU_CORTEX_M3=y
# CONFIG_CPU_CORTEX_M4 is not set # CONFIG_CPU_CORTEX_M4 is not set

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@ -62,7 +62,7 @@ CONFIG_BSP_FSL_FRDM_K64F=y
# ARM Cortex CPU options # ARM Cortex CPU options
# #
CONFIG_CPU_CORTEX=y CONFIG_CPU_CORTEX=y
CONFIG_CPU_CORTEXM=y CONFIG_CPU_CORTEX_M=y
CONFIG_CPU_CORTEX_M3_M4=y CONFIG_CPU_CORTEX_M3_M4=y
CONFIG_CPU_CORTEX_M3=y CONFIG_CPU_CORTEX_M3=y
CONFIG_CPU_CORTEX_M4=y CONFIG_CPU_CORTEX_M4=y

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@ -62,7 +62,7 @@ CONFIG_BSP_TI_LM3S6965=y
# ARM Cortex CPU options # ARM Cortex CPU options
# #
CONFIG_CPU_CORTEX=y CONFIG_CPU_CORTEX=y
CONFIG_CPU_CORTEXM=y CONFIG_CPU_CORTEX_M=y
CONFIG_CPU_CORTEX_M3_M4=y CONFIG_CPU_CORTEX_M3_M4=y
CONFIG_CPU_CORTEX_M3=y CONFIG_CPU_CORTEX_M3=y
# CONFIG_CPU_CORTEX_M4 is not set # CONFIG_CPU_CORTEX_M4 is not set

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@ -83,7 +83,7 @@ CONFIG_BSP_FSL_FRDM_K64F=y
# ARM Cortex CPU options # ARM Cortex CPU options
# #
CONFIG_CPU_CORTEX=y CONFIG_CPU_CORTEX=y
CONFIG_CPU_CORTEXM=y CONFIG_CPU_CORTEX_M=y
CONFIG_CPU_CORTEX_M3_M4=y CONFIG_CPU_CORTEX_M3_M4=y
CONFIG_CPU_CORTEX_M3=y CONFIG_CPU_CORTEX_M3=y
CONFIG_CPU_CORTEX_M4=y CONFIG_CPU_CORTEX_M4=y

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@ -33,7 +33,7 @@
#ifndef _ASM_INLINE_H #ifndef _ASM_INLINE_H
#define _ASM_INLINE_H #define _ASM_INLINE_H
#if !defined(CONFIG_ARM) || !defined(CONFIG_CPU_CORTEXM) #if !defined(CONFIG_ARM) || !defined(CONFIG_CPU_CORTEX_M)
#error arch/arm/include/asm_inline.h is for ARM CortexM only #error arch/arm/include/asm_inline.h is for ARM CortexM only
#endif #endif

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@ -120,7 +120,7 @@ typedef struct preempt tPreempt;
#define STACK_ROUND_UP(x) ROUND_UP(x, STACK_ALIGN_SIZE) #define STACK_ROUND_UP(x) ROUND_UP(x, STACK_ALIGN_SIZE)
#define STACK_ROUND_DOWN(x) ROUND_DOWN(x, STACK_ALIGN_SIZE) #define STACK_ROUND_DOWN(x) ROUND_DOWN(x, STACK_ALIGN_SIZE)
#ifdef CONFIG_CPU_CORTEXM #ifdef CONFIG_CPU_CORTEX_M
#include <CortexM/stack.h> #include <CortexM/stack.h>
#include <CortexM/exc.h> #include <CortexM/exc.h>
#endif #endif

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@ -43,9 +43,9 @@ Interrupt stuff, abstracted across CPU architectures.
#if defined(CONFIG_X86_32) #if defined(CONFIG_X86_32)
#define IRQ_PRIORITY 3 #define IRQ_PRIORITY 3
#elif defined(CONFIG_ARM) #elif defined(CONFIG_ARM)
#if defined(CONFIG_CPU_CORTEXM) #if defined(CONFIG_CPU_CORTEX_M)
#define IRQ_PRIORITY _EXC_PRIO(3) #define IRQ_PRIORITY _EXC_PRIO(3)
#endif /* CONFIG_CPU_CORTEXM */ #endif /* CONFIG_CPU_CORTEX_M */
#endif #endif
/* /*
@ -97,7 +97,7 @@ static char sw_isr_trigger_1[] =
#endif /* NUM_SW_IRQS >= 2 */ #endif /* NUM_SW_IRQS >= 2 */
#elif defined(CONFIG_ARM) #elif defined(CONFIG_ARM)
#if defined(CONFIG_CPU_CORTEXM) #if defined(CONFIG_CPU_CORTEX_M)
#include <nanokernel.h> #include <nanokernel.h>
static inline void sw_isr_trigger_0(void) static inline void sw_isr_trigger_0(void)
{ {
@ -110,7 +110,7 @@ static inline void sw_isr_trigger_1(void)
_NvicSwInterruptTrigger(1); _NvicSwInterruptTrigger(1);
} }
#endif /* NUM_SW_IRQS >= 2 */ #endif /* NUM_SW_IRQS >= 2 */
#endif /* CONFIG_CPU_CORTEXM */ #endif /* CONFIG_CPU_CORTEX_M */
#endif #endif
/*! Defines the ISR initialization information. */ /*! Defines the ISR initialization information. */
@ -161,7 +161,7 @@ static int initIRQ
} }
#endif /* NUM_SW_IRQS >= 2 */ #endif /* NUM_SW_IRQS >= 2 */
#elif defined(CONFIG_ARM) #elif defined(CONFIG_ARM)
#if defined(CONFIG_CPU_CORTEXM) #if defined(CONFIG_CPU_CORTEX_M)
if (i->isr[0]) if (i->isr[0])
{ {
(void) irq_connect (0, IRQ_PRIORITY, i->isr[0], i->arg[0]); (void) irq_connect (0, IRQ_PRIORITY, i->isr[0], i->arg[0]);
@ -172,7 +172,7 @@ static int initIRQ
(void) irq_connect (1, IRQ_PRIORITY, i->isr[1], i->arg[1]); (void) irq_connect (1, IRQ_PRIORITY, i->isr[1], i->arg[1]);
irq_enable (1); irq_enable (1);
} }
#endif /* CONFIG_CPU_CORTEXM */ #endif /* CONFIG_CPU_CORTEX_M */
#endif /* CONFIG_X86_32 */ #endif /* CONFIG_X86_32 */
return 0; return 0;

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@ -49,7 +49,7 @@ extern "C" {
#define OCTET_TO_SIZEOFUNIT(X) (X) #define OCTET_TO_SIZEOFUNIT(X) (X)
#define SIZEOFUNIT_TO_OCTET(X) (X) #define SIZEOFUNIT_TO_OCTET(X) (X)
#ifdef CONFIG_CPU_CORTEXM #ifdef CONFIG_CPU_CORTEX_M
#include <arch/arm/CortexM/exc.h> #include <arch/arm/CortexM/exc.h>
#include <arch/arm/CortexM/irq.h> #include <arch/arm/CortexM/irq.h>
#include <arch/arm/CortexM/ffs.h> #include <arch/arm/CortexM/ffs.h>

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@ -39,7 +39,7 @@ use with the GCC linker.
#ifndef __LINKER_TOOL_GCC_H #ifndef __LINKER_TOOL_GCC_H
#define __LINKER_TOOL_GCC_H #define __LINKER_TOOL_GCC_H
#if defined(CONFIG_CPU_CORTEXM) #if defined(CONFIG_CPU_CORTEX_M)
OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
#elif defined(CONFIG_ARC) #elif defined(CONFIG_ARC)
OUTPUT_FORMAT("elf32-littlearc", "elf32-bigarc", "elf32-littlearc") OUTPUT_FORMAT("elf32-littlearc", "elf32-bigarc", "elf32-littlearc")

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@ -42,9 +42,9 @@ Interrupt stuff, abstracted across CPU architectures.
#if defined(CONFIG_X86_32) #if defined(CONFIG_X86_32)
#define IRQ_PRIORITY 3 #define IRQ_PRIORITY 3
#elif defined(CONFIG_ARM) #elif defined(CONFIG_ARM)
#if defined(CONFIG_CPU_CORTEXM) #if defined(CONFIG_CPU_CORTEX_M)
#define IRQ_PRIORITY _EXC_PRIO(3) #define IRQ_PRIORITY _EXC_PRIO(3)
#endif /* CONFIG_CPU_CORTEXM */ #endif /* CONFIG_CPU_CORTEX_M */
#endif #endif
/* /*
@ -91,7 +91,7 @@ static char sw_isr_trigger_1[] = {
#endif /* NUM_SW_IRQS >= 2 */ #endif /* NUM_SW_IRQS >= 2 */
#elif defined(CONFIG_ARM) #elif defined(CONFIG_ARM)
#if defined(CONFIG_CPU_CORTEXM) #if defined(CONFIG_CPU_CORTEX_M)
#include <nanokernel.h> #include <nanokernel.h>
static inline void sw_isr_trigger_0(void) static inline void sw_isr_trigger_0(void)
{ {
@ -104,7 +104,7 @@ static inline void sw_isr_trigger_1(void)
_NvicSwInterruptTrigger(1); _NvicSwInterruptTrigger(1);
} }
#endif /* NUM_SW_IRQS >= 2 */ #endif /* NUM_SW_IRQS >= 2 */
#endif /* CONFIG_CPU_CORTEXM */ #endif /* CONFIG_CPU_CORTEX_M */
#endif #endif
struct isrInitInfo { struct isrInitInfo {
@ -143,7 +143,7 @@ static int initIRQ(struct isrInitInfo *i)
} }
#endif /* NUM_SW_IRQS >= 2 */ #endif /* NUM_SW_IRQS >= 2 */
#elif defined(CONFIG_ARM) #elif defined(CONFIG_ARM)
#if defined(CONFIG_CPU_CORTEXM) #if defined(CONFIG_CPU_CORTEX_M)
if (i->isr[0]) { if (i->isr[0]) {
(void) irq_connect(0, IRQ_PRIORITY, i->isr[0], i->arg[0]); (void) irq_connect(0, IRQ_PRIORITY, i->isr[0], i->arg[0]);
irq_enable(0); irq_enable(0);
@ -152,7 +152,7 @@ static int initIRQ(struct isrInitInfo *i)
(void) irq_connect(1, IRQ_PRIORITY, i->isr[1], i->arg[1]); (void) irq_connect(1, IRQ_PRIORITY, i->isr[1], i->arg[1]);
irq_enable(1); irq_enable(1);
} }
#endif /* CONFIG_CPU_CORTEXM */ #endif /* CONFIG_CPU_CORTEX_M */
#endif /* CONFIG_X86_32 */ #endif /* CONFIG_X86_32 */
return 0; return 0;