Rename option CPU_CORTEXM to CPU_CORTEX_M
Makes name more consistent with other CPU_CORTEX_M* options. Change-Id: I65968cb300207ba0de6231d9a67f2720be77b6ba Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
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12 changed files with 24 additions and 24 deletions
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@ -39,7 +39,7 @@ config CPU_CORTEX
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help
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help
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This option signifies the use of a CPU of the Cortex family.
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This option signifies the use of a CPU of the Cortex family.
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config CPU_CORTEXM
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config CPU_CORTEX_M
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bool "ARM Cortex-M"
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bool "ARM Cortex-M"
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default n
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default n
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select CPU_CORTEX
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select CPU_CORTEX
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@ -50,7 +50,7 @@ config CPU_CORTEXM
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config CPU_CORTEX_M3_M4
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config CPU_CORTEX_M3_M4
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bool "ARM Cortex-M3 or ARM Cortex-M4"
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bool "ARM Cortex-M3 or ARM Cortex-M4"
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default n
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default n
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select CPU_CORTEXM
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select CPU_CORTEX_M
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help
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help
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This option signifies the use of either a Cortex-M3 or Cortex-M4 CPU.
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This option signifies the use of either a Cortex-M3 or Cortex-M4 CPU.
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@ -73,7 +73,7 @@ config CPU_CORTEX_M4
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endmenu
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endmenu
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menu "ARM Cortex-M family options"
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menu "ARM Cortex-M family options"
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depends on CPU_CORTEXM
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depends on CPU_CORTEX_M
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config LDREX_STREX_AVAILABLE
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config LDREX_STREX_AVAILABLE
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bool
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bool
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@ -83,7 +83,7 @@ CONFIG_BSP_FSL_FRDM_K64F=y
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# ARM Cortex CPU options
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# ARM Cortex CPU options
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#
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#
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CONFIG_CPU_CORTEX=y
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CONFIG_CPU_CORTEX=y
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CONFIG_CPU_CORTEXM=y
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CONFIG_CPU_CORTEX_M=y
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CONFIG_CPU_CORTEX_M3_M4=y
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CONFIG_CPU_CORTEX_M3_M4=y
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CONFIG_CPU_CORTEX_M3=y
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CONFIG_CPU_CORTEX_M3=y
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CONFIG_CPU_CORTEX_M4=y
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CONFIG_CPU_CORTEX_M4=y
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@ -83,7 +83,7 @@ CONFIG_BSP_TI_LM3S6965=y
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# ARM Cortex CPU options
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# ARM Cortex CPU options
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#
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#
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CONFIG_CPU_CORTEX=y
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CONFIG_CPU_CORTEX=y
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CONFIG_CPU_CORTEXM=y
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CONFIG_CPU_CORTEX_M=y
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CONFIG_CPU_CORTEX_M3_M4=y
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CONFIG_CPU_CORTEX_M3_M4=y
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CONFIG_CPU_CORTEX_M3=y
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CONFIG_CPU_CORTEX_M3=y
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# CONFIG_CPU_CORTEX_M4 is not set
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# CONFIG_CPU_CORTEX_M4 is not set
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@ -62,7 +62,7 @@ CONFIG_BSP_FSL_FRDM_K64F=y
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# ARM Cortex CPU options
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# ARM Cortex CPU options
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#
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#
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CONFIG_CPU_CORTEX=y
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CONFIG_CPU_CORTEX=y
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CONFIG_CPU_CORTEXM=y
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CONFIG_CPU_CORTEX_M=y
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CONFIG_CPU_CORTEX_M3_M4=y
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CONFIG_CPU_CORTEX_M3_M4=y
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CONFIG_CPU_CORTEX_M3=y
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CONFIG_CPU_CORTEX_M3=y
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CONFIG_CPU_CORTEX_M4=y
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CONFIG_CPU_CORTEX_M4=y
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@ -62,7 +62,7 @@ CONFIG_BSP_TI_LM3S6965=y
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# ARM Cortex CPU options
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# ARM Cortex CPU options
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#
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#
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CONFIG_CPU_CORTEX=y
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CONFIG_CPU_CORTEX=y
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CONFIG_CPU_CORTEXM=y
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CONFIG_CPU_CORTEX_M=y
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CONFIG_CPU_CORTEX_M3_M4=y
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CONFIG_CPU_CORTEX_M3_M4=y
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CONFIG_CPU_CORTEX_M3=y
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CONFIG_CPU_CORTEX_M3=y
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# CONFIG_CPU_CORTEX_M4 is not set
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# CONFIG_CPU_CORTEX_M4 is not set
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@ -83,7 +83,7 @@ CONFIG_BSP_FSL_FRDM_K64F=y
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# ARM Cortex CPU options
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# ARM Cortex CPU options
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#
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#
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CONFIG_CPU_CORTEX=y
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CONFIG_CPU_CORTEX=y
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CONFIG_CPU_CORTEXM=y
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CONFIG_CPU_CORTEX_M=y
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CONFIG_CPU_CORTEX_M3_M4=y
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CONFIG_CPU_CORTEX_M3_M4=y
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CONFIG_CPU_CORTEX_M3=y
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CONFIG_CPU_CORTEX_M3=y
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CONFIG_CPU_CORTEX_M4=y
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CONFIG_CPU_CORTEX_M4=y
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@ -33,7 +33,7 @@
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#ifndef _ASM_INLINE_H
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#ifndef _ASM_INLINE_H
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#define _ASM_INLINE_H
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#define _ASM_INLINE_H
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#if !defined(CONFIG_ARM) || !defined(CONFIG_CPU_CORTEXM)
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#if !defined(CONFIG_ARM) || !defined(CONFIG_CPU_CORTEX_M)
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#error arch/arm/include/asm_inline.h is for ARM CortexM only
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#error arch/arm/include/asm_inline.h is for ARM CortexM only
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#endif
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#endif
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@ -120,7 +120,7 @@ typedef struct preempt tPreempt;
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#define STACK_ROUND_UP(x) ROUND_UP(x, STACK_ALIGN_SIZE)
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#define STACK_ROUND_UP(x) ROUND_UP(x, STACK_ALIGN_SIZE)
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#define STACK_ROUND_DOWN(x) ROUND_DOWN(x, STACK_ALIGN_SIZE)
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#define STACK_ROUND_DOWN(x) ROUND_DOWN(x, STACK_ALIGN_SIZE)
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#ifdef CONFIG_CPU_CORTEXM
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#ifdef CONFIG_CPU_CORTEX_M
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#include <CortexM/stack.h>
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#include <CortexM/stack.h>
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#include <CortexM/exc.h>
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#include <CortexM/exc.h>
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#endif
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#endif
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@ -43,9 +43,9 @@ Interrupt stuff, abstracted across CPU architectures.
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#if defined(CONFIG_X86_32)
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#if defined(CONFIG_X86_32)
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#define IRQ_PRIORITY 3
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#define IRQ_PRIORITY 3
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#elif defined(CONFIG_ARM)
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#elif defined(CONFIG_ARM)
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#if defined(CONFIG_CPU_CORTEXM)
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#if defined(CONFIG_CPU_CORTEX_M)
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#define IRQ_PRIORITY _EXC_PRIO(3)
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#define IRQ_PRIORITY _EXC_PRIO(3)
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#endif /* CONFIG_CPU_CORTEXM */
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#endif /* CONFIG_CPU_CORTEX_M */
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#endif
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#endif
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/*
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/*
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@ -97,7 +97,7 @@ static char sw_isr_trigger_1[] =
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#endif /* NUM_SW_IRQS >= 2 */
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#endif /* NUM_SW_IRQS >= 2 */
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#elif defined(CONFIG_ARM)
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#elif defined(CONFIG_ARM)
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#if defined(CONFIG_CPU_CORTEXM)
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#if defined(CONFIG_CPU_CORTEX_M)
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#include <nanokernel.h>
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#include <nanokernel.h>
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static inline void sw_isr_trigger_0(void)
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static inline void sw_isr_trigger_0(void)
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{
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{
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@ -110,7 +110,7 @@ static inline void sw_isr_trigger_1(void)
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_NvicSwInterruptTrigger(1);
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_NvicSwInterruptTrigger(1);
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}
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}
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#endif /* NUM_SW_IRQS >= 2 */
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#endif /* NUM_SW_IRQS >= 2 */
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#endif /* CONFIG_CPU_CORTEXM */
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#endif /* CONFIG_CPU_CORTEX_M */
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#endif
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#endif
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/*! Defines the ISR initialization information. */
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/*! Defines the ISR initialization information. */
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@ -161,7 +161,7 @@ static int initIRQ
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}
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}
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#endif /* NUM_SW_IRQS >= 2 */
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#endif /* NUM_SW_IRQS >= 2 */
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#elif defined(CONFIG_ARM)
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#elif defined(CONFIG_ARM)
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#if defined(CONFIG_CPU_CORTEXM)
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#if defined(CONFIG_CPU_CORTEX_M)
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if (i->isr[0])
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if (i->isr[0])
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{
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{
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(void) irq_connect (0, IRQ_PRIORITY, i->isr[0], i->arg[0]);
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(void) irq_connect (0, IRQ_PRIORITY, i->isr[0], i->arg[0]);
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@ -172,7 +172,7 @@ static int initIRQ
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(void) irq_connect (1, IRQ_PRIORITY, i->isr[1], i->arg[1]);
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(void) irq_connect (1, IRQ_PRIORITY, i->isr[1], i->arg[1]);
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irq_enable (1);
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irq_enable (1);
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}
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}
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#endif /* CONFIG_CPU_CORTEXM */
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#endif /* CONFIG_CPU_CORTEX_M */
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#endif /* CONFIG_X86_32 */
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#endif /* CONFIG_X86_32 */
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return 0;
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return 0;
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@ -49,7 +49,7 @@ extern "C" {
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#define OCTET_TO_SIZEOFUNIT(X) (X)
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#define OCTET_TO_SIZEOFUNIT(X) (X)
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#define SIZEOFUNIT_TO_OCTET(X) (X)
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#define SIZEOFUNIT_TO_OCTET(X) (X)
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#ifdef CONFIG_CPU_CORTEXM
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#ifdef CONFIG_CPU_CORTEX_M
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#include <arch/arm/CortexM/exc.h>
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#include <arch/arm/CortexM/exc.h>
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#include <arch/arm/CortexM/irq.h>
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#include <arch/arm/CortexM/irq.h>
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#include <arch/arm/CortexM/ffs.h>
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#include <arch/arm/CortexM/ffs.h>
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@ -39,7 +39,7 @@ use with the GCC linker.
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#ifndef __LINKER_TOOL_GCC_H
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#ifndef __LINKER_TOOL_GCC_H
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#define __LINKER_TOOL_GCC_H
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#define __LINKER_TOOL_GCC_H
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#if defined(CONFIG_CPU_CORTEXM)
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#if defined(CONFIG_CPU_CORTEX_M)
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OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
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OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
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#elif defined(CONFIG_ARC)
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#elif defined(CONFIG_ARC)
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OUTPUT_FORMAT("elf32-littlearc", "elf32-bigarc", "elf32-littlearc")
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OUTPUT_FORMAT("elf32-littlearc", "elf32-bigarc", "elf32-littlearc")
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#if defined(CONFIG_X86_32)
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#if defined(CONFIG_X86_32)
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#define IRQ_PRIORITY 3
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#define IRQ_PRIORITY 3
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#elif defined(CONFIG_ARM)
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#elif defined(CONFIG_ARM)
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#if defined(CONFIG_CPU_CORTEXM)
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#if defined(CONFIG_CPU_CORTEX_M)
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#define IRQ_PRIORITY _EXC_PRIO(3)
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#define IRQ_PRIORITY _EXC_PRIO(3)
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#endif /* CONFIG_CPU_CORTEXM */
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#endif /* CONFIG_CPU_CORTEX_M */
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#endif
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#endif
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/*
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/*
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@ -91,7 +91,7 @@ static char sw_isr_trigger_1[] = {
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#endif /* NUM_SW_IRQS >= 2 */
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#endif /* NUM_SW_IRQS >= 2 */
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#elif defined(CONFIG_ARM)
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#elif defined(CONFIG_ARM)
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#if defined(CONFIG_CPU_CORTEXM)
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#if defined(CONFIG_CPU_CORTEX_M)
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#include <nanokernel.h>
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#include <nanokernel.h>
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static inline void sw_isr_trigger_0(void)
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static inline void sw_isr_trigger_0(void)
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{
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{
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_NvicSwInterruptTrigger(1);
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_NvicSwInterruptTrigger(1);
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}
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}
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#endif /* NUM_SW_IRQS >= 2 */
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#endif /* NUM_SW_IRQS >= 2 */
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#endif /* CONFIG_CPU_CORTEXM */
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#endif /* CONFIG_CPU_CORTEX_M */
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#endif
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#endif
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struct isrInitInfo {
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struct isrInitInfo {
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@ -143,7 +143,7 @@ static int initIRQ(struct isrInitInfo *i)
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}
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}
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#endif /* NUM_SW_IRQS >= 2 */
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#endif /* NUM_SW_IRQS >= 2 */
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#elif defined(CONFIG_ARM)
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#elif defined(CONFIG_ARM)
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#if defined(CONFIG_CPU_CORTEXM)
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#if defined(CONFIG_CPU_CORTEX_M)
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if (i->isr[0]) {
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if (i->isr[0]) {
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(void) irq_connect(0, IRQ_PRIORITY, i->isr[0], i->arg[0]);
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(void) irq_connect(0, IRQ_PRIORITY, i->isr[0], i->arg[0]);
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irq_enable(0);
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irq_enable(0);
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(void) irq_connect(1, IRQ_PRIORITY, i->isr[1], i->arg[1]);
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(void) irq_connect(1, IRQ_PRIORITY, i->isr[1], i->arg[1]);
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irq_enable(1);
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irq_enable(1);
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}
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}
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#endif /* CONFIG_CPU_CORTEXM */
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#endif /* CONFIG_CPU_CORTEX_M */
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#endif /* CONFIG_X86_32 */
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#endif /* CONFIG_X86_32 */
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return 0;
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return 0;
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