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x86: remove @return doc for void functions

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For functions returning nothing, there is no need to document
with @return, as Doxgen complains about "documented empty
return type of ...".

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit is contained in:
Daniel Leung 2022-01-06 17:05:53 -08:00 • committed by Anas Nashif
commit 25f87aac87
5 changed files with 0 additions and 24 deletions
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2
arch/x86/core/cache.c
View file

@ -26,8 +26,6 @@
* both is optimal. * both is optimal.
* *
* The cache line size is specified via the d-cache-line-size DTS property. * The cache line size is specified via the d-cache-line-size DTS property.
*
* @return N/A
*/ */
static void arch_dcache_flush(void *start_addr, size_t size) static void arch_dcache_flush(void *start_addr, size_t size)
{ {

2
arch/x86/core/ia32/excstub.S
View file

@ -45,8 +45,6 @@
* created by this routine to determine the locations of volatile registers. * created by this routine to determine the locations of volatile registers.
* These tools must be updated to reflect any changes to the stack frame. * These tools must be updated to reflect any changes to the stack frame.
* *
* @return N/A
*
* C function prototype: * C function prototype:
* *
* void _exception_enter(uint32_t error_code, void *handler) * void _exception_enter(uint32_t error_code, void *handler)

15
arch/x86/core/ia32/float.c
View file

@ -50,13 +50,10 @@
extern uint32_t _sse_mxcsr_default_value; extern uint32_t _sse_mxcsr_default_value;
/** /**
*
* @brief Disallow use of floating point capabilities * @brief Disallow use of floating point capabilities
* *
* This routine sets CR0[TS] to 1, which disallows the use of FP instructions * This routine sets CR0[TS] to 1, which disallows the use of FP instructions
* by the currently executing thread. * by the currently executing thread.
*
* @return N/A
*/ */
static inline void z_FpAccessDisable(void) static inline void z_FpAccessDisable(void)
{ {
@ -73,15 +70,12 @@ static inline void z_FpAccessDisable(void)
/** /**
*
* @brief Save non-integer context information * @brief Save non-integer context information
* *
* This routine saves the system's "live" non-integer context into the * This routine saves the system's "live" non-integer context into the
* specified area. If the specified thread supports SSE then * specified area. If the specified thread supports SSE then
* x87/MMX/SSEx thread info is saved, otherwise only x87/MMX thread is saved. * x87/MMX/SSEx thread info is saved, otherwise only x87/MMX thread is saved.
* Function is invoked by FpCtxSave(struct k_thread *thread) * Function is invoked by FpCtxSave(struct k_thread *thread)
*
* @return N/A
*/ */
static inline void z_do_fp_regs_save(void *preemp_float_reg) static inline void z_do_fp_regs_save(void *preemp_float_reg)
{ {
@ -92,15 +86,12 @@ static inline void z_do_fp_regs_save(void *preemp_float_reg)
} }
/** /**
*
* @brief Save non-integer context information * @brief Save non-integer context information
* *
* This routine saves the system's "live" non-integer context into the * This routine saves the system's "live" non-integer context into the
* specified area. If the specified thread supports SSE then * specified area. If the specified thread supports SSE then
* x87/MMX/SSEx thread info is saved, otherwise only x87/MMX thread is saved. * x87/MMX/SSEx thread info is saved, otherwise only x87/MMX thread is saved.
* Function is invoked by FpCtxSave(struct k_thread *thread) * Function is invoked by FpCtxSave(struct k_thread *thread)
*
* @return N/A
*/ */
static inline void z_do_fp_and_sse_regs_save(void *preemp_float_reg) static inline void z_do_fp_and_sse_regs_save(void *preemp_float_reg)
{ {
@ -111,12 +102,9 @@ static inline void z_do_fp_and_sse_regs_save(void *preemp_float_reg)
} }
/** /**
*
* @brief Initialize floating point register context information. * @brief Initialize floating point register context information.
* *
* This routine initializes the system's "live" floating point registers. * This routine initializes the system's "live" floating point registers.
*
* @return N/A
*/ */
static inline void z_do_fp_regs_init(void) static inline void z_do_fp_regs_init(void)
{ {
@ -124,12 +112,9 @@ static inline void z_do_fp_regs_init(void)
} }
/** /**
*
* @brief Initialize SSE register context information. * @brief Initialize SSE register context information.
* *
* This routine initializes the system's "live" SSE registers. * This routine initializes the system's "live" SSE registers.
*
* @return N/A
*/ */
static inline void z_do_sse_regs_init(void) static inline void z_do_sse_regs_init(void)
{ {

2
arch/x86/core/ia32/intstub.S
View file

@ -56,8 +56,6 @@
* created by this routine to determine the locations of volatile registers. * created by this routine to determine the locations of volatile registers.
* These tools must be updated to reflect any changes to the stack frame. * These tools must be updated to reflect any changes to the stack frame.
* *
* @return N/A
*
* C function prototype: * C function prototype:
* *
* void _interrupt_enter(void *isr, void *isr_param); * void _interrupt_enter(void *isr, void *isr_param);

3
include/arch/x86/ia32/arch.h
View file

@ -115,9 +115,6 @@ typedef struct s_isrList {
* @param p IRQ priority * @param p IRQ priority
* @param v Interrupt Vector * @param v Interrupt Vector
* @param d Descriptor Privilege Level * @param d Descriptor Privilege Level
*
* @return N/A
*
*/ */
#define NANO_CPU_INT_REGISTER(r, n, p, v, d) \ #define NANO_CPU_INT_REGISTER(r, n, p, v, d) \