npcx: scfg: psl: cleanup unused functions and DT files
Clean up unused psl functions in scfg.c, unused DT macros, unused psl DT nodes and related yaml files. Currently, PSL pad configurations are made by pinctrl mechanism. Please refer https://issuetracker.google.com/234861079 for more detail. Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This commit is contained in:
Mulin Chao
Carles Cufí
parent
1fc243c73d
commit
24fb705cdd
15 changed files with 1 additions and 490 deletions
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@ -50,22 +50,12 @@
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min-residency-us = <201000>;
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min-residency-us = <201000>;
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};
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};
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};
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};
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vsby-psl-in-list {
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psl-in-pads = <&psl_in1>; /* Use PSL_IN1 as detection pins */
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status = "okay";
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};
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};
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};
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&cpu0 {
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&cpu0 {
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cpu-power-states = <&suspend_to_idle0 &suspend_to_idle1>;
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cpu-power-states = <&suspend_to_idle0 &suspend_to_idle1>;
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};
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};
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&psl_in1 {
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/* A falling edge detection type for PSL_IN1 */
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flag = <NPCX_PSL_FALLING_EDGE>;
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};
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/* Overwrite default device properties with overlays in board dt file here. */
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/* Overwrite default device properties with overlays in board dt file here. */
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&uart1 {
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&uart1 {
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status = "okay";
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status = "okay";
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@ -62,22 +62,12 @@
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min-residency-us = <201000>;
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min-residency-us = <201000>;
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};
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};
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};
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};
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vsby-psl-in-list {
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psl-in-pads = <&psl_in1>; /* Use PSL_IN1 as detection pins */
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status = "okay";
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};
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};
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};
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&cpu0 {
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&cpu0 {
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cpu-power-states = <&suspend_to_idle0 &suspend_to_idle1>;
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cpu-power-states = <&suspend_to_idle0 &suspend_to_idle1>;
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};
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};
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&psl_in1 {
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/* A falling edge detection type for PSL_IN1 */
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flag = <NPCX_PSL_FALLING_EDGE>;
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};
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/* Overwrite default device properties with overlays in board dt file here. */
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/* Overwrite default device properties with overlays in board dt file here. */
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&uart1 {
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&uart1 {
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status = "okay";
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status = "okay";
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@ -54,21 +54,6 @@
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lvol-io-pads = <>;
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lvol-io-pads = <>;
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};
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};
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vsby-psl-in-list {
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compatible = "nuvoton,npcx-pslctrl-def";
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/* Put Power Switch Logic (PSL) input pads which detect the
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* wake-up events and turn on core power supply (VCC1) from
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* standby power state (ultra-low-power mode) into "psl-in-pads"
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* property. For example, if PSL input 1 that is plan to detect
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* a 'falling edge' event, this property should be:
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* psl-in-pads = <&psl_in1>;
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* And the flag property in psl_in1 should change to
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* flag = <NPCX_PSL_FALLING_EDGE>;
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*/
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psl-in-pads = <>;
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status = "disabled";
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};
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/** Dummy pinctrl node. It will be initialized with defaults based on the SoC series.
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/** Dummy pinctrl node. It will be initialized with defaults based on the SoC series.
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* Then, the user can override the pin control options at the board level.
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* Then, the user can override the pin control options at the board level.
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*/
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*/
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@ -585,13 +570,6 @@
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status = "disabled";
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status = "disabled";
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};
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};
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psl_out: psl-out {
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compatible = "nuvoton,npcx-psl-out";
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controller = <&gpio8>;
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pin = <5>;
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label = "PSL_OUT";
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};
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i2c0_0: io_i2c_ctrl0_port0 {
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i2c0_0: io_i2c_ctrl0_port0 {
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compatible = "nuvoton,npcx-i2c-port";
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compatible = "nuvoton,npcx-i2c-port";
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#address-cells = <1>;
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#address-cells = <1>;
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@ -1,33 +0,0 @@
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/*
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* Copyright (c) 2021 Nuvoton Technology Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/ {
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def-psl-conf-list {
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compatible = "nuvoton,npcx-pslctrl-conf";
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/* PSL input IO configurations */
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psl_in1: psl-iod2 {
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offset = <0>; /* PSL_IN1/PIND2 */
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pinctrl-0 = <&altd_npsl_in1_sl>;
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polarity-0 = <&altd_psl_in1_ahi>;
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};
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psl_in2: psl-io00 {
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offset = <1>; /* PSL_IN2/PIN00 */
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pinctrl-0 = <&altd_npsl_in2_sl>;
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polarity-0 = <&altd_psl_in2_ahi>;
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};
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psl_in3: psl-io01 {
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offset = <2>; /* PSL_IN3/PIN01 */
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pinctrl-0 = <&altd_psl_in3_sl>;
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polarity-0 = <&altd_psl_in3_ahi>;
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};
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psl_in4: psl-io02 {
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offset = <3>; /* PSL_IN4/PIN02 */
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pinctrl-0 = <&altd_psl_in4_sl>;
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polarity-0 = <&altd_psl_in4_ahi>;
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};
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};
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};
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@ -1,10 +0,0 @@
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/*
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* Copyright (c) 2021 Nuvoton Technology Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* Common Power Switch Logic (PSL) pads configurations in npcx family */
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#include <nuvoton/npcx/npcx-psl-ctrl-map.dtsi>
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/* Specific Power Switch Logic (PSL) pads configurations in npcx7 series */
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@ -1,10 +0,0 @@
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/*
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* Copyright (c) 2021 Nuvoton Technology Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* Common Power Switch Logic (PSL) pads configurations in npcx family */
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#include <nuvoton/npcx/npcx-psl-ctrl-map.dtsi>
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/* Specific Power Switch Logic (PSL) pads configurations in npcx9 series */
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@ -14,8 +14,6 @@
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#include "npcx/npcx7/npcx7-espi-vws-map.dtsi"
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#include "npcx/npcx7/npcx7-espi-vws-map.dtsi"
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/* NPCX7 series low-voltage io controls mapping table */
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/* NPCX7 series low-voltage io controls mapping table */
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#include "npcx/npcx7/npcx7-lvol-ctrl-map.dtsi"
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#include "npcx/npcx7/npcx7-lvol-ctrl-map.dtsi"
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/* NPCX7 series power-switch-logic (PSL) io controls mapping table */
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#include "npcx/npcx7/npcx7-psl-ctrl-map.dtsi"
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/* Device tree declarations of npcx soc family */
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/* Device tree declarations of npcx soc family */
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#include "npcx.dtsi"
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#include "npcx.dtsi"
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@ -14,8 +14,6 @@
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#include "npcx/npcx9/npcx9-espi-vws-map.dtsi"
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#include "npcx/npcx9/npcx9-espi-vws-map.dtsi"
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/* NPCX9 series low-voltage io controls mapping table */
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/* NPCX9 series low-voltage io controls mapping table */
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#include "npcx/npcx9/npcx9-lvol-ctrl-map.dtsi"
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#include "npcx/npcx9/npcx9-lvol-ctrl-map.dtsi"
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/* NPCX9 series power-switch-logic (PSL) io controls mapping table */
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#include "npcx/npcx9/npcx9-psl-ctrl-map.dtsi"
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/* Device tree declarations of npcx soc family */
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/* Device tree declarations of npcx soc family */
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#include "npcx.dtsi"
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#include "npcx.dtsi"
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@ -1,19 +0,0 @@
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# Copyright (c) 2021 Nuvoton Technology Corporation.
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# SPDX-License-Identifier: Apache-2.0
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description: Nuvoton, NPCX-PSL (Power Switch Logic) Output node
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compatible: "nuvoton,npcx-psl-out"
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include: [base.yaml]
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properties:
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controller:
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type: phandle
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required: true
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description: gpio controller to handle PSL output pad.
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pin:
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type: int
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required: true
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description: pin in gpio controller for PSL output.
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@ -1,44 +0,0 @@
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# Copyright (c) 2021 Nuvoton Technology Corporation.
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# SPDX-License-Identifier: Apache-2.0
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description: |
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Nuvoton NPCX pads configuration map between Pin Mux controller and
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Power Switch Logic (PSL) controller driver instances.
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compatible: "nuvoton,npcx-pslctrl-conf"
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child-binding:
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description: |
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Child node to present the mapping between pin-mux controller
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and its power switch logic (PSL) support
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properties:
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offset:
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type: int
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required: true
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description: Offset in PSL_CTS for status and detection mode.
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pinctrl-0:
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type: phandles
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required: true
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description: Pinmux controller configuration for PSL io pads.
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polarity-0:
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type: phandles
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required: true
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description: Active polarity configuration for PSL io pads.
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flag:
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type: int
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required: false
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description: |
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Detection mode and type for wake-up event detection.
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5 = Configures PSL input in detecting rising edge.
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6 = Configures PSL input in in detecting level high state.
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9 = Configures PSL input in detecting falling edge.
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10 = Configures PSL input in detecting level low state.
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enum:
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- 5
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- 6
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- 9
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- 10
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@ -1,17 +0,0 @@
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# Copyright (c) 2021 Nuvoton Technology Corporation.
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# SPDX-License-Identifier: Apache-2.0
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description: Nuvoton, NPCX Default Power Switch Logic (PSL) input pads configurations
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compatible: "nuvoton,npcx-pslctrl-def"
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include: [base.yaml]
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properties:
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psl-in-pads:
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type: phandles
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required: true
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description: |
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list of PSL input pads that are in charge of detecting the wake-up
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signals and the related circuit will turn on core power supply
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(VCC1) from standby power state (ultra-low-power mode) later.
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* @brief NPCX specific PIN configuration flag
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* @brief NPCX specific PIN configuration flag
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*
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*
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* Pin configuration is coded with the following fields
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* Pin configuration is coded with the following fields
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* Power Switch Logic (PSL) [ 0 : 3 ]
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* Reserved [ 0 : 31]
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* Reserved [ 4 : 31]
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*
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* Applicable to NPCX7 series.
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*/
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*/
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/*
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* Power Switch Logic (PSL) input wake-up mode is sensitive to edge signals.
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*
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* This is a component flag that should be combined with other
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* `NPCX_PSL_ACTIVE_*` flags to produce a meaningful configuration.
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*/
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#define NPCX_PSL_MODE_EDGE (1 << 0)
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/*
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* Power Switch Logic (PSL) input wake-up mode is sensitive to logical levels.
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*
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* This is a component flag that should be combined with other
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* `NPCX_PSL_ACTIVE_*` flags to produce a meaningful configuration.
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*/
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#define NPCX_PSL_MODE_LEVEL (1 << 1)
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/*
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* The active polarity of Power Switch Logic (PSL) input is high level or
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* low-to-high transition.
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*
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* This is a component flag that should be combined with other
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* `NPCX_PSL_MODE_*` flags to produce a meaningful configuration.
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*/
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#define NPCX_PSL_ACTIVE_HIGH (1 << 2)
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/*
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* The active polarity of Power Switch Logic (PSL) input is low level or
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* high-to-low transition.
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*
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* This is a component flag that should be combined with other
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* `NPCX_PSL_MODE_*` flags to produce a meaningful configuration.
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*/
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#define NPCX_PSL_ACTIVE_LOW (1 << 3)
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/*
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* Configures Power Switch Logic (PSL) input in detecting rising edge.
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*
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* This is used for describing the 'flag' property from PSL input device with
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* 'nuvoton,npcx-pslctrl-conf' compatible.
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*/
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#define NPCX_PSL_RISING_EDGE (NPCX_PSL_MODE_EDGE | NPCX_PSL_ACTIVE_HIGH)
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/*
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* Configures Power Switch Logic (PSL) input in detecting falling edge.
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*
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* This is used for describing the 'flag' property from PSL input device with
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* 'nuvoton,npcx-pslctrl-conf' compatible.
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*/
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#define NPCX_PSL_FALLING_EDGE (NPCX_PSL_MODE_EDGE | NPCX_PSL_ACTIVE_LOW)
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/*
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* Configures Power Switch Logic (PSL) input in detecting level high state (has
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* logical value '1').
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*
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* This is used for describing the 'flag' property from PSL input device with
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* 'nuvoton,npcx-pslctrl-conf' compatible.
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*/
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#define NPCX_PSL_LEVEL_HIGH (NPCX_PSL_MODE_LEVEL | NPCX_PSL_ACTIVE_HIGH)
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/*
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* Configures Power Switch Logic (PSL) input in detecting level low state (has
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* logical value '0').
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*
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* This is used for describing the 'flag' property from PSL input device with
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* 'nuvoton,npcx-pslctrl-conf' compatible.
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*/
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#define NPCX_PSL_LEVEL_LOW (NPCX_PSL_MODE_LEVEL | NPCX_PSL_ACTIVE_LOW)
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#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NPCX_PINCTRL_H_ */
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#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_NPCX_PINCTRL_H_ */
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@ -45,10 +45,6 @@ static const struct npcx_alt def_alts[] = {
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static const struct npcx_lvol def_lvols[] = NPCX_DT_IO_LVOL_ITEMS_DEF_LIST;
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static const struct npcx_lvol def_lvols[] = NPCX_DT_IO_LVOL_ITEMS_DEF_LIST;
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#if DT_HAS_COMPAT_STATUS_OKAY(nuvoton_npcx_pslctrl_def)
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static const struct npcx_psl_in psl_in_confs[] = NPCX_DT_PSL_IN_ITEMS_LIST;
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#endif
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static const struct npcx_scfg_config npcx_scfg_cfg = {
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static const struct npcx_scfg_config npcx_scfg_cfg = {
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.base_scfg = DT_REG_ADDR_BY_NAME(DT_NODELABEL(scfg), scfg),
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.base_scfg = DT_REG_ADDR_BY_NAME(DT_NODELABEL(scfg), scfg),
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.base_glue = DT_REG_ADDR_BY_NAME(DT_NODELABEL(scfg), glue),
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.base_glue = DT_REG_ADDR_BY_NAME(DT_NODELABEL(scfg), glue),
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@ -152,59 +148,6 @@ bool npcx_pinctrl_flash_write_protect_is_set(void)
|
||||||
return IS_BIT_SET(inst_scfg->DEV_CTL4, NPCX_DEV_CTL4_WP_IF);
|
return IS_BIT_SET(inst_scfg->DEV_CTL4, NPCX_DEV_CTL4_WP_IF);
|
||||||
}
|
}
|
||||||
|
|
||||||
void npcx_pinctrl_psl_output_set_inactive(void)
|
|
||||||
{
|
|
||||||
struct gpio_reg *const inst = (struct gpio_reg *)
|
|
||||||
NPCX_DT_PSL_OUT_CONTROLLER(0);
|
|
||||||
int pin = NPCX_DT_PSL_OUT_PIN(0);
|
|
||||||
|
|
||||||
/* Set PSL_OUT to inactive level by setting related bit of PDOUT */
|
|
||||||
inst->PDOUT |= BIT(pin);
|
|
||||||
}
|
|
||||||
|
|
||||||
#if DT_HAS_COMPAT_STATUS_OKAY(nuvoton_npcx_pslctrl_def)
|
|
||||||
static void npcx_pinctrl_psl_detect_mode_sel(uint32_t offset, bool edge_mode)
|
|
||||||
{
|
|
||||||
struct glue_reg *const inst_glue = HAL_GLUE_INST();
|
|
||||||
|
|
||||||
if (edge_mode) {
|
|
||||||
inst_glue->PSL_CTS |= NPCX_PSL_CTS_MODE_BIT(offset);
|
|
||||||
} else {
|
|
||||||
inst_glue->PSL_CTS &= ~NPCX_PSL_CTS_MODE_BIT(offset);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
bool npcx_pinctrl_psl_input_asserted(uint32_t i)
|
|
||||||
{
|
|
||||||
struct glue_reg *const inst_glue = HAL_GLUE_INST();
|
|
||||||
|
|
||||||
if (i >= ARRAY_SIZE(psl_in_confs)) {
|
|
||||||
return false;
|
|
||||||
}
|
|
||||||
|
|
||||||
return IS_BIT_SET(inst_glue->PSL_CTS,
|
|
||||||
NPCX_PSL_CTS_EVENT_BIT(psl_in_confs[i].offset));
|
|
||||||
}
|
|
||||||
|
|
||||||
void npcx_pinctrl_psl_input_configure(void)
|
|
||||||
{
|
|
||||||
/* Configure detection type of PSL input pads */
|
|
||||||
for (int i = 0; i < ARRAY_SIZE(psl_in_confs); i++) {
|
|
||||||
/* Detection polarity select */
|
|
||||||
npcx_pinctrl_alt_sel(&psl_in_confs[i].polarity,
|
|
||||||
(psl_in_confs[i].flag & NPCX_PSL_ACTIVE_HIGH) != 0);
|
|
||||||
/* Detection mode select */
|
|
||||||
npcx_pinctrl_psl_detect_mode_sel(psl_in_confs[i].offset,
|
|
||||||
(psl_in_confs[i].flag & NPCX_PSL_MODE_EDGE) != 0);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Configure pin-mux for all PSL input pads from GPIO to PSL */
|
|
||||||
for (int i = 0; i < ARRAY_SIZE(psl_in_confs); i++) {
|
|
||||||
npcx_pinctrl_alt_sel(&psl_in_confs[i].pinctrl, 1);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
void npcx_host_interface_sel(enum npcx_hif_type hif_type)
|
void npcx_host_interface_sel(enum npcx_hif_type hif_type)
|
||||||
{
|
{
|
||||||
struct scfg_reg *inst_scfg = HAL_SFCG_INST();
|
struct scfg_reg *inst_scfg = HAL_SFCG_INST();
|
||||||
|
|
|
||||||
|
|
@ -402,139 +402,6 @@
|
||||||
NPCX_DT_LVOL_ITEMS_BY_IDX, (,), _) \
|
NPCX_DT_LVOL_ITEMS_BY_IDX, (,), _) \
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Get a node from path '/vsby-psl-in-list' which has a property
|
|
||||||
* 'psl-in-pads' contains Power Switch Logic (PSL) input pads which are
|
|
||||||
* in charge of detecting wake-up events on VSBY power domain.
|
|
||||||
*
|
|
||||||
* @return node identifier with that path.
|
|
||||||
*/
|
|
||||||
#define NPCX_DT_NODE_PSL_IN_LIST DT_PATH(vsby_psl_in_list)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Length of npcx_psl_in structures in 'psl-in-pads' property
|
|
||||||
*
|
|
||||||
* @return length of 'psl-in-pads' prop which type is 'phandles'
|
|
||||||
*/
|
|
||||||
#define NPCX_DT_PSL_IN_ITEMS_LEN DT_PROP_LEN(NPCX_DT_NODE_PSL_IN_LIST, \
|
|
||||||
psl_in_pads)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Get phandle from 'psl-in-pads' prop which type is 'phandles' at index
|
|
||||||
* 'i'
|
|
||||||
*
|
|
||||||
* @param i index of 'psl-in-pads' prop which type is 'phandles'
|
|
||||||
* @return phandle from 'psl-in-pads' prop at index 'i'
|
|
||||||
*/
|
|
||||||
#define NPCX_DT_PHANDLE_FROM_PSL_IN_NODE(i) \
|
|
||||||
DT_PHANDLE_BY_IDX(NPCX_DT_NODE_PSL_IN_LIST, psl_in_pads, i)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Get phandle from 'pinctrl-0' prop which type is 'phandles' at index
|
|
||||||
* 'i'
|
|
||||||
*
|
|
||||||
* @param i index of 'psl-in-pads' prop which type is 'phandles'
|
|
||||||
* @return phandle from 'pinctrl-0' prop at index 'i'
|
|
||||||
*/
|
|
||||||
#define NPCX_DT_PHANDLE_FROM_PSL_PINMUX_NODE(i) \
|
|
||||||
DT_PINCTRL_0(NPCX_DT_PHANDLE_FROM_PSL_IN_NODE(i), 0)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Get phandle from 'polarity-0' prop which type is 'phandles' at index
|
|
||||||
* 'i'
|
|
||||||
*
|
|
||||||
* @param i index of 'psl-in-pads' prop which type is 'phandles'
|
|
||||||
* @return phandle from 'polarity-0' prop at index 'i'
|
|
||||||
*/
|
|
||||||
#define NPCX_DT_PHANDLE_FROM_PSL_POLARITY_NODE(i) \
|
|
||||||
DT_PHANDLE(NPCX_DT_PHANDLE_FROM_PSL_IN_NODE(i), polarity_0)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Construct a npcx_alt structure from 'pinctrl-0' property at index 'i'
|
|
||||||
* of 'psl-in-pads' prop.
|
|
||||||
*
|
|
||||||
* @param i index of 'psl-in-pads' prop which type is 'phandles'
|
|
||||||
* @return npcx_alt item from 'pinctrl-0' property at index 'i'
|
|
||||||
*/
|
|
||||||
#define NPCX_DT_PSL_IN_ALT_CONF_BY_IDX(i) \
|
|
||||||
{ \
|
|
||||||
.group = DT_PHA(NPCX_DT_PHANDLE_FROM_PSL_PINMUX_NODE(i), alts, group), \
|
|
||||||
.bit = DT_PHA(NPCX_DT_PHANDLE_FROM_PSL_PINMUX_NODE(i), alts, bit), \
|
|
||||||
.inverted = DT_PHA(NPCX_DT_PHANDLE_FROM_PSL_PINMUX_NODE(i), alts, inv), \
|
|
||||||
},
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Construct a npcx_alt structure from 'polarity-0' property at index 'i'
|
|
||||||
* of 'psl-in-pads' prop.
|
|
||||||
*
|
|
||||||
* @param i index of 'psl-in-pads' prop which type is 'phandles'
|
|
||||||
* @return npcx_alt item from 'pinctrl-0' property at index 'i'
|
|
||||||
*/
|
|
||||||
#define NPCX_DT_PSL_IN_POL_CONF_BY_IDX(i) \
|
|
||||||
{ \
|
|
||||||
.group = DT_PHA(NPCX_DT_PHANDLE_FROM_PSL_POLARITY_NODE(i), alts, group), \
|
|
||||||
.bit = DT_PHA(NPCX_DT_PHANDLE_FROM_PSL_POLARITY_NODE(i), alts, bit), \
|
|
||||||
.inverted = DT_PHA(NPCX_DT_PHANDLE_FROM_PSL_POLARITY_NODE(i), alts, inv), \
|
|
||||||
},
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Construct a npcx_psl_in structure from 'psl-in-pads' property at index
|
|
||||||
* 'i'
|
|
||||||
*
|
|
||||||
* @param i index of 'psl-in-pads' prop which type is 'phandles'
|
|
||||||
* @return npcx_psl_in item from 'psl-in-pads' property at index 'i'
|
|
||||||
*/
|
|
||||||
#define NPCX_DT_PSL_IN_ITEMS_BY_IDX(i, _) \
|
|
||||||
{ \
|
|
||||||
.flag = DT_PROP(NPCX_DT_PHANDLE_FROM_PSL_IN_NODE(i), flag), \
|
|
||||||
.offset = DT_PROP(NPCX_DT_PHANDLE_FROM_PSL_IN_NODE(i), offset),\
|
|
||||||
.pinctrl = NPCX_DT_PSL_IN_ALT_CONF_BY_IDX(i) \
|
|
||||||
.polarity = NPCX_DT_PSL_IN_POL_CONF_BY_IDX(i) \
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Macro function to construct a list of npcx_psl_in items by
|
|
||||||
* UTIL_LISTIFY func.
|
|
||||||
*
|
|
||||||
* Example devicetree fragment:
|
|
||||||
* / {
|
|
||||||
* vsby-psl-in-list {
|
|
||||||
* psl-in-pads = <&psl_in1>;
|
|
||||||
* };
|
|
||||||
* };
|
|
||||||
* &psl_in1 {
|
|
||||||
* flag = <NPCX_PSL_FALLING_EDGE>;
|
|
||||||
* };
|
|
||||||
*
|
|
||||||
* Example usage:
|
|
||||||
* static const struct npcx_psl_in psl_in_confs[] = NPCX_DT_PSL_IN_ITEMS_LIST;
|
|
||||||
*
|
|
||||||
* @return an array of npcx_psl_in items which configures PSL input pads
|
|
||||||
*/
|
|
||||||
#define NPCX_DT_PSL_IN_ITEMS_LIST { \
|
|
||||||
LISTIFY(NPCX_DT_PSL_IN_ITEMS_LEN, \
|
|
||||||
NPCX_DT_PSL_IN_ITEMS_BY_IDX, (,), _) \
|
|
||||||
}
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Get base address of corresponding GPIO controller for enabling PSL
|
|
||||||
* output.
|
|
||||||
*
|
|
||||||
* @param @param inst number for devices with compatible 'nuvoton_npcx_psl_out'.
|
|
||||||
* @return base address of corresponding GPIO controller
|
|
||||||
*/
|
|
||||||
#define NPCX_DT_PSL_OUT_CONTROLLER(inst) DT_REG_ADDR_BY_IDX(DT_PHANDLE_BY_IDX( \
|
|
||||||
DT_INST(inst, nuvoton_npcx_psl_out), controller, 0), 0)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Get pin of corresponding GPIO controller for enabling PSL output.
|
|
||||||
*
|
|
||||||
* @param @param inst number for devices with compatible 'nuvoton_npcx_psl_out'.
|
|
||||||
* @return pin of corresponding GPIO controller.
|
|
||||||
*/
|
|
||||||
#define NPCX_DT_PSL_OUT_PIN(inst) DT_PROP(DT_INST(inst, nuvoton_npcx_psl_out), \
|
|
||||||
pin)
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Check if the host interface type is automatically configured by
|
* @brief Check if the host interface type is automatically configured by
|
||||||
* booter.
|
* booter.
|
||||||
|
|
|
||||||
|
|
@ -41,27 +41,6 @@ struct npcx_lvol {
|
||||||
uint16_t bit:3; /** Related register bit for low-voltage conf. */
|
uint16_t bit:3; /** Related register bit for low-voltage conf. */
|
||||||
};
|
};
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief NPCX Power Switch Logic (PSL) input configuration structure
|
|
||||||
*
|
|
||||||
* Used to configure PSL input pad which detect the wake-up events and switch
|
|
||||||
* core power supply (VCC1) on from standby power state (ultra-low-power mode).
|
|
||||||
*/
|
|
||||||
struct npcx_psl_in {
|
|
||||||
/** flag to indicate the detection mode and type. */
|
|
||||||
uint32_t flag;
|
|
||||||
/** offset in PSL_CTS for status and detection mode. */
|
|
||||||
uint32_t offset;
|
|
||||||
/** Device Alternate Function. (DEVALT) register/bit for PSL pin-muxing.
|
|
||||||
* It determines whether PSL input or GPIO selected to the pad.
|
|
||||||
*/
|
|
||||||
struct npcx_alt pinctrl;
|
|
||||||
/** Device Alternate Function. (DEVALT) register/bit for PSL polarity.
|
|
||||||
* It determines active polarity of wake-up signal via PSL input.
|
|
||||||
*/
|
|
||||||
struct npcx_alt polarity;
|
|
||||||
};
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Select i2c port pads of i2c controller
|
* @brief Select i2c port pads of i2c controller
|
||||||
*
|
*
|
||||||
|
|
@ -83,34 +62,6 @@ int npcx_pinctrl_flash_write_protect_set(void);
|
||||||
*/
|
*/
|
||||||
bool npcx_pinctrl_flash_write_protect_is_set(void);
|
bool npcx_pinctrl_flash_write_protect_is_set(void);
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Set PSL output pad to inactive level.
|
|
||||||
*
|
|
||||||
* The PSL_OUT output pad should be connected to the control pin of either the
|
|
||||||
* switch or the power supply used generate the VCC1 power from the VSBY power.
|
|
||||||
* When PSL_OUT is high (active), the Core Domain power supply (VCC1) is turned
|
|
||||||
* on. When PSL_OUT is low (inactive) by setting bit of related PDOUT, VCC1 is
|
|
||||||
* turned off for entering standby power state (ultra-low-power mode).
|
|
||||||
*/
|
|
||||||
void npcx_pinctrl_psl_output_set_inactive(void);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Configure PSL input pads in psl_in_pads list
|
|
||||||
*
|
|
||||||
* Used to configure PSL input pads list from "psl-in-pads" property which
|
|
||||||
* detect the wake-up events and the related circuit will turn on core power
|
|
||||||
* supply (VCC1) from standby power state (ultra-low-power mode) later.
|
|
||||||
*/
|
|
||||||
void npcx_pinctrl_psl_input_configure(void);
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Get the asserted status of PSL input pads
|
|
||||||
*
|
|
||||||
* @param i index of 'psl-in-pads' prop
|
|
||||||
* @return 1 is asserted, otherwise de-asserted.
|
|
||||||
*/
|
|
||||||
bool npcx_pinctrl_psl_input_asserted(uint32_t i);
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Restore all connections between IO pads that support low-voltage power
|
* @brief Restore all connections between IO pads that support low-voltage power
|
||||||
* supply and GPIO hardware devices. This utility is used for solving a
|
* supply and GPIO hardware devices. This utility is used for solving a
|
||||||
|
|
|
||||||
Loading…
Add table
Add a link
Reference in a new issue