stm32f4: Clean references to stm32f4 specific clock control
Following activation of stm32 common clock driver for stm32f4 series remove references to stm32f4 specific driver. Change-Id: I372a0ea046007bcb34944d6b2b8880077583b1d3 Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou
Kumar Gala
parent
80b7bec12c
commit
242ed389a3
22 changed files with 13 additions and 1076 deletions
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@ -42,9 +42,6 @@ endif #SERIAL
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if CLOCK_CONTROL
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config CLOCK_CONTROL_STM32F4X
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def_bool n
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config CLOCK_CONTROL_STM32_CUBE
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def_bool y
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@ -15,15 +15,6 @@
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* Chapter 3.4: Embedded Flash Memory
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*/
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enum {
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STM32F4X_FLASH_LATENCY_0 = 0x0,
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STM32F4X_FLASH_LATENCY_1 = 0x1,
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STM32F4X_FLASH_LATENCY_2 = 0x2,
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STM32F4X_FLASH_LATENCY_3 = 0x3,
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STM32F4X_FLASH_LATENCY_4 = 0x4,
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STM32F4X_FLASH_LATENCY_5 = 0x5,
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};
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union __flash_acr {
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u32_t val;
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struct {
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@ -48,102 +39,4 @@ struct stm32f4x_flash {
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volatile u32_t optctrl;
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};
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/**
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* @brief setup embedded flash controller
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*
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* Configure flash access time latency (wait states) depending on
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* SYSCLK. This code assumes that we're using a supply voltage of
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* 2.7V or higher, for lower voltages this code must be changed.
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*
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* The following tables show the required latency value required for a
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* certain CPU frequency (HCLK) and supply voltage. See the section
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* "Relation between CPU clock frequency and Flash memory read time"
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* in the reference manual for more information.
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*
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* Note that the highest frequency might be limited for other reaasons
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* than wait states, for example the STM32F405xx is limited to 168MHz
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* even with 5 wait states and the highest supply voltage.
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*
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* STM32F401xx:
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*
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* LATENCY | 2.7V - 3.6V | 2.4V - 2.7V | 2.1V - 2.4V | 1.8V - 2.1V
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* ------- | ----------- | ----------- | ----------- | -----------
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* 0 | 30 MHz | 24 MHz | 18 MHz | 16 MHz
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* 1 | 60 MHz | 48 MHz | 36 MHz | 32 MHz
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* 2 | 84 MHz | 72 MHz | 54 MHz | 48 MHz
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* 3 | | 84 MHz | 72 MHz | 64 MHz
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* 4 | | | 84 MHz | 80 MHz
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* 5 | | | | 84 MHz
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*
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* STM32F405xx/407xx/415xx/417xx/42xxx/43xxx:
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*
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* LATENCY | 2.7V - 3.6V | 2.4V - 2.7V | 2.1V - 2.4V | 1.8V - 2.1V
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* ------- | ----------- | ----------- | ----------- | -----------
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* 0 | 30 MHz | 24 MHz | 22 MHz | 20 MHz
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* 1 | 60 MHz | 48 MHz | 44 MHz | 40 MHz
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* 2 | 90 MHz | 72 MHz | 66 MHz | 60 MHz
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* 3 | 120 MHz | 96 MHz | 88 MHz | 80 MHz
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* 4 | 150 MHz | 120 MHz | 110 MHz | 100 MHz
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* 5 | 180 MHz | 144 MHz | 132 MHz | 120 MHz
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* 6 | | 168 MHz | 154 MHz | 140 MHz
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* 7 | | 180 MHz | 176 MHz | 160 MHz
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* 8 | | | 180 MHz | 168 MHz
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*
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* STM32F411x:
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*
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* LATENCY | 2.7V - 3.6V | 2.4V - 2.7V | 2.1V - 2.4V | 1.7V - 2.1V
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* ------- | ----------- | ----------- | ----------- | -----------
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* 0 | 30 MHz | 24 MHz | 18 MHz | 16 MHz
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* 1 | 64 MHz | 48 MHz | 36 MHz | 32 MHz
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* 2 | 90 MHz | 72 MHz | 54 MHz | 48 MHz
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* 3 | 100 MHz | 96 MHz | 72 MHz | 64 MHz
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* 4 | | 100 MHz | 90 MHz | 80 MHz
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* 5 | | | 100 MHz | 96 MHz
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* 6 | | | | 100 MHz
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*/
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static inline void __setup_flash(void)
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{
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volatile struct stm32f4x_flash *regs;
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u32_t tmpreg = 0;
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regs = (struct stm32f4x_flash *) FLASH_R_BASE;
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if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 30000000) {
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regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_0;
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}
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#ifdef CONFIG_SOC_STM32F401XE
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else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 60000000) {
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regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_1;
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} else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 84000000) {
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regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_2;
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}
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#elif CONFIG_SOC_STM32F411XE
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else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 64000000) {
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regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_1;
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} else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 90000000) {
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regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_2;
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} else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 100000000) {
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regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_3;
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}
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#elif defined(CONFIG_SOC_STM32F407XX) || defined(CONFIG_SOC_STM32F429XX)
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else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 60000000) {
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regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_1;
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} else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 90000000) {
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regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_2;
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} else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 120000000) {
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regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_3;
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} else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 150000000) {
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regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_4;
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} else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 180000000) {
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regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_5;
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}
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#else
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#error Flash latency configuration for MCU model is missing
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#endif
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/* Make sure latency was set */
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tmpreg = regs->acr.bit.latency;
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}
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#endif /* _STM32F4X_FLASHREGISTERS_H_ */
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@ -1,159 +0,0 @@
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/*
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* Copyright (c) 2016 Linaro Limited.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _STM32F4X_CLOCK_H_
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#define _STM32F4X_CLOCK_H_
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/**
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* @brief Driver for Reset & Clock Control of STM32F4X family processor.
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*
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* Based on reference manual:
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* RM0368 Reference manual STM32F401xB/C and STM32F401xD/E
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* advanced ARM ® -based 32-bit MCUs
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*
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* Chapter 6. Reset and Clock control (RCC) for STM43F401xB/C and STM32F401xD/E
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*/
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/* 6.3.1 Clock control register (RCC_CR) */
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enum {
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STM32F4X_RCC_CFG_PLL_SRC_HSI = 0x0,
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STM32F4X_RCC_CFG_PLL_SRC_HSE = 0x1,
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};
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enum {
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STM32F4X_RCC_CFG_SYSCLK_SRC_HSI = 0x0,
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STM32F4X_RCC_CFG_SYSCLK_SRC_HSE = 0x1,
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STM32F4X_RCC_CFG_SYSCLK_SRC_PLL = 0x2,
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};
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enum {
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STM32F4X_RCC_CFG_PLLP_DIV_2 = 0x0,
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STM32F4X_RCC_CFG_PLLP_DIV_4 = 0x1,
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STM32F4X_RCC_CFG_PLLP_DIV_6 = 0x2,
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STM32F4X_RCC_CFG_PLLP_DIV_8 = 0x3,
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};
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enum {
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STM32F4X_RCC_CFG_HCLK_DIV_0 = 0x0,
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STM32F4X_RCC_CFG_HCLK_DIV_2 = 0x4,
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STM32F4X_RCC_CFG_HCLK_DIV_4 = 0x5,
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STM32F4X_RCC_CFG_HCLK_DIV_8 = 0x6,
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STM32F4X_RCC_CFG_HCLK_DIV_16 = 0x7,
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};
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enum {
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STM32F4X_RCC_CFG_SYSCLK_DIV_0 = 0x0,
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STM32F4X_RCC_CFG_SYSCLK_DIV_2 = 0x8,
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STM32F4X_RCC_CFG_SYSCLK_DIV_4 = 0x9,
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STM32F4X_RCC_CFG_SYSCLK_DIV_8 = 0xa,
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STM32F4X_RCC_CFG_SYSCLK_DIV_16 = 0xb,
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STM32F4X_RCC_CFG_SYSCLK_DIV_64 = 0xc,
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STM32F4X_RCC_CFG_SYSCLK_DIV_128 = 0xd,
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STM32F4X_RCC_CFG_SYSCLK_DIV_256 = 0xe,
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STM32F4X_RCC_CFG_SYSCLK_DIV_512 = 0xf,
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};
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/**
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* @brief Reset and Clock Control
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*/
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/* Helpers */
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enum {
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STM32F4X_RCC_APB1ENR_PWREN = 0x10000000U,
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};
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union __rcc_cr {
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u32_t val;
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struct {
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u32_t hsion :1 __packed;
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u32_t hsirdy :1 __packed;
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u32_t rsvd__2 :1 __packed;
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u32_t hsitrim :5 __packed;
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u32_t hsical :8 __packed;
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u32_t hseon :1 __packed;
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u32_t hserdy :1 __packed;
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u32_t hsebyp :1 __packed;
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u32_t csson :1 __packed;
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u32_t rsvd__20_23 :4 __packed;
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u32_t pllon :1 __packed;
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u32_t pllrdy :1 __packed;
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u32_t plli2son :1 __packed;
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u32_t plli2srdy :1 __packed;
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u32_t pllsaion :1 __packed;
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u32_t pllsairdy :1 __packed;
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u32_t rsvd__30_31 :2 __packed;
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} bit;
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};
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union __rcc_pllcfgr {
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u32_t val;
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struct {
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u32_t pllm :6 __packed;
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u32_t plln :9 __packed;
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u32_t rsvd__15 :1 __packed;
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u32_t pllp :2 __packed;
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u32_t rsvd__18_21 :4 __packed;
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u32_t pllsrc :1 __packed;
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u32_t rsvd__23 :1 __packed;
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u32_t pllq :4 __packed;
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u32_t rsvd__28_31 :4 __packed;
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} bit;
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};
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union __rcc_cfgr {
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u32_t val;
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struct {
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u32_t sw :2 __packed;
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u32_t sws :2 __packed;
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u32_t hpre :4 __packed;
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u32_t rsvd__8_9 :2 __packed;
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u32_t ppre1 :3 __packed;
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u32_t ppre2 :3 __packed;
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u32_t rtcpre :5 __packed;
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u32_t mco1 :2 __packed;
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u32_t i2sscr :1 __packed;
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u32_t mco1pre :3 __packed;
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u32_t mco2pre :3 __packed;
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u32_t mco2 :2 __packed;
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} bit;
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};
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struct stm32f4x_rcc {
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union __rcc_cr cr;
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union __rcc_pllcfgr pllcfgr;
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union __rcc_cfgr cfgr;
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u32_t cir;
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u32_t ahb1rstr;
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u32_t ahb2rstr;
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u32_t ahb3rstr;
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u32_t rsvd0;
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u32_t apb1rstr;
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u32_t apb2rstr;
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u32_t rsvd1[2];
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u32_t ahb1enr;
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u32_t ahb2enr;
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u32_t ahb3enr;
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u32_t rsvd2;
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u32_t apb1enr;
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u32_t apb2enr;
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u32_t rsvd3[2];
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u32_t ahb1lpenr;
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u32_t ahb2lpenr;
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u32_t ahb3lpenr;
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u32_t rsvd4;
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u32_t apb1lpenr;
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u32_t apb2lpenr;
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u32_t rsvd5[2];
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u32_t bdcr;
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u32_t csr;
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u32_t rsvd6[2];
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u32_t sscgr;
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u32_t plli2scfgr;
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u32_t rsvd7;
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u32_t dckcfgr;
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};
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#endif /* _STM32F4X_CLOCK_H_ */
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@ -234,17 +234,10 @@ int stm32_gpio_enable_int(int port, int pin)
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(struct stm32f4x_syscfg *)SYSCFG_BASE;
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volatile union syscfg_exticr *exticr;
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struct device *clk = device_get_binding(STM32_CLOCK_CONTROL_NAME);
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#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE
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struct stm32_pclken pclken = {
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.bus = STM32_CLOCK_BUS_APB2,
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.enr = LL_APB2_GRP1_PERIPH_SYSCFG
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};
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#else
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struct stm32f4x_pclken pclken = {
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.bus = STM32F4X_CLOCK_BUS_APB2,
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.enr = STM32F4X_CLOCK_ENABLE_SYSCFG
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};
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#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */
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int shift = 0;
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/* Enable SYSCFG clock */
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@ -8,7 +8,6 @@
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#define _STM32F4_SOC_REGISTERS_H_
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/* include register mapping headers */
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#include "rcc_registers.h"
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#include "flash_registers.h"
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#include "gpio_registers.h"
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