From 242ed389a3e125b1ba6adb5807cacb0c50638e25 Mon Sep 17 00:00:00 2001 From: Erwan Gouriou Date: Tue, 11 Apr 2017 11:03:32 +0200 Subject: [PATCH] stm32f4: Clean references to stm32f4 specific clock control Following activation of stm32 common clock driver for stm32f4 series remove references to stm32f4 specific driver. Change-Id: I372a0ea046007bcb34944d6b2b8880077583b1d3 Signed-off-by: Erwan Gouriou --- .../st_stm32/stm32f4/Kconfig.defconfig.series | 3 - .../soc/st_stm32/stm32f4/flash_registers.h | 107 ------ arch/arm/soc/st_stm32/stm32f4/rcc_registers.h | 159 -------- arch/arm/soc/st_stm32/stm32f4/soc_gpio.c | 7 - arch/arm/soc/st_stm32/stm32f4/soc_registers.h | 1 - boards/arm/96b_carbon/96b_carbon_defconfig | 12 - .../arm/nucleo_f401re/nucleo_f401re_defconfig | 14 - .../arm/nucleo_f411re/nucleo_f411re_defconfig | 14 - drivers/clock_control/Kconfig | 2 - drivers/clock_control/Kconfig.stm32f4x | 141 ------- drivers/clock_control/Makefile | 1 - drivers/clock_control/stm32f4x_clock.c | 350 ------------------ drivers/dma/dma_stm32f4x.c | 14 - drivers/gpio/gpio_stm32.c | 35 +- drivers/gpio/gpio_stm32.h | 4 +- drivers/pinmux/stm32/pinmux_stm32.c | 21 +- drivers/pwm/pwm_stm32.c | 43 +-- drivers/pwm/pwm_stm32.h | 4 - drivers/serial/uart_stm32.c | 17 +- drivers/serial/uart_stm32.h | 4 - .../clock_control/stm32_clock_control.h | 2 - .../clock_control/stm32f4_clock_control.h | 134 ------- 22 files changed, 13 insertions(+), 1076 deletions(-) delete mode 100644 arch/arm/soc/st_stm32/stm32f4/rcc_registers.h delete mode 100644 drivers/clock_control/Kconfig.stm32f4x delete mode 100644 drivers/clock_control/stm32f4x_clock.c delete mode 100644 include/drivers/clock_control/stm32f4_clock_control.h diff --git a/arch/arm/soc/st_stm32/stm32f4/Kconfig.defconfig.series b/arch/arm/soc/st_stm32/stm32f4/Kconfig.defconfig.series index f9727327b35..cc581d52069 100644 --- a/arch/arm/soc/st_stm32/stm32f4/Kconfig.defconfig.series +++ b/arch/arm/soc/st_stm32/stm32f4/Kconfig.defconfig.series @@ -42,9 +42,6 @@ endif #SERIAL if CLOCK_CONTROL -config CLOCK_CONTROL_STM32F4X - def_bool n - config CLOCK_CONTROL_STM32_CUBE def_bool y diff --git a/arch/arm/soc/st_stm32/stm32f4/flash_registers.h b/arch/arm/soc/st_stm32/stm32f4/flash_registers.h index 8b9ae4e7b70..67c88734841 100644 --- a/arch/arm/soc/st_stm32/stm32f4/flash_registers.h +++ b/arch/arm/soc/st_stm32/stm32f4/flash_registers.h @@ -15,15 +15,6 @@ * Chapter 3.4: Embedded Flash Memory */ -enum { - STM32F4X_FLASH_LATENCY_0 = 0x0, - STM32F4X_FLASH_LATENCY_1 = 0x1, - STM32F4X_FLASH_LATENCY_2 = 0x2, - STM32F4X_FLASH_LATENCY_3 = 0x3, - STM32F4X_FLASH_LATENCY_4 = 0x4, - STM32F4X_FLASH_LATENCY_5 = 0x5, -}; - union __flash_acr { u32_t val; struct { @@ -48,102 +39,4 @@ struct stm32f4x_flash { volatile u32_t optctrl; }; -/** - * @brief setup embedded flash controller - * - * Configure flash access time latency (wait states) depending on - * SYSCLK. This code assumes that we're using a supply voltage of - * 2.7V or higher, for lower voltages this code must be changed. - * - * The following tables show the required latency value required for a - * certain CPU frequency (HCLK) and supply voltage. See the section - * "Relation between CPU clock frequency and Flash memory read time" - * in the reference manual for more information. - * - * Note that the highest frequency might be limited for other reaasons - * than wait states, for example the STM32F405xx is limited to 168MHz - * even with 5 wait states and the highest supply voltage. - * - * STM32F401xx: - * - * LATENCY | 2.7V - 3.6V | 2.4V - 2.7V | 2.1V - 2.4V | 1.8V - 2.1V - * ------- | ----------- | ----------- | ----------- | ----------- - * 0 | 30 MHz | 24 MHz | 18 MHz | 16 MHz - * 1 | 60 MHz | 48 MHz | 36 MHz | 32 MHz - * 2 | 84 MHz | 72 MHz | 54 MHz | 48 MHz - * 3 | | 84 MHz | 72 MHz | 64 MHz - * 4 | | | 84 MHz | 80 MHz - * 5 | | | | 84 MHz - * - * STM32F405xx/407xx/415xx/417xx/42xxx/43xxx: - * - * LATENCY | 2.7V - 3.6V | 2.4V - 2.7V | 2.1V - 2.4V | 1.8V - 2.1V - * ------- | ----------- | ----------- | ----------- | ----------- - * 0 | 30 MHz | 24 MHz | 22 MHz | 20 MHz - * 1 | 60 MHz | 48 MHz | 44 MHz | 40 MHz - * 2 | 90 MHz | 72 MHz | 66 MHz | 60 MHz - * 3 | 120 MHz | 96 MHz | 88 MHz | 80 MHz - * 4 | 150 MHz | 120 MHz | 110 MHz | 100 MHz - * 5 | 180 MHz | 144 MHz | 132 MHz | 120 MHz - * 6 | | 168 MHz | 154 MHz | 140 MHz - * 7 | | 180 MHz | 176 MHz | 160 MHz - * 8 | | | 180 MHz | 168 MHz - * - * STM32F411x: - * - * LATENCY | 2.7V - 3.6V | 2.4V - 2.7V | 2.1V - 2.4V | 1.7V - 2.1V - * ------- | ----------- | ----------- | ----------- | ----------- - * 0 | 30 MHz | 24 MHz | 18 MHz | 16 MHz - * 1 | 64 MHz | 48 MHz | 36 MHz | 32 MHz - * 2 | 90 MHz | 72 MHz | 54 MHz | 48 MHz - * 3 | 100 MHz | 96 MHz | 72 MHz | 64 MHz - * 4 | | 100 MHz | 90 MHz | 80 MHz - * 5 | | | 100 MHz | 96 MHz - * 6 | | | | 100 MHz - */ -static inline void __setup_flash(void) -{ - volatile struct stm32f4x_flash *regs; - u32_t tmpreg = 0; - - regs = (struct stm32f4x_flash *) FLASH_R_BASE; - - if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 30000000) { - regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_0; - } -#ifdef CONFIG_SOC_STM32F401XE - else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 60000000) { - regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_1; - } else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 84000000) { - regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_2; - } -#elif CONFIG_SOC_STM32F411XE - else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 64000000) { - regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_1; - } else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 90000000) { - regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_2; - } else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 100000000) { - regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_3; - } -#elif defined(CONFIG_SOC_STM32F407XX) || defined(CONFIG_SOC_STM32F429XX) - else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 60000000) { - regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_1; - } else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 90000000) { - regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_2; - } else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 120000000) { - regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_3; - } else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 150000000) { - regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_4; - } else if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC <= 180000000) { - regs->acr.bit.latency = STM32F4X_FLASH_LATENCY_5; - } -#else -#error Flash latency configuration for MCU model is missing -#endif - - /* Make sure latency was set */ - tmpreg = regs->acr.bit.latency; - -} - #endif /* _STM32F4X_FLASHREGISTERS_H_ */ diff --git a/arch/arm/soc/st_stm32/stm32f4/rcc_registers.h b/arch/arm/soc/st_stm32/stm32f4/rcc_registers.h deleted file mode 100644 index 6cd0a97bf4f..00000000000 --- a/arch/arm/soc/st_stm32/stm32f4/rcc_registers.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - * Copyright (c) 2016 Linaro Limited. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _STM32F4X_CLOCK_H_ -#define _STM32F4X_CLOCK_H_ - -/** - * @brief Driver for Reset & Clock Control of STM32F4X family processor. - * - * Based on reference manual: - * RM0368 Reference manual STM32F401xB/C and STM32F401xD/E - * advanced ARM ® -based 32-bit MCUs - * - * Chapter 6. Reset and Clock control (RCC) for STM43F401xB/C and STM32F401xD/E - */ - -/* 6.3.1 Clock control register (RCC_CR) */ -enum { - STM32F4X_RCC_CFG_PLL_SRC_HSI = 0x0, - STM32F4X_RCC_CFG_PLL_SRC_HSE = 0x1, -}; - -enum { - STM32F4X_RCC_CFG_SYSCLK_SRC_HSI = 0x0, - STM32F4X_RCC_CFG_SYSCLK_SRC_HSE = 0x1, - STM32F4X_RCC_CFG_SYSCLK_SRC_PLL = 0x2, -}; - -enum { - STM32F4X_RCC_CFG_PLLP_DIV_2 = 0x0, - STM32F4X_RCC_CFG_PLLP_DIV_4 = 0x1, - STM32F4X_RCC_CFG_PLLP_DIV_6 = 0x2, - STM32F4X_RCC_CFG_PLLP_DIV_8 = 0x3, -}; - -enum { - STM32F4X_RCC_CFG_HCLK_DIV_0 = 0x0, - STM32F4X_RCC_CFG_HCLK_DIV_2 = 0x4, - STM32F4X_RCC_CFG_HCLK_DIV_4 = 0x5, - STM32F4X_RCC_CFG_HCLK_DIV_8 = 0x6, - STM32F4X_RCC_CFG_HCLK_DIV_16 = 0x7, -}; - -enum { - STM32F4X_RCC_CFG_SYSCLK_DIV_0 = 0x0, - STM32F4X_RCC_CFG_SYSCLK_DIV_2 = 0x8, - STM32F4X_RCC_CFG_SYSCLK_DIV_4 = 0x9, - STM32F4X_RCC_CFG_SYSCLK_DIV_8 = 0xa, - STM32F4X_RCC_CFG_SYSCLK_DIV_16 = 0xb, - STM32F4X_RCC_CFG_SYSCLK_DIV_64 = 0xc, - STM32F4X_RCC_CFG_SYSCLK_DIV_128 = 0xd, - STM32F4X_RCC_CFG_SYSCLK_DIV_256 = 0xe, - STM32F4X_RCC_CFG_SYSCLK_DIV_512 = 0xf, -}; - -/** - * @brief Reset and Clock Control - */ - -/* Helpers */ -enum { - STM32F4X_RCC_APB1ENR_PWREN = 0x10000000U, -}; - -union __rcc_cr { - u32_t val; - struct { - u32_t hsion :1 __packed; - u32_t hsirdy :1 __packed; - u32_t rsvd__2 :1 __packed; - u32_t hsitrim :5 __packed; - u32_t hsical :8 __packed; - u32_t hseon :1 __packed; - u32_t hserdy :1 __packed; - u32_t hsebyp :1 __packed; - u32_t csson :1 __packed; - u32_t rsvd__20_23 :4 __packed; - u32_t pllon :1 __packed; - u32_t pllrdy :1 __packed; - u32_t plli2son :1 __packed; - u32_t plli2srdy :1 __packed; - u32_t pllsaion :1 __packed; - u32_t pllsairdy :1 __packed; - u32_t rsvd__30_31 :2 __packed; - } bit; -}; - -union __rcc_pllcfgr { - u32_t val; - struct { - u32_t pllm :6 __packed; - u32_t plln :9 __packed; - u32_t rsvd__15 :1 __packed; - u32_t pllp :2 __packed; - u32_t rsvd__18_21 :4 __packed; - u32_t pllsrc :1 __packed; - u32_t rsvd__23 :1 __packed; - u32_t pllq :4 __packed; - u32_t rsvd__28_31 :4 __packed; - } bit; -}; - -union __rcc_cfgr { - u32_t val; - struct { - u32_t sw :2 __packed; - u32_t sws :2 __packed; - u32_t hpre :4 __packed; - u32_t rsvd__8_9 :2 __packed; - u32_t ppre1 :3 __packed; - u32_t ppre2 :3 __packed; - u32_t rtcpre :5 __packed; - u32_t mco1 :2 __packed; - u32_t i2sscr :1 __packed; - u32_t mco1pre :3 __packed; - u32_t mco2pre :3 __packed; - u32_t mco2 :2 __packed; - } bit; -}; - -struct stm32f4x_rcc { - union __rcc_cr cr; - union __rcc_pllcfgr pllcfgr; - union __rcc_cfgr cfgr; - u32_t cir; - u32_t ahb1rstr; - u32_t ahb2rstr; - u32_t ahb3rstr; - u32_t rsvd0; - u32_t apb1rstr; - u32_t apb2rstr; - u32_t rsvd1[2]; - u32_t ahb1enr; - u32_t ahb2enr; - u32_t ahb3enr; - u32_t rsvd2; - u32_t apb1enr; - u32_t apb2enr; - u32_t rsvd3[2]; - u32_t ahb1lpenr; - u32_t ahb2lpenr; - u32_t ahb3lpenr; - u32_t rsvd4; - u32_t apb1lpenr; - u32_t apb2lpenr; - u32_t rsvd5[2]; - u32_t bdcr; - u32_t csr; - u32_t rsvd6[2]; - u32_t sscgr; - u32_t plli2scfgr; - u32_t rsvd7; - u32_t dckcfgr; -}; - -#endif /* _STM32F4X_CLOCK_H_ */ diff --git a/arch/arm/soc/st_stm32/stm32f4/soc_gpio.c b/arch/arm/soc/st_stm32/stm32f4/soc_gpio.c index 44098169d44..8a0bd865bef 100644 --- a/arch/arm/soc/st_stm32/stm32f4/soc_gpio.c +++ b/arch/arm/soc/st_stm32/stm32f4/soc_gpio.c @@ -234,17 +234,10 @@ int stm32_gpio_enable_int(int port, int pin) (struct stm32f4x_syscfg *)SYSCFG_BASE; volatile union syscfg_exticr *exticr; struct device *clk = device_get_binding(STM32_CLOCK_CONTROL_NAME); -#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE struct stm32_pclken pclken = { .bus = STM32_CLOCK_BUS_APB2, .enr = LL_APB2_GRP1_PERIPH_SYSCFG }; -#else - struct stm32f4x_pclken pclken = { - .bus = STM32F4X_CLOCK_BUS_APB2, - .enr = STM32F4X_CLOCK_ENABLE_SYSCFG - }; -#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */ int shift = 0; /* Enable SYSCFG clock */ diff --git a/arch/arm/soc/st_stm32/stm32f4/soc_registers.h b/arch/arm/soc/st_stm32/stm32f4/soc_registers.h index 1ad979890b7..c7a2d5cb799 100644 --- a/arch/arm/soc/st_stm32/stm32f4/soc_registers.h +++ b/arch/arm/soc/st_stm32/stm32f4/soc_registers.h @@ -8,7 +8,6 @@ #define _STM32F4_SOC_REGISTERS_H_ /* include register mapping headers */ -#include "rcc_registers.h" #include "flash_registers.h" #include "gpio_registers.h" diff --git a/boards/arm/96b_carbon/96b_carbon_defconfig b/boards/arm/96b_carbon/96b_carbon_defconfig index 26f43e1bc68..4a4a660c98e 100644 --- a/boards/arm/96b_carbon/96b_carbon_defconfig +++ b/boards/arm/96b_carbon/96b_carbon_defconfig @@ -23,18 +23,6 @@ CONFIG_GPIO_STM32_PORTD=y # clock configuration CONFIG_CLOCK_CONTROL=y -CONFIG_CLOCK_STM32F4X_SYSCLK_SRC_PLL=y -# use HSE as PLL input -CONFIG_CLOCK_STM32F4X_PLL_SRC_HSE=y -# CONFIG_CLOCK_STM32F4X_HSE_BYPASS=y -# produce 84MHz clock at PLL output -CONFIG_CLOCK_STM32F4X_PLLM_DIV_FACTOR=16 -CONFIG_CLOCK_STM32F4X_PLLN_MULTIPLIER=336 -CONFIG_CLOCK_STM32F4X_PLLP_DIV_FACTOR=4 -CONFIG_CLOCK_STM32F4X_PLLQ_DIV_FACTOR=7 -CONFIG_CLOCK_STM32F4X_AHB_PRESCALER=0 -CONFIG_CLOCK_STM32F4X_APB1_PRESCALER=2 -CONFIG_CLOCK_STM32F4X_APB2_PRESCALER=0 # Clock configuration for Cube Clock control driver CONFIG_CLOCK_STM32_HSE_CLOCK=16000000 diff --git a/boards/arm/nucleo_f401re/nucleo_f401re_defconfig b/boards/arm/nucleo_f401re/nucleo_f401re_defconfig index fa2bc5e3c94..d699e082a2a 100644 --- a/boards/arm/nucleo_f401re/nucleo_f401re_defconfig +++ b/boards/arm/nucleo_f401re/nucleo_f401re_defconfig @@ -22,20 +22,6 @@ CONFIG_GPIO=y # clock configuration CONFIG_CLOCK_CONTROL=y -CONFIG_CLOCK_STM32F4X_SYSCLK_SRC_PLL=y -# use HSE as PLL input -CONFIG_CLOCK_STM32F4X_PLL_SRC_HSE=y -# however, the board does not have an external oscillator, so just use -# the 8MHz clock signal coming from integrated STLink -CONFIG_CLOCK_STM32F4X_HSE_BYPASS=y -# produce 84MHz clock at PLL output -CONFIG_CLOCK_STM32F4X_PLLM_DIV_FACTOR=8 -CONFIG_CLOCK_STM32F4X_PLLN_MULTIPLIER=336 -CONFIG_CLOCK_STM32F4X_PLLP_DIV_FACTOR=4 -CONFIG_CLOCK_STM32F4X_PLLQ_DIV_FACTOR=7 -CONFIG_CLOCK_STM32F4X_AHB_PRESCALER=0 -CONFIG_CLOCK_STM32F4X_APB1_PRESCALER=2 -CONFIG_CLOCK_STM32F4X_APB2_PRESCALER=0 # Clock configuration for Cube Clock control driver CONFIG_CLOCK_STM32_HSE_CLOCK=8000000 diff --git a/boards/arm/nucleo_f411re/nucleo_f411re_defconfig b/boards/arm/nucleo_f411re/nucleo_f411re_defconfig index c61fcd47b2c..8303a5fee54 100644 --- a/boards/arm/nucleo_f411re/nucleo_f411re_defconfig +++ b/boards/arm/nucleo_f411re/nucleo_f411re_defconfig @@ -22,20 +22,6 @@ CONFIG_GPIO=y # clock configuration CONFIG_CLOCK_CONTROL=y -CONFIG_CLOCK_STM32F4X_SYSCLK_SRC_PLL=y -# use HSE as PLL input -CONFIG_CLOCK_STM32F4X_PLL_SRC_HSE=y -# however, the board does not have an external oscillator, so just use -# the 8MHz clock signal coming from integrated STLink -CONFIG_CLOCK_STM32F4X_HSE_BYPASS=y -# produce 96MHz clock at PLL output -CONFIG_CLOCK_STM32F4X_PLLM_DIV_FACTOR=8 -CONFIG_CLOCK_STM32F4X_PLLN_MULTIPLIER=384 -CONFIG_CLOCK_STM32F4X_PLLP_DIV_FACTOR=4 -CONFIG_CLOCK_STM32F4X_PLLQ_DIV_FACTOR=8 -CONFIG_CLOCK_STM32F4X_AHB_PRESCALER=0 -CONFIG_CLOCK_STM32F4X_APB1_PRESCALER=2 -CONFIG_CLOCK_STM32F4X_APB2_PRESCALER=0 # Clock configuration for Cube Clock control driver CONFIG_CLOCK_STM32_HSE_CLOCK=8000000 diff --git a/drivers/clock_control/Kconfig b/drivers/clock_control/Kconfig index 6df214b918e..df51078e2c5 100644 --- a/drivers/clock_control/Kconfig +++ b/drivers/clock_control/Kconfig @@ -50,8 +50,6 @@ source "drivers/clock_control/Kconfig.stm32f10x" source "drivers/clock_control/Kconfig.stm32f107xx" -source "drivers/clock_control/Kconfig.stm32f4x" - source "drivers/clock_control/Kconfig.beetle" endif # CLOCK_CONTROL diff --git a/drivers/clock_control/Kconfig.stm32f4x b/drivers/clock_control/Kconfig.stm32f4x deleted file mode 100644 index 9621e155112..00000000000 --- a/drivers/clock_control/Kconfig.stm32f4x +++ /dev/null @@ -1,141 +0,0 @@ -# Kconfig - STM32F4 MCU clock control driver config -# -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# Copyright (c) Linaro Limited. -# -# SPDX-License-Identifier: Apache-2.0 -# - -if SOC_SERIES_STM32F4X - -menuconfig CLOCK_CONTROL_STM32F4X - bool - prompt "STM32F4X Reset & Clock Control" - default y if SOC_SERIES_STM32F4X - help - Enable driver for Reset & Clock Control subsystem found - in STM32F4 family of MCUs - -config CLOCK_CONTROL_STM32F4X_DEVICE_INIT_PRIORITY - int "Clock Control Device Priority" - default 1 - depends on CLOCK_CONTROL_STM32F4X - help - This option controls the priority of clock control - device initialization. Higher priority ensures that the device - is initialized earlier in the startup cycle. If unsure, leave - at default value 1 - -choice -prompt "STM32F4X System Clock Source" -depends on CLOCK_CONTROL_STM32F4X - -config CLOCK_STM32F4X_SYSCLK_SRC_HSI - bool "HSI" - help - Use HSI as source of SYSCLK - -config CLOCK_STM32F4X_SYSCLK_SRC_HSE - bool "HSE" - help - Use HSE as source of SYSCLK - -config CLOCK_STM32F4X_SYSCLK_SRC_PLL - bool "PLL" - help - Use PLL as source of SYSCLK - -endchoice - -choice -prompt "STM32F4X PLL Clock Source" -depends on CLOCK_CONTROL_STM32F4X && CLOCK_STM32F4X_SYSCLK_SRC_PLL - -config CLOCK_STM32F4X_PLL_SRC_HSI - bool "HSI" - help - Use HSI as source of PLL - -config CLOCK_STM32F4X_PLL_SRC_HSE - bool "HSE" - help - Use HSE as source of PLL - -endchoice - -config CLOCK_STM32F4X_HSE_BYPASS - bool "HSE bypass" - depends on CLOCK_CONTROL_STM32F4X && (CLOCK_STM32F4X_PLL_SRC_HSE || CLOCK_STM32F4X_SYSCLK_SRC_HSE) - help - Enable this option to bypass external high-speed clock (HSE). - -config CLOCK_STM32F4X_PLLM_DIV_FACTOR - int "Division factor for PLL VCO input clock" - depends on CLOCK_CONTROL_STM32F4X && CLOCK_STM32F4X_SYSCLK_SRC_PLL - default 8 - range 2 63 - help - PLLM division factor needs to be set correctly to ensure that the VCO - input frequency ranges from 1 to 2 MHz. It is recommended to select a - frequency of 2 MHz to limit PLL jitter. - Allowed values: 2-63 - -config CLOCK_STM32F4X_PLLN_MULTIPLIER - int "Multiplier factor for PLL VCO output clock" - depends on CLOCK_CONTROL_STM32F4X && CLOCK_STM32F4X_SYSCLK_SRC_PLL - default 336 - range 192 432 if SOC_STM32F401XE - range 50 432 - help - PLLN multiplier factor needs to be set correctly to ensure that the - VCO output frequency is between 100 and 432 MHz, except on STM32F401 - where the frequency must be between 192 and 432 MHz. - Allowed values: 50-432 (STM32F401: 192-432) - -config CLOCK_STM32F4X_PLLP_DIV_FACTOR - int "PLL division factor for main system clock" - depends on CLOCK_CONTROL_STM32F4X && CLOCK_STM32F4X_SYSCLK_SRC_PLL - default 4 - range 2 8 - help - PLLP division factor needs to be set correctly to not exceed 84MHz. - Allowed values: 2, 4, 6, 8 - -config CLOCK_STM32F4X_PLLQ_DIV_FACTOR - int "Division factor for OTG FS, SDIO and RNG clocks" - depends on CLOCK_CONTROL_STM32F4X && CLOCK_STM32F4X_SYSCLK_SRC_PLL - default 7 - range 2 15 - help - The USB OTG FS requires a 48MHz clock to work correctly. SDIO and RNG - need a frequency lower than or equal to 48 MHz to work correctly. - Allowed values: 2-15 - -config CLOCK_STM32F4X_AHB_PRESCALER - int "AHB prescaler" - depends on CLOCK_CONTROL_STM32F4X - default 0 - range 0 512 - help - AHB prescaler, allowed values: 0, 2, 4, 8, 16, 64, 128, - 256, 512. - -config CLOCK_STM32F4X_APB1_PRESCALER - int "APB1 low speed clock prescaler" - depends on CLOCK_CONTROL_STM32F4X - default 2 - range 0 16 - help - APB1 Low speed clock (PCLK1) prescaler, allowed values: - 0, 2, 4, 8, 16. The APB1 clock must not exceed 42MHz. - -config CLOCK_STM32F4X_APB2_PRESCALER - int "APB2 high speed clock prescaler" - depends on CLOCK_CONTROL_STM32F4X - default 0 - range 0 16 - help - APB2 High speed clock (PCLK2) prescaler, allowed values: - 0, 2, 4, 8, 16. The APB2 clock must not exceed 84MHz. - -endif diff --git a/drivers/clock_control/Makefile b/drivers/clock_control/Makefile index 13574177a85..fc9273a8906 100644 --- a/drivers/clock_control/Makefile +++ b/drivers/clock_control/Makefile @@ -8,6 +8,5 @@ obj-$(CONFIG_SOC_SERIES_STM32F4X) += stm32f4x_ll_clock.o else obj-$(CONFIG_CLOCK_CONTROL_STM32F10X) += stm32f10x_clock.o obj-$(CONFIG_CLOCK_CONTROL_STM32F10X_CONN_LINE) += stm32f107xx_clock.o -obj-$(CONFIG_CLOCK_CONTROL_STM32F4X) += stm32f4x_clock.o endif obj-$(CONFIG_CLOCK_CONTROL_BEETLE) += beetle_clock_control.o diff --git a/drivers/clock_control/stm32f4x_clock.c b/drivers/clock_control/stm32f4x_clock.c deleted file mode 100644 index 45c7781510e..00000000000 --- a/drivers/clock_control/stm32f4x_clock.c +++ /dev/null @@ -1,350 +0,0 @@ -/* - * Copyright (c) 2016 Open-RnD Sp. z o.o. - * Copyright (c) 2016 Linaro Limited. - * - * SPDX-License-Identifier: Apache-2.0 - */ - - -/** - * @brief Driver for Reset & Clock Control of STM32F4X family processor. - * - * Based on reference manual: - * RM0368 Reference manual STM32F401xB/C and STM32F401xD/E - * advanced ARM ® -based 32-bit MCUs - * - * Chapter 6. Reset and Clock control (RCC) for STM43F401xB/C and STM32F401xD/E - */ - -#include -#include -#include -#include -#include - -struct stm32f4x_rcc_data { - u8_t *base; -}; - -static inline int stm32f4x_clock_control_on(struct device *dev, - clock_control_subsys_t sub_system) -{ - struct stm32f4x_rcc_data *data = dev->driver_data; - volatile struct stm32f4x_rcc *rcc = (struct stm32f4x_rcc *)(data->base); - struct stm32f4x_pclken *pclken = (struct stm32f4x_pclken *)(sub_system); - u32_t tmpreg = 0; /* Register delay helper */ - - switch (pclken->bus) { - case STM32F4X_CLOCK_BUS_AHB1: - rcc->ahb1enr |= pclken->enr; - tmpreg = rcc->ahb1enr; - break; - case STM32F4X_CLOCK_BUS_AHB2: - rcc->ahb2enr |= pclken->enr; - tmpreg = rcc->ahb2enr; - break; - case STM32F4X_CLOCK_BUS_APB1: - rcc->apb1enr |= pclken->enr; - tmpreg = rcc->apb1enr; - break; - case STM32F4X_CLOCK_BUS_APB2: - rcc->apb2enr |= pclken->enr; - tmpreg = rcc->apb2enr; - break; - } - - return 0; -} - -static inline int stm32f4x_clock_control_off(struct device *dev, - clock_control_subsys_t sub_system) -{ - struct stm32f4x_rcc_data *data = dev->driver_data; - volatile struct stm32f4x_rcc *rcc = (struct stm32f4x_rcc *)(data->base); - struct stm32f4x_pclken *pclken = (struct stm32f4x_pclken *)(sub_system); - u32_t tmpreg = 0; /* Register delay helper */ - - switch (pclken->bus) { - case STM32F4X_CLOCK_BUS_AHB1: - rcc->ahb1enr &= ~pclken->enr; - tmpreg = rcc->ahb1enr; - break; - case STM32F4X_CLOCK_BUS_AHB2: - rcc->ahb2enr &= ~pclken->enr; - tmpreg = rcc->ahb2enr; - break; - case STM32F4X_CLOCK_BUS_APB1: - rcc->apb1enr &= ~pclken->enr; - tmpreg = rcc->apb1enr; - break; - case STM32F4X_CLOCK_BUS_APB2: - rcc->apb2enr &= ~pclken->enr; - tmpreg = rcc->apb2enr; - break; - } - - return 0; -} - -/** - * @brief helper for mapping a setting to register value - */ -struct regval_map { - int val; - int reg; -}; - -static int map_reg_val(const struct regval_map *map, size_t cnt, int val) -{ - for (int i = 0; i < cnt; i++) { - if (map[i].val == val) { - return map[i].reg; - } - } - - return 0; -} - -/** - * @brief map APB prescaler setting to register value - */ -static int __apb_prescaler(int prescaler) -{ - if (prescaler == 0) { - return STM32F4X_RCC_CFG_HCLK_DIV_0; - } - - const struct regval_map map[] = { - {0, STM32F4X_RCC_CFG_HCLK_DIV_0}, - {2, STM32F4X_RCC_CFG_HCLK_DIV_2}, - {4, STM32F4X_RCC_CFG_HCLK_DIV_4}, - {8, STM32F4X_RCC_CFG_HCLK_DIV_8}, - {16, STM32F4X_RCC_CFG_HCLK_DIV_16}, - }; - - return map_reg_val(map, ARRAY_SIZE(map), prescaler); -} - -/** - * @brief map AHB prescaler setting to register value - */ -static int __ahb_prescaler(int prescaler) -{ - if (prescaler == 0) { - return STM32F4X_RCC_CFG_SYSCLK_DIV_0; - } - - const struct regval_map map[] = { - {0, STM32F4X_RCC_CFG_SYSCLK_DIV_0}, - {2, STM32F4X_RCC_CFG_SYSCLK_DIV_2}, - {4, STM32F4X_RCC_CFG_SYSCLK_DIV_4}, - {8, STM32F4X_RCC_CFG_SYSCLK_DIV_8}, - {16, STM32F4X_RCC_CFG_SYSCLK_DIV_16}, - {64, STM32F4X_RCC_CFG_SYSCLK_DIV_64}, - {128, STM32F4X_RCC_CFG_SYSCLK_DIV_128}, - {256, STM32F4X_RCC_CFG_SYSCLK_DIV_256}, - {512, STM32F4X_RCC_CFG_SYSCLK_DIV_512}, - }; - - return map_reg_val(map, ARRAY_SIZE(map), prescaler); -} - -#ifdef CONFIG_CLOCK_STM32F4X_SYSCLK_SRC_PLL -/** - * @brief map PPLP division factor to register value - */ -static int __pllp_div(int div) -{ - if (div == 0) { - return STM32F4X_RCC_CFG_PLLP_DIV_2; - } - - const struct regval_map map[] = { - {2, STM32F4X_RCC_CFG_PLLP_DIV_2}, - {4, STM32F4X_RCC_CFG_PLLP_DIV_4}, - {6, STM32F4X_RCC_CFG_PLLP_DIV_6}, - {8, STM32F4X_RCC_CFG_PLLP_DIV_8}, - }; - - return map_reg_val(map, ARRAY_SIZE(map), div); -} -#endif /* CONFIG_CLOCK_STM32F4X_SYSCLK_SRC_PLL */ - -static u32_t __get_ahb_clock(u32_t sysclk) -{ - /* AHB clock is generated based on SYSCLK */ - u32_t sysclk_div = CONFIG_CLOCK_STM32F4X_AHB_PRESCALER; - - if (sysclk_div == 0) { - sysclk_div = 1; - } - - return sysclk / sysclk_div; -} - -static u32_t __get_apb_clock(u32_t ahb_clock, u32_t prescaler) -{ - if (prescaler == 0) { - prescaler = 1; - } - - return ahb_clock / prescaler; -} - -static int stm32f4x_clock_control_get_subsys_rate(struct device *clock, - clock_control_subsys_t sub_system, - u32_t *rate) -{ - struct stm32f4x_pclken *pclken = (struct stm32f4x_pclken *)(sub_system); - /* assumes SYSCLK is SYS_CLOCK_HW_CYCLES_PER_SEC */ - u32_t ahb_clock = - __get_ahb_clock(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC); - u32_t apb1_clock = __get_apb_clock(ahb_clock, - CONFIG_CLOCK_STM32F4X_APB1_PRESCALER); - u32_t apb2_clock = __get_apb_clock(ahb_clock, - CONFIG_CLOCK_STM32F4X_APB2_PRESCALER); - ARG_UNUSED(clock); - - switch (pclken->bus) { - case STM32F4X_CLOCK_BUS_AHB1: - case STM32F4X_CLOCK_BUS_AHB2: - *rate = ahb_clock; - break; - case STM32F4X_CLOCK_BUS_APB1: - *rate = apb1_clock; - break; - case STM32F4X_CLOCK_BUS_APB2: - *rate = apb2_clock; - break; - } - - return 0; -} - -static struct clock_control_driver_api stm32f4x_clock_control_api = { - .on = stm32f4x_clock_control_on, - .off = stm32f4x_clock_control_off, - .get_rate = stm32f4x_clock_control_get_subsys_rate, -}; - -static int stm32f4x_clock_control_init(struct device *dev) -{ - struct stm32f4x_rcc_data *data = dev->driver_data; - volatile struct stm32f4x_rcc *rcc = - (struct stm32f4x_rcc *)(data->base); - /* SYSCLK source defaults to HSI */ - int sysclk_src = STM32F4X_RCC_CFG_SYSCLK_SRC_HSI; - u32_t hpre = __ahb_prescaler(CONFIG_CLOCK_STM32F4X_AHB_PRESCALER); - u32_t ppre1 = __apb_prescaler(CONFIG_CLOCK_STM32F4X_APB1_PRESCALER); - u32_t ppre2 = __apb_prescaler(CONFIG_CLOCK_STM32F4X_APB2_PRESCALER); -#ifdef CONFIG_CLOCK_STM32F4X_SYSCLK_SRC_PLL - u32_t pllmdiv = CONFIG_CLOCK_STM32F4X_PLLM_DIV_FACTOR; - u32_t pllnmul = CONFIG_CLOCK_STM32F4X_PLLN_MULTIPLIER; - u32_t pllpdiv = __pllp_div(CONFIG_CLOCK_STM32F4X_PLLP_DIV_FACTOR); - u32_t pllqdiv = CONFIG_CLOCK_STM32F4X_PLLQ_DIV_FACTOR; -#endif /* CONFIG_CLOCK_STM32F4X_SYSCLK_SRC_PLL */ - /* Register delay helper */ - u32_t tmpreg = 0; - - /* Enable power control clock */ - rcc->apb1enr |= STM32F4X_RCC_APB1ENR_PWREN; - tmpreg = rcc->apb1enr; - - /* disable PLL */ - rcc->cr.bit.pllon = 0; - /* disable HSE */ - rcc->cr.bit.hseon = 0; - -#ifdef CONFIG_CLOCK_STM32F4X_HSE_BYPASS - /* HSE is disabled, HSE bypass can be enabled */ - rcc->cr.bit.hsebyp = 1; -#endif - -#ifdef CONFIG_CLOCK_STM32F4X_PLL_SRC_HSI - /* enable HSI clock */ - rcc->cr.bit.hsion = 1; - - /* this should end after one test */ - while (rcc->cr.bit.hsirdy != 1) { - } - - /* TODO: should we care about HSI calibration adjustment? */ - - /* PLL input from HSI */ - rcc->pllcfgr.bit.pllsrc = STM32F4X_RCC_CFG_PLL_SRC_HSI; -#endif /* CONFIG_CLOCK_STM32F4X_PLL_SRC_HSI */ - -#ifdef CONFIG_CLOCK_STM32F4X_PLL_SRC_HSE - /* wait for to become ready */ - rcc->cr.bit.hseon = 1; - - while (rcc->cr.bit.hserdy != 1) { - } - - /* TODO: should we disable HSI if HSE gets used? */ - - rcc->pllcfgr.bit.pllsrc = STM32F4X_RCC_CFG_PLL_SRC_HSE; -#endif /* CONFIG_CLOCK_STM32F4X_PLL_SRC_HSE */ - - /* setup AHB prescaler */ - rcc->cfgr.bit.hpre = hpre; - - /* setup APB1, must not exceed 42MHz */ - rcc->cfgr.bit.ppre1 = ppre1; - - /* setup APB2 */ - rcc->cfgr.bit.ppre2 = ppre2; - -#ifdef CONFIG_CLOCK_STM32F4X_SYSCLK_SRC_PLL - /* default set of dividers and multipliers (PLL must be disabled) */ - rcc->pllcfgr.bit.pllm = pllmdiv; - rcc->pllcfgr.bit.plln = pllnmul; - rcc->pllcfgr.bit.pllp = pllpdiv; - rcc->pllcfgr.bit.pllq = pllqdiv; - - /* enable PLL */ - rcc->cr.bit.pllon = 1; - - /* wait for PLL to become ready */ - while (rcc->cr.bit.pllrdy != 1) { - } - - sysclk_src = STM32F4X_RCC_CFG_SYSCLK_SRC_PLL; -#elif defined(CONFIG_CLOCK_STM32F4X_SYSCLK_SRC_HSE) - /* wait for to become ready */ - rcc->cr.bit.hseon = 1; - while (rcc->cr.bit.hserdy != 1) { - } - - sysclk_src = STM32F4X_RCC_CFG_SYSCLK_SRC_HSE; -#endif - - /* configure flash access latency before SYSCLK source switch */ - __setup_flash(); - - /* set SYSCLK clock value */ - rcc->cfgr.bit.sw = sysclk_src; - - /* wait for SYSCLK to switch the source */ - while (rcc->cfgr.bit.sws != sysclk_src) { - } - - return 0; -} - -static struct stm32f4x_rcc_data stm32f4x_rcc_data = { - .base = (u8_t *)RCC_BASE, -}; - -/* FIXME: move prescaler/multiplier defines into device config */ - -/** - * @brief RCC device, note that priority is intentionally set to 1 so - * that the device init runs just after SOC init - */ -DEVICE_AND_API_INIT(rcc_stm32f4x, STM32_CLOCK_CONTROL_NAME, - &stm32f4x_clock_control_init, - &stm32f4x_rcc_data, NULL, - PRE_KERNEL_1, - CONFIG_CLOCK_CONTROL_STM32F4X_DEVICE_INIT_PRIORITY, - &stm32f4x_clock_control_api); diff --git a/drivers/dma/dma_stm32f4x.c b/drivers/dma/dma_stm32f4x.c index 5cdecaec0a1..a1a1138b7a6 100644 --- a/drivers/dma/dma_stm32f4x.c +++ b/drivers/dma/dma_stm32f4x.c @@ -66,11 +66,7 @@ static struct dma_stm32_device { } device_data[DMA_STM32_MAX_DEVS]; struct dma_stm32_config { -#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE struct stm32_pclken pclken; -#else - struct stm32f4x_pclken pclken; -#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */ void (*config)(struct dma_stm32_device *); }; @@ -500,13 +496,8 @@ static const struct dma_driver_api dma_funcs = { }; const struct dma_stm32_config dma_stm32_1_cdata = { -#if CONFIG_CLOCK_CONTROL_STM32F4X - .pclken = { .bus = STM32F4X_CLOCK_BUS_AHB1, - .enr = STM32F4X_CLOCK_ENABLE_DMA1 }, -#else .pclken = { .bus = STM32_CLOCK_BUS_AHB1, .enr = LL_AHB1_GRP1_PERIPH_DMA1 }, -#endif .config = dma_stm32_1_config, }; @@ -516,13 +507,8 @@ DEVICE_AND_API_INIT(dma_stm32_1, CONFIG_DMA_1_NAME, &dma_stm32_init, (void *)&dma_funcs); static const struct dma_stm32_config dma_stm32_2_cdata = { -#if CONFIG_CLOCK_CONTROL_STM32F4X - .pclken = { .bus = STM32F4X_CLOCK_BUS_AHB1, - .enr = STM32F4X_CLOCK_ENABLE_DMA2 }, -#else .pclken = { .bus = STM32_CLOCK_BUS_AHB1, .enr = LL_AHB1_GRP1_PERIPH_DMA2 }, -#endif /* CONFIG_CLOCK_CONTROL_STM32F4X */ .config = dma_stm32_2_config, }; diff --git a/drivers/gpio/gpio_stm32.c b/drivers/gpio/gpio_stm32.c index a08ff1b2895..2c8172fe1fc 100644 --- a/drivers/gpio/gpio_stm32.c +++ b/drivers/gpio/gpio_stm32.c @@ -189,8 +189,7 @@ static int gpio_stm32_init(struct device *device) device_get_binding(STM32_CLOCK_CONTROL_NAME); -#if defined(CONFIG_SOC_SERIES_STM32F4X) || \ - defined(CONFIG_CLOCK_CONTROL_STM32_CUBE) +#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE clock_control_on(clk, (clock_control_subsys_t *) &cfg->pclken); #else clock_control_on(clk, cfg->clock_subsys); @@ -199,7 +198,7 @@ static int gpio_stm32_init(struct device *device) } -#if defined(CONFIG_CLOCK_CONTROL_STM32_CUBE) +#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE #define GPIO_DEVICE_INIT(__name, __suffix, __base_addr, __port, __cenr, __bus) \ static const struct gpio_stm32_config gpio_stm32_cfg_## __suffix = { \ @@ -219,9 +218,8 @@ DEVICE_AND_API_INIT(gpio_stm32_## __suffix, \ #else -#ifndef CONFIG_SOC_SERIES_STM32F4X - -/* TODO: Change F1 to work similarly to F4 */ +/* TODO: This case only applies to F1 family */ +/* To be removed when migrated to LL clock control driver */ #define GPIO_DEVICE_INIT(__name, __suffix, __base_addr, __port, __clock) \ static const struct gpio_stm32_config gpio_stm32_cfg_## __suffix = { \ .base = (u32_t *)__base_addr, \ @@ -238,24 +236,7 @@ DEVICE_AND_API_INIT(gpio_stm32_## __suffix, \ CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \ &gpio_stm32_driver); -#else /* CONFIG_SOC_SERIES_STM32F4X */ -#define GPIO_DEVICE_INIT(__name, __suffix, __base_addr, __port, __cenr) \ -static const struct gpio_stm32_config gpio_stm32_cfg_## __suffix = { \ - .base = (u32_t *)__base_addr, \ - .port = __port, \ - .pclken = { .bus = STM32F4X_CLOCK_BUS_AHB1, .enr = __cenr }, \ -}; \ -static struct gpio_stm32_data gpio_stm32_data_## __suffix; \ -DEVICE_AND_API_INIT(gpio_stm32_## __suffix, \ - __name, \ - gpio_stm32_init, \ - &gpio_stm32_data_## __suffix, \ - &gpio_stm32_cfg_## __suffix, \ - POST_KERNEL, \ - CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \ - &gpio_stm32_driver); -#endif #endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */ #ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE @@ -264,17 +245,13 @@ DEVICE_AND_API_INIT(gpio_stm32_## __suffix, \ GPIO##__SUFFIX##_BASE, STM32_PORT##__SUFFIX, \ STM32_PERIPH_GPIO##__SUFFIX, \ STM32_CLOCK_BUS_GPIO) -#elif defined(CONFIG_SOC_SERIES_STM32F1X) +#else + /* TODO: Clean once F1 series moved to LL Clock control */ #define GPIO_DEVICE_INIT_STM32(__suffix, __SUFFIX) \ GPIO_DEVICE_INIT("GPIO" #__SUFFIX, __suffix, \ GPIO##__SUFFIX##_BASE, STM32_PORT##__SUFFIX, \ STM32F10X_CLOCK_SUBSYS_IOP##__SUFFIX | \ STM32F10X_CLOCK_SUBSYS_AFIO) -#elif defined(CONFIG_SOC_SERIES_STM32F4X) -#define GPIO_DEVICE_INIT_STM32(__suffix, __SUFFIX) \ - GPIO_DEVICE_INIT("GPIO" #__SUFFIX, __suffix, \ - GPIO##__SUFFIX##_BASE, STM32_PORT##__SUFFIX, \ - STM32F4X_CLOCK_ENABLE_GPIO##__SUFFIX) #endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */ #ifdef CONFIG_GPIO_STM32_PORTA diff --git a/drivers/gpio/gpio_stm32.h b/drivers/gpio/gpio_stm32.h index a1cbe85e122..c59d7c67955 100644 --- a/drivers/gpio/gpio_stm32.h +++ b/drivers/gpio/gpio_stm32.h @@ -53,9 +53,7 @@ struct gpio_stm32_config { enum stm32_pin_port port; #ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE struct stm32_pclken pclken; -#elif CONFIG_SOC_SERIES_STM32F4X - struct stm32f4x_pclken pclken; -#else /* SOC_SERIES_STM32F1X || SOC_SERIES_STM32F3X || SOC_SERIES_STM32L4X */ +#else /* SOC_SERIES_STM32F1X */ /* clock subsystem */ clock_control_subsys_t clock_subsys; #endif diff --git a/drivers/pinmux/stm32/pinmux_stm32.c b/drivers/pinmux/stm32/pinmux_stm32.c index 2b89a63b103..0fe6abd0136 100644 --- a/drivers/pinmux/stm32/pinmux_stm32.c +++ b/drivers/pinmux/stm32/pinmux_stm32.c @@ -42,17 +42,6 @@ static const u32_t ports_enable[STM32_PORTS_MAX] = { STM32_PERIPH_GPIOH, #endif }; -#elif defined(CONFIG_SOC_SERIES_STM32F4X) -static const u32_t ports_enable[STM32_PORTS_MAX] = { - STM32F4X_CLOCK_ENABLE_GPIOA, - STM32F4X_CLOCK_ENABLE_GPIOB, - STM32F4X_CLOCK_ENABLE_GPIOC, - STM32F4X_CLOCK_ENABLE_GPIOD, - STM32F4X_CLOCK_ENABLE_GPIOE, - STM32F4X_CLOCK_ENABLE_GPIOF, - STM32F4X_CLOCK_ENABLE_GPIOG, - STM32F4X_CLOCK_ENABLE_GPIOH, -}; #endif /** @@ -79,18 +68,10 @@ static int enable_port(u32_t port, struct device *clk) return clock_control_on(clk, (clock_control_subsys_t *) &pclken); #else -#if defined(CONFIG_SOC_SERIES_STM32F1X) + /* TODO: Clean once F1 series moved to LL Clock control */ clock_control_subsys_t subsys = stm32_get_port_clock(port); return clock_control_on(clk, subsys); -#elif CONFIG_SOC_SERIES_STM32F4X - struct stm32f4x_pclken pclken; - /* AHB1 bus for all the GPIO ports */ - pclken.bus = STM32F4X_CLOCK_BUS_AHB1; - pclken.enr = ports_enable[port]; - - return clock_control_on(clk, (clock_control_subsys_t *) &pclken); -#endif #endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */ } diff --git a/drivers/pwm/pwm_stm32.c b/drivers/pwm/pwm_stm32.c index 6ee3a0fecd0..6be993122ac 100644 --- a/drivers/pwm/pwm_stm32.c +++ b/drivers/pwm/pwm_stm32.c @@ -53,30 +53,8 @@ static u32_t __get_tim_clk(u32_t bus_clk, return tim_clk; } #else -#ifdef CONFIG_SOC_SERIES_STM32F4X -static u32_t __get_tim_clk(u32_t bus_clk, - clock_control_subsys_t *sub_system) -{ - struct stm32f4x_pclken *pclken = (struct stm32f4x_pclken *)(sub_system); - u32_t tim_clk, apb_psc; - - if (pclken->bus == STM32F4X_CLOCK_BUS_APB1) { - apb_psc = CONFIG_CLOCK_STM32F4X_APB1_PRESCALER; - } else { - apb_psc = CONFIG_CLOCK_STM32F4X_APB2_PRESCALER; - } - - if (apb_psc == RCC_HCLK_DIV1) { - tim_clk = bus_clk; - } else { - tim_clk = 2 * bus_clk; - } - - return tim_clk; -} - -#else - +/* This code only applies to F1 family */ +/* To be deleted when F1 series ported to LL clock control driver */ static u32_t __get_tim_clk(u32_t bus_clk, clock_control_subsys_t sub_system) { @@ -97,7 +75,6 @@ static u32_t __get_tim_clk(u32_t bus_clk, return tim_clk; } -#endif /* CONFIG_SOC_SERIES_STM32F4X */ #endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */ /* @@ -200,8 +177,7 @@ static int pwm_stm32_get_cycles_per_sec(struct device *dev, u32_t pwm, } /* Timer clock depends on APB prescaler */ -#if defined(CONFIG_SOC_SERIES_STM32F4X) || \ - defined(CONFIG_CLOCK_CONTROL_STM32_CUBE) +#if defined(CONFIG_CLOCK_CONTROL_STM32_CUBE) clock_control_get_rate(data->clock, (clock_control_subsys_t *)&cfg->pclken, &bus_clk); @@ -243,8 +219,7 @@ static int pwm_stm32_init(struct device *dev) __pwm_stm32_get_clock(dev); /* enable clock */ -#if defined(CONFIG_SOC_SERIES_STM32F4X) || \ - defined(CONFIG_CLOCK_CONTROL_STM32_CUBE) +#if defined(CONFIG_CLOCK_CONTROL_STM32_CUBE) clock_control_on(data->clock, (clock_control_subsys_t *)&config->pclken); #else @@ -266,13 +241,8 @@ static const struct pwm_stm32_config pwm_stm32_dev_cfg_1 = { #ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE .pclken = { .bus = STM32_CLOCK_BUS_APB2, .enr = LL_APB2_GRP1_PERIPH_TIM1 }, -#else -#ifdef CONFIG_SOC_SERIES_STM32F4X - .pclken = { .bus = STM32F4X_CLOCK_BUS_APB2, - .enr = STM32F4X_CLOCK_ENABLE_TIM1 }, #else .clock_subsys = UINT_TO_POINTER(CLOCK_SUBSYS_TIM1), -#endif /* CONFIG_SOC_SERIES_STM32F4X */ #endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */ }; @@ -295,13 +265,8 @@ static const struct pwm_stm32_config pwm_stm32_dev_cfg_2 = { #ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE .pclken = { .bus = STM32_CLOCK_BUS_APB1, .enr = LL_APB1_GRP1_PERIPH_TIM2 }, -#else -#ifdef CONFIG_SOC_SERIES_STM32F4X - .pclken = { .bus = STM32F4X_CLOCK_BUS_APB1, - .enr = STM32F4X_CLOCK_ENABLE_TIM2 }, #else .clock_subsys = UINT_TO_POINTER(CLOCK_SUBSYS_TIM2), -#endif /* CONFIG_SOC_SERIES_STM32F4X */ #endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */ }; diff --git a/drivers/pwm/pwm_stm32.h b/drivers/pwm/pwm_stm32.h index 6a53fed7b84..98331c3281a 100644 --- a/drivers/pwm/pwm_stm32.h +++ b/drivers/pwm/pwm_stm32.h @@ -22,11 +22,7 @@ struct pwm_stm32_config { #ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE struct stm32_pclken pclken; #else -#if defined(CONFIG_SOC_SERIES_STM32F1X) clock_control_subsys_t clock_subsys; -#elif defined(CONFIG_SOC_SERIES_STM32F4X) - struct stm32f4x_pclken pclken; -#endif #endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */ }; diff --git a/drivers/serial/uart_stm32.c b/drivers/serial/uart_stm32.c index bd615e0f26f..f5a47b55a4a 100644 --- a/drivers/serial/uart_stm32.c +++ b/drivers/serial/uart_stm32.c @@ -287,8 +287,7 @@ static int uart_stm32_init(struct device *dev) /* enable clock */ #if defined(CONFIG_SOC_SERIES_STM32F1X) clock_control_on(data->clock, config->clock_subsys); -#elif defined(CONFIG_SOC_SERIES_STM32F4X) || \ - defined(CONFIG_CLOCK_CONTROL_STM32_CUBE) +#elif defined(CONFIG_CLOCK_CONTROL_STM32_CUBE) clock_control_on(data->clock, (clock_control_subsys_t *)&config->pclken); #endif @@ -327,12 +326,7 @@ static const struct uart_stm32_config uart_stm32_dev_cfg_1 = { .pclken = { .bus = STM32_CLOCK_BUS_APB2, .enr = LL_APB2_GRP1_PERIPH_USART1 }, #else -#ifdef CONFIG_SOC_SERIES_STM32F1X .clock_subsys = UINT_TO_POINTER(STM32F10X_CLOCK_SUBSYS_USART1), -#elif CONFIG_SOC_SERIES_STM32F4X - .pclken = { .bus = STM32F4X_CLOCK_BUS_APB2, - .enr = STM32F4X_CLOCK_ENABLE_USART1 }, -#endif /* CONFIG_SOC_SERIES_STM32FX */ #endif /* CLOCK_CONTROL_STM32_CUBE */ }; @@ -381,12 +375,7 @@ static const struct uart_stm32_config uart_stm32_dev_cfg_2 = { .pclken = { .bus = STM32_CLOCK_BUS_APB1, .enr = LL_APB1_GRP1_PERIPH_USART2 }, #else -#ifdef CONFIG_SOC_SERIES_STM32F1X .clock_subsys = UINT_TO_POINTER(STM32F10X_CLOCK_SUBSYS_USART2), -#elif CONFIG_SOC_SERIES_STM32F4X - .pclken = { .bus = STM32F4X_CLOCK_BUS_APB1, - .enr = STM32F4X_CLOCK_ENABLE_USART2 }, -#endif /* CONFIG_SOC_SERIES_STM32FX */ #endif /* CLOCK_CONTROL_STM32_CUBE */ }; @@ -433,11 +422,7 @@ static const struct uart_stm32_config uart_stm32_dev_cfg_3 = { .pclken = { .bus = STM32_CLOCK_BUS_APB1, .enr = LL_APB1_GRP1_PERIPH_USART3 }, #else -#ifdef CONFIG_SOC_SERIES_STM32F1X .clock_subsys = UINT_TO_POINTER(STM32F10X_CLOCK_SUBSYS_USART3), -#elif CONFIG_SOC_SERIES_STM32F4X - .clock_subsys = UINT_TO_POINTER(STM32F40X_CLOCK_SUBSYS_USART3), -#endif /* CONFIG_SOC_SERIES_STM32F4X */ #endif /* CLOCK_CONTROL_STM32_CUBE */ }; diff --git a/drivers/serial/uart_stm32.h b/drivers/serial/uart_stm32.h index 160dc537e13..fa37a373bcb 100644 --- a/drivers/serial/uart_stm32.h +++ b/drivers/serial/uart_stm32.h @@ -19,11 +19,7 @@ struct uart_stm32_config { #if defined(CONFIG_CLOCK_CONTROL_STM32_CUBE) struct stm32_pclken pclken; #else -#if defined(CONFIG_SOC_SERIES_STM32F1X) clock_control_subsys_t clock_subsys; -#elif defined(CONFIG_SOC_SERIES_STM32F4X) - struct stm32f4x_pclken pclken; -#endif #endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */ }; diff --git a/include/drivers/clock_control/stm32_clock_control.h b/include/drivers/clock_control/stm32_clock_control.h index 63bd59427bb..57904a981c8 100644 --- a/include/drivers/clock_control/stm32_clock_control.h +++ b/include/drivers/clock_control/stm32_clock_control.h @@ -16,8 +16,6 @@ #ifdef CONFIG_SOC_SERIES_STM32F1X #include "stm32f1_clock_control.h" -#elif CONFIG_SOC_SERIES_STM32F4X -#include "stm32f4_clock_control.h" #endif /* Bus */ diff --git a/include/drivers/clock_control/stm32f4_clock_control.h b/include/drivers/clock_control/stm32f4_clock_control.h deleted file mode 100644 index 7580ac5bd2c..00000000000 --- a/include/drivers/clock_control/stm32f4_clock_control.h +++ /dev/null @@ -1,134 +0,0 @@ -/* - * Copyright (c) 2016 Open-RnD Sp. z o.o. - * (c) 2016 Linaro Limited. - * - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef _STM32F4_CLOCK_CONTROL_H_ -#define _STM32F4_CLOCK_CONTROL_H_ - -/** - * @file - * - * @brief Clock subsystem IDs for STM32F4 family - */ - -/* Bus */ -enum { - STM32F4X_CLOCK_BUS_AHB1, - STM32F4X_CLOCK_BUS_AHB2, - STM32F4X_CLOCK_BUS_AHB3, - STM32F4X_CLOCK_BUS_APB1, - STM32F4X_CLOCK_BUS_APB2, -}; - -/* AHB1 pins */ -enum { - /* AHB1 */ - STM32F4X_CLOCK_ENABLE_GPIOA = 1 << 0, - STM32F4X_CLOCK_ENABLE_GPIOB = 1 << 1, - STM32F4X_CLOCK_ENABLE_GPIOC = 1 << 2, - STM32F4X_CLOCK_ENABLE_GPIOD = 1 << 3, - STM32F4X_CLOCK_ENABLE_GPIOE = 1 << 4, - STM32F4X_CLOCK_ENABLE_GPIOF = 1 << 5, - STM32F4X_CLOCK_ENABLE_GPIOG = 1 << 6, - STM32F4X_CLOCK_ENABLE_GPIOH = 1 << 7, - STM32F4X_CLOCK_ENABLE_GPIOI = 1 << 8, - STM32F4X_CLOCK_ENABLE_GPIOJ = 1 << 9, - STM32F4X_CLOCK_ENABLE_GPIOK = 1 << 10, - STM32F4X_CLOCK_ENABLE_CRC = 1 << 12, - STM32F4X_CLOCK_ENABLE_BKPSRAM = 1 << 18, - STM32F4X_CLOCK_ENABLE_CCMDATARAM = 1 << 20, - STM32F4X_CLOCK_ENABLE_DMA1 = 1 << 21, - STM32F4X_CLOCK_ENABLE_DMA2 = 1 << 22, - STM32F4X_CLOCK_ENABLE_DMA2D = 1 << 23, - STM32F4X_CLOCK_ENABLE_ETHMAC = 1 << 25, - STM32F4X_CLOCK_ENABLE_ETHMACTX = 1 << 26, - STM32F4X_CLOCK_ENABLE_ETHMACRX = 1 << 27, - STM32F4X_CLOCK_ENABLE_ETHMACPTP = 1 << 28, - STM32F4X_CLOCK_ENABLE_OTGHS = 1 << 29, - STM32F4X_CLOCK_ENABLE_OTGHSULPI = 1 << 30, -}; - -/* AHB2 pins */ -enum { - STM32F4X_CLOCK_ENABLE_DCMI = 1 << 0, - STM32F4X_CLOCK_ENABLE_CRYP = 1 << 4, - STM32F4X_CLOCK_ENABLE_HASH = 1 << 5, - STM32F4X_CLOCK_ENABLE_RNG = 1 << 6, - STM32F4X_CLOCK_ENABLE_OTGFS = 1 << 7, -}; - -/* AHB3 pins */ -enum { - STM32F4X_CLOCK_ENABLE_FSMC = 1 << 0, - STM32F4X_CLOCK_ENABLE_QSPI = 1 << 1, -}; - -/* APB1 pins */ -enum { - STM32F4X_CLOCK_ENABLE_TIM2 = 1 << 0, - STM32F4X_CLOCK_ENABLE_TIM3 = 1 << 1, - STM32F4X_CLOCK_ENABLE_TIM4 = 1 << 2, - STM32F4X_CLOCK_ENABLE_TIM5 = 1 << 3, - STM32F4X_CLOCK_ENABLE_TIM6 = 1 << 4, - STM32F4X_CLOCK_ENABLE_TIM7 = 1 << 5, - STM32F4X_CLOCK_ENABLE_TIM12 = 1 << 6, - STM32F4X_CLOCK_ENABLE_TIM13 = 1 << 7, - STM32F4X_CLOCK_ENABLE_TIM14 = 1 << 8, - STM32F4X_CLOCK_ENABLE_LPTIMER1 = 1 << 9, - STM32F4X_CLOCK_ENABLE_RTCAPB = 1 << 10, - STM32F4X_CLOCK_ENABLE_WWDG = 1 << 11, - STM32F4X_CLOCK_ENABLE_SPI2 = 1 << 14, - STM32F4X_CLOCK_ENABLE_SPI3 = 1 << 15, - STM32F4X_CLOCK_ENABLE_USART2 = 1 << 17, - STM32F4X_CLOCK_ENABLE_USART3 = 1 << 18, - STM32F4X_CLOCK_ENABLE_UART4 = 1 << 19, - STM32F4X_CLOCK_ENABLE_UART5 = 1 << 20, - STM32F4X_CLOCK_ENABLE_I2C1 = 1 << 21, - STM32F4X_CLOCK_ENABLE_I2C2 = 1 << 22, - STM32F4X_CLOCK_ENABLE_I2C3 = 1 << 23, - STM32F4X_CLOCK_ENABLE_I2CFMP1 = 1 << 24, - STM32F4X_CLOCK_ENABLE_CAN1 = 1 << 25, - STM32F4X_CLOCK_ENABLE_CAN2 = 1 << 26, - STM32F4X_CLOCK_ENABLE_CAN3 = 1 << 27, - STM32F4X_CLOCK_ENABLE_PWR = 1 << 28, - STM32F4X_CLOCK_ENABLE_DAC = 1 << 29, - STM32F4X_CLOCK_ENABLE_UART7 = 1 << 30, - STM32F4X_CLOCK_ENABLE_UART8 = 1 << 31, -}; - -/* APB2 pins */ -enum { - STM32F4X_CLOCK_ENABLE_TIM1 = 1 << 0, - STM32F4X_CLOCK_ENABLE_TIM8 = 1 << 1, - STM32F4X_CLOCK_ENABLE_USART1 = 1 << 4, - STM32F4X_CLOCK_ENABLE_USART6 = 1 << 5, - STM32F4X_CLOCK_ENABLE_UART9 = 1 << 6, - STM32F4X_CLOCK_ENABLE_UART10 = 1 << 7, - STM32F4X_CLOCK_ENABLE_ADC1 = 1 << 8, - STM32F4X_CLOCK_ENABLE_ADC2 = 1 << 9, - STM32F4X_CLOCK_ENABLE_ADC3 = 1 << 10, - STM32F4X_CLOCK_ENABLE_SDIO = 1 << 11, - STM32F4X_CLOCK_ENABLE_SPI1 = 1 << 12, - STM32F4X_CLOCK_ENABLE_SPI4 = 1 << 13, - STM32F4X_CLOCK_ENABLE_SYSCFG = 1 << 14, - STM32F4X_CLOCK_ENABLE_EXTIT = 1 << 15, - STM32F4X_CLOCK_ENABLE_TIM9 = 1 << 16, - STM32F4X_CLOCK_ENABLE_TIM10 = 1 << 17, - STM32F4X_CLOCK_ENABLE_TIM11 = 1 << 18, - STM32F4X_CLOCK_ENABLE_SPI5 = 1 << 20, - STM32F4X_CLOCK_ENABLE_SPI6 = 1 << 21, - STM32F4X_CLOCK_ENABLE_SAI1 = 1 << 22, - STM32F4X_CLOCK_ENABLE_DFSDM1 = 1 << 24, - STM32F4X_CLOCK_ENABLE_DFSDM2 = 1 << 25, - STM32F4X_CLOCK_ENABLE_LTDC = 1 << 26, - STM32F4X_CLOCK_ENABLE_DSI = 1 << 27, -}; - -struct stm32f4x_pclken { - u32_t bus; - u32_t enr; -}; - -#endif /* _STM32F4_CLOCK_CONTROL_H_ */