michaelh/zephyr
1
0
Fork 0
Code Releases Activity

boards: hifive_unleashed: add support for E51 and U54 targets

Browse source 
Add `hifive_unleashed//e51` (earlier selected by default, using
`hifive_unleashed`) and `hifive_unleashed//u54` targets.

Define work-area for other 4 cores in openocd.cfg

Update twister platform white/black lists, to support new targets

Signed-off-by: Jakub Wasilewski <jwasilewski@internships.antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit is contained in:
Jakub Wasilewski 2024-05-14 16:20:00 +02:00 • committed by Fabio Baltieri
commit 2423c87d54
18 changed files with 220 additions and 21 deletions
Download patch file Download diff file Expand all files Collapse all files

3
boards/sifive/hifive_unleashed/Kconfig.hifive_unleashed
View file

@ -2,4 +2,5 @@
# SPDX-License-Identifier: Apache-2.0
config BOARD_HIFIVE_UNLEASHED
select SOC_SIFIVE_FREEDOM_FU540
select SOC_SIFIVE_FREEDOM_FU540_E51 if BOARD_HIFIVE_UNLEASHED_FU540_E51
select SOC_SIFIVE_FREEDOM_FU540_U54 if BOARD_HIFIVE_UNLEASHED_FU540_U54

18
boards/sifive/hifive_unleashed/doc/index.rst
View file

@ -15,9 +15,21 @@ Building
Applications for the ``hifive_unleashed`` board configuration can be built as
usual (see :ref:`build_an_application`) using the corresponding board name:
.. zephyr-app-commands::
:board: hifive_unleashed
:goals: build
.. tabs::
.. group-tab:: E51
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: hifive_unleashed/fu540/e51
:goals: build
.. group-tab:: U54
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: hifive_unleashed/fu540/u54
:goals: build
Flashing
========

0
boards/sifive/hifive_unleashed/hifive_unleashed.dts → boards/sifive/hifive_unleashed/hifive_unleashed.dtsi
View file

30
boards/sifive/hifive_unleashed/hifive_unleashed_e51.dts Normal file
View file

@ -0,0 +1,30 @@
/*
* Copyright (c) 2024 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include "hifive_unleashed.dtsi"
/ {
cpus {
cpu@1 {
status = "disabled";
};
cpu@2 {
status = "disabled";
};
cpu@3 {
status = "disabled";
};
cpu@4 {
status = "disabled";
};
};
};

6
boards/sifive/hifive_unleashed/hifive_unleashed.yaml → boards/sifive/hifive_unleashed/hifive_unleashed_e51.yaml
View file

@ -1,5 +1,5 @@
identifier: hifive_unleashed
name: SiFive HiFive Unleashed
identifier: hifive_unleashed/fu540/e51
name: SiFive HiFive Unleashed (E51)
type: mcu
arch: riscv
toolchain:
@ -8,11 +8,11 @@ ram: 3840
simulation: renode
simulation_exec: renode
testing:
timeout_multiplier: 6
ignore_tags:
- net
- bluetooth
- flash
- newlib
- crypto
renode:
uart: sysbus.uart0

0
boards/sifive/hifive_unleashed/hifive_unleashed_defconfig → boards/sifive/hifive_unleashed/hifive_unleashed_e51_defconfig
View file

17
boards/sifive/hifive_unleashed/hifive_unleashed_u54.dts Normal file
View file

@ -0,0 +1,17 @@
/*
* Copyright (c) 2024 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include "hifive_unleashed.dtsi"
/ {
cpus {
cpu@0 {
status = "disabled";
};
};
};

23
boards/sifive/hifive_unleashed/hifive_unleashed_u54.yaml Normal file
View file

@ -0,0 +1,23 @@
identifier: hifive_unleashed/fu540/u54
name: SiFive HiFive Unleashed (U54)
type: mcu
arch: riscv
toolchain:
- zephyr
ram: 3840
simulation: renode
simulation_exec: renode
testing:
timeout_multiplier: 6
ignore_tags:
- net
- bluetooth
- flash
- crypto
renode:
uart: sysbus.uart0
resc: boards/sifive/hifive_unleashed/support/hifive_unleashed.resc
supported:
- gpio
- spi
vendor: sifive

10
boards/sifive/hifive_unleashed/hifive_unleashed_u54_defconfig Normal file
View file

@ -0,0 +1,10 @@
# SPDX-License-Identifier: Apache-2.0
CONFIG_CONSOLE=y
CONFIG_GPIO=y
CONFIG_SERIAL=y
CONFIG_UART_SIFIVE_PORT_0=y
CONFIG_UART_CONSOLE=y
CONFIG_XIP=n
CONFIG_RV_BOOT_HART=1
CONFIG_FLOAT_HARD=y

4
boards/sifive/hifive_unleashed/support/openocd_hifive_unleashed.cfg
View file

@ -18,5 +18,9 @@ target create $_TARGETNAME.3 riscv -chain-position $_TARGETNAME -coreid 3
target create $_TARGETNAME.4 riscv -chain-position $_TARGETNAME -coreid 4
target smp $_TARGETNAME.0 $_TARGETNAME.1 $_TARGETNAME.2 $_TARGETNAME.3 $_TARGETNAME.4
$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 0x4000 -work-area-backup 1
$_TARGETNAME.1 configure -work-area-phys 0x80000000 -work-area-size 0x4000 -work-area-backup 1
$_TARGETNAME.2 configure -work-area-phys 0x80000000 -work-area-size 0x4000 -work-area-backup 1
$_TARGETNAME.3 configure -work-area-phys 0x80000000 -work-area-size 0x4000 -work-area-backup 1
$_TARGETNAME.4 configure -work-area-phys 0x80000000 -work-area-size 0x4000 -work-area-backup 1
flash bank onboard_spi_flash0 fespi 0x20000000 0 0 0 $_TARGETNAME.0 0x10040000

92
dts/riscv/sifive/riscv64-fu540.dtsi
View file

@ -32,14 +32,80 @@
#address-cells = <1>;
#size-cells = <0>;
cpu: cpu@0 {
cpu@0 {
compatible = "sifive,e51", "riscv";
device_type = "cpu";
reg = <0>;
i-cache-line-size = <0x4000>;
reg = <0x0>;
riscv,isa = "rv64imac_zicsr_zifencei";
status = "okay";
hlic0: interrupt-controller {
compatible = "riscv,cpu-intc";
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
};
};
hlic: interrupt-controller {
cpu@1 {
compatible = "sifive,u54", "riscv";
device_type = "cpu";
mmu-type = "riscv,sv39";
i-cache-line-size = <0x8000>;
d-cache-line-size = <0x8000>;
reg = <0x1>;
riscv,isa = "rv64gc";
hlic1: interrupt-controller {
compatible = "riscv,cpu-intc";
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
};
};
cpu@2 {
clock-frequency = <0>;
compatible = "sifive,u54", "riscv";
device_type = "cpu";
mmu-type = "riscv,sv39";
i-cache-line-size = <0x8000>;
d-cache-line-size = <0x8000>;
reg = <0x2>;
riscv,isa = "rv64gc";
hlic2: interrupt-controller {
compatible = "riscv,cpu-intc";
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
};
};
cpu@3 {
clock-frequency = <0>;
compatible = "sifive,u54", "riscv";
device_type = "cpu";
mmu-type = "riscv,sv39";
i-cache-line-size = <0x8000>;
d-cache-line-size = <0x8000>;
reg = <0x3>;
riscv,isa = "rv64gc";
hlic3: interrupt-controller {
compatible = "riscv,cpu-intc";
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
};
};
cpu@4 {
clock-frequency = <0>;
compatible = "sifive,u54", "riscv";
device_type = "cpu";
mmu-type = "riscv,sv39";
i-cache-line-size = <0x8000>;
d-cache-line-size = <0x8000>;
reg = <0x4>;
riscv,isa = "rv64gc";
hlic4: interrupt-controller {
compatible = "riscv,cpu-intc";
#address-cells = <0>;
#interrupt-cells = <1>;
@ -102,9 +168,17 @@
reg-names = "mem";
};
clint: clint@2000000 {
compatible = "sifive,clint0";
interrupts-extended = <&hlic 3 &hlic 7>;
interrupts-extended = <&hlic0 3 &hlic0 7
&hlic1 3 &hlic1 7
&hlic2 3 &hlic2 7
&hlic3 3 &hlic3 7
&hlic4 3 &hlic4 7>;
interrupt-names = "soft0", "timer0", "soft1", "timer1",
"soft2", "timer2", "soft3", "timer3",
"soft4", "timer4";
reg = <0x2000000 0x10000>;
};
@ -116,10 +190,14 @@
plic: interrupt-controller@c000000 {
compatible = "sifive,plic-1.0.0";
#address-cells = <0>;
#interrupt-cells = <2>;
#address-cells = <1>;
interrupt-controller;
interrupts-extended = <&hlic 11>;
interrupts-extended = <&hlic0 11
&hlic1 11 &hlic1 9
&hlic2 11 &hlic2 9
&hlic3 11 &hlic3 9
&hlic4 11 &hlic4 9>;
reg = <0x0c000000 0x04000000>;
riscv,max-priority = <7>;
riscv,ndev = <52>;

3
samples/drivers/jesd216/sample.yaml
View file

@ -15,7 +15,8 @@ tests:
sample.drivers.jesd216:
platform_exclude:
- hifive1
- hifive_unleashed
- hifive_unleashed/fu540/e51
- hifive_unleashed/fu540/u54
- hifive_unmatched
- mimxrt1170_evk/mimxrt1176/cm7
- mimxrt1170_evk/mimxrt1176/cm4

5
soc/sifive/sifive_freedom/fu500/Kconfig
View file

@ -23,3 +23,8 @@ config SOC_SERIES_SIFIVE_FREEDOM_FU500
select SOC_EARLY_INIT_HOOK
select INCLUDE_RESET_VECTOR
imply XIP
config SOC_SIFIVE_FREEDOM_FU540_U54
bool
select RISCV_ISA_EXT_G
select CPU_HAS_FPU_DOUBLE_PRECISION

6
soc/sifive/sifive_freedom/fu500/Kconfig.defconfig
View file

@ -25,4 +25,10 @@ config MAX_IRQ_PER_AGGREGATOR
config NUM_IRQS
default 64
config FPU
default y if CPU_HAS_FPU
config RISCV_IMPRECISE_FPU_STATE_TRACKING
default y if FPU
endif # SOC_SERIES_SIFIVE_FREEDOM_FU500

16
soc/sifive/sifive_freedom/fu500/Kconfig.soc
View file

@ -5,12 +5,20 @@ config SOC_SERIES_SIFIVE_FREEDOM_FU500
bool
select SOC_FAMILY_SIFIVE_FREEDOM
config SOC_SERIES
default "fu500" if SOC_SERIES_SIFIVE_FREEDOM_FU500
config SOC_SIFIVE_FREEDOM_FU540
bool
select SOC_SERIES_SIFIVE_FREEDOM_FU500
config SOC_SIFIVE_FREEDOM_FU540_E51
bool
select SOC_SIFIVE_FREEDOM_FU540
config SOC_SIFIVE_FREEDOM_FU540_U54
bool
select SOC_SIFIVE_FREEDOM_FU540
config SOC_SERIES
default "fu500" if SOC_SERIES_SIFIVE_FREEDOM_FU500
config SOC
default "fu540" if SOC_SIFIVE_FREEDOM_FU540
default "fu540" if SOC_SIFIVE_FREEDOM_FU540_E51 || SOC_SIFIVE_FREEDOM_FU540_U54

3
soc/sifive/sifive_freedom/soc.yml
View file

@ -7,6 +7,9 @@ family:
- name: fu500
socs:
- name: fu540
cpuclusters:
- name: e51
- name: u54
- name: fu700
socs:
- name: fu740

2
tests/drivers/console/line_splitting/testcase.yaml
View file

@ -2,7 +2,7 @@ common:
tags:
- drivers
- console
platform_allow: hifive1 hifive_unleashed
platform_allow: hifive1 hifive_unleashed/fu540/e51
harness: robot
tests:

3
tests/subsys/zbus/integration/testcase.yaml
View file

@ -3,7 +3,8 @@ tests:
platform_exclude:
- m2gl025_miv
- qemu_cortex_a9
- hifive_unleashed
- hifive_unleashed/fu540/e51
- hifive_unleashed/fu540/u54
- fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a/smp/ns
tags: zbus
integration_platforms: