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riscv32: rename to riscv

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With the upcoming riscv64 support, it is best to use "riscv" as the
subdirectory name and common symbols as riscv32 and riscv64 support
code is almost identical. Then later decide whether 32-bit or 64-bit
compilation is wanted.

Redirects for the web documentation are also included.

Then zephyrbot complained about this:

"
New files added that are not covered in CODEOWNERS:

dts/riscv/microsemi-miv.dtsi
dts/riscv/riscv32-fe310.dtsi

Please add one or more entries in the CODEOWNERS file to cover
those files
"

So I assigned them to those who created them. Feel free to readjust
as necessary.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
This commit is contained in:
Nicolas Pitre 2019-07-17 13:17:05 -04:00 • committed by Andrew Boie
commit 1f4b5ddd0f
159 changed files with 125 additions and 118 deletions
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77
soc/riscv/riscv-privilege/common/soc_common_irq.c Normal file
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/*
* Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief interrupt management code for riscv SOCs supporting the riscv
privileged architecture specification
*/
#include <irq.h>
void z_arch_irq_enable(unsigned int irq)
{
u32_t mie;
#if defined(CONFIG_RISCV_HAS_PLIC)
if (irq > RISCV_MAX_GENERIC_IRQ) {
riscv_plic_irq_enable(irq);
return;
}
#endif
/*
* CSR mie register is updated using atomic instruction csrrs
* (atomic read and set bits in CSR register)
*/
__asm__ volatile ("csrrs %0, mie, %1\n"
: "=r" (mie)
: "r" (1 << irq));
}
void z_arch_irq_disable(unsigned int irq)
{
u32_t mie;
#if defined(CONFIG_RISCV_HAS_PLIC)
if (irq > RISCV_MAX_GENERIC_IRQ) {
riscv_plic_irq_disable(irq);
return;
}
#endif
/*
* Use atomic instruction csrrc to disable device interrupt in mie CSR.
* (atomic read and clear bits in CSR register)
*/
__asm__ volatile ("csrrc %0, mie, %1\n"
: "=r" (mie)
: "r" (1 << irq));
};
int z_arch_irq_is_enabled(unsigned int irq)
{
u32_t mie;
#if defined(CONFIG_RISCV_HAS_PLIC)
if (irq > RISCV_MAX_GENERIC_IRQ)
return riscv_plic_irq_is_enabled(irq);
#endif
__asm__ volatile ("csrr %0, mie" : "=r" (mie));
return !!(mie & (1 << irq));
}
#if defined(CONFIG_RISCV_SOC_INTERRUPT_INIT)
void soc_interrupt_init(void)
{
/* ensure that all interrupts are disabled */
(void)irq_lock();
__asm__ volatile ("csrwi mie, 0\n"
"csrwi mip, 0\n");
}
#endif