From 1f4b5ddd0fa84f828213fe1200917bad480bce7b Mon Sep 17 00:00:00 2001 From: Nicolas Pitre Date: Wed, 17 Jul 2019 13:17:05 -0400 Subject: [PATCH] riscv32: rename to riscv With the upcoming riscv64 support, it is best to use "riscv" as the subdirectory name and common symbols as riscv32 and riscv64 support code is almost identical. Then later decide whether 32-bit or 64-bit compilation is wanted. Redirects for the web documentation are also included. Then zephyrbot complained about this: " New files added that are not covered in CODEOWNERS: dts/riscv/microsemi-miv.dtsi dts/riscv/riscv32-fe310.dtsi Please add one or more entries in the CODEOWNERS file to cover those files " So I assigned them to those who created them. Feel free to readjust as necessary. Signed-off-by: Nicolas Pitre --- CODEOWNERS | 18 ++++++++++-------- arch/Kconfig | 4 ++-- arch/{riscv32 => riscv}/CMakeLists.txt | 0 arch/{riscv32 => riscv}/Kconfig | 7 ++++--- arch/{riscv32 => riscv}/core/CMakeLists.txt | 0 arch/{riscv32 => riscv}/core/cpu_idle.c | 0 arch/{riscv32 => riscv}/core/fatal.c | 6 +++--- arch/{riscv32 => riscv}/core/irq_manage.c | 2 +- arch/{riscv32 => riscv}/core/irq_offload.c | 0 arch/{riscv32 => riscv}/core/isr.S | 0 .../{riscv32 => riscv}/core/offsets/offsets.c | 0 arch/{riscv32 => riscv}/core/prep_c.c | 0 arch/{riscv32 => riscv}/core/reset.S | 0 arch/{riscv32 => riscv}/core/swap.S | 0 arch/{riscv32 => riscv}/core/thread.c | 0 .../include/kernel_arch_data.h | 8 ++++---- .../include/kernel_arch_func.h | 12 ++++++------ .../include/kernel_arch_thread.h | 7 +++---- .../include/offsets_short_arch.h | 6 +++--- boards/index.rst | 2 +- .../{riscv32 => riscv}/hifive1/CMakeLists.txt | 0 .../{riscv32 => riscv}/hifive1/Kconfig.board | 0 .../hifive1/Kconfig.defconfig | 0 boards/{riscv32 => riscv}/hifive1/board.cmake | 0 .../{riscv32 => riscv}/hifive1/doc/index.rst | 1 - boards/{riscv32 => riscv}/hifive1/hifive1.dts | 1 - .../{riscv32 => riscv}/hifive1/hifive1.yaml | 0 .../hifive1/hifive1_defconfig | 2 +- boards/{riscv32 => riscv}/hifive1/pinmux.c | 0 .../hifive1/support/openocd.cfg | 0 .../hifive1_revb/CMakeLists.txt | 0 .../hifive1_revb/Kconfig.board | 0 .../hifive1_revb/Kconfig.defconfig | 0 .../hifive1_revb/board.cmake | 0 .../hifive1_revb/doc/index.rst | 1 - .../hifive1_revb/hifive1_revb.dts | 1 - .../hifive1_revb/hifive1_revb.yaml | 0 .../hifive1_revb/hifive1_revb_defconfig | 2 +- .../{riscv32 => riscv}/hifive1_revb/pinmux.c | 0 boards/{riscv32 => riscv}/index.rst | 4 ++-- .../litex_vexriscv/CMakeLists.txt | 0 .../litex_vexriscv/Kconfig.board | 0 .../litex_vexriscv/Kconfig.defconfig | 0 .../litex_vexriscv/doc/litex_vexriscv.rst | 0 .../litex_vexriscv/litex_vexriscv.dts | 0 .../litex_vexriscv/litex_vexriscv.yaml | 0 .../litex_vexriscv/litex_vexriscv_defconfig | 2 +- .../m2gl025_miv/CMakeLists.txt | 0 .../m2gl025_miv/Kconfig.board | 0 .../m2gl025_miv/Kconfig.defconfig | 0 .../m2gl025_miv/board.cmake | 0 .../m2gl025_miv/doc/index.rst | 1 - .../m2gl025_miv/m2gl025_miv.dts | 0 .../m2gl025_miv/m2gl025_miv.yaml | 0 .../m2gl025_miv/m2gl025_miv_defconfig | 2 +- .../m2gl025_miv/support/m2gl025_miv.resc | 0 .../qemu_riscv32/Kconfig.board | 0 .../qemu_riscv32/Kconfig.defconfig | 0 .../qemu_riscv32/board.cmake | 1 + .../qemu_riscv32/doc/index.rst | 0 .../qemu_riscv32/doc/qemu_riscv32.png | Bin .../qemu_riscv32/qemu_riscv32.dts | 1 - .../qemu_riscv32/qemu_riscv32.yaml | 0 .../qemu_riscv32/qemu_riscv32_defconfig | 2 +- .../rv32m1_vega/CMakeLists.txt | 0 .../rv32m1_vega/Kconfig.board | 0 .../rv32m1_vega/Kconfig.defconfig | 0 .../rv32m1_vega/board.cmake | 0 .../rv32m1_vega/doc/index.rst | 0 .../rv32m1_vega/doc/ri5cy_boot.jpg | Bin .../rv32m1_vega/doc/rv32m1_vega.png | Bin .../rv32m1_vega/doc/rv32m1_vega_jtag.jpg | Bin .../{riscv32 => riscv}/rv32m1_vega/pinmux.c | 0 .../rv32m1_vega/rv32m1_vega.dtsi | 0 .../rv32m1_vega/rv32m1_vega_ri5cy.dts | 0 .../rv32m1_vega/rv32m1_vega_ri5cy.yaml | 0 .../rv32m1_vega/rv32m1_vega_ri5cy_defconfig | 2 +- .../rv32m1_vega/rv32m1_vega_zero_riscy.dts | 0 .../rv32m1_vega/rv32m1_vega_zero_riscy.yaml | 0 .../rv32m1_vega_zero_riscy_defconfig | 2 +- .../support/openocd_rv32m1_vega_ri5cy.cfg | 0 .../openocd_rv32m1_vega_zero_riscy.cfg | 0 cmake/toolchain/xtools/target.cmake | 2 +- cmake/toolchain/zephyr/0.10.0/target.cmake | 2 +- cmake/toolchain/zephyr/0.10.1/target.cmake | 2 +- doc/conf.py | 16 ++++++++++++---- drivers/interrupt_controller/plic.c | 2 +- dts/{riscv32 => riscv}/microsemi-miv.dtsi | 0 dts/{riscv32 => riscv}/riscv32-fe310.dtsi | 0 .../riscv32-litex-vexriscv.dtsi | 0 dts/{riscv32 => riscv}/rv32m1.dtsi | 0 dts/{riscv32 => riscv}/rv32m1_ri5cy.dtsi | 2 +- dts/{riscv32 => riscv}/rv32m1_zero_riscy.dtsi | 2 +- include/arch/cpu.h | 4 ++-- include/arch/{riscv32 => riscv}/arch.h | 12 ++++++------ .../arch/{riscv32 => riscv}/common/linker.ld | 2 +- include/arch/{riscv32 => riscv}/exp.h | 10 +++++----- .../riscv-privilege/asm_inline.h | 8 ++++---- .../riscv-privilege/asm_inline_gcc.h | 6 +++--- include/linker/linker-tool-gcc.h | 6 +++++- include/toolchain/common.h | 2 +- include/toolchain/gcc.h | 4 ++-- kernel/Kconfig | 4 ++-- lib/libc/newlib/libc-hooks.c | 2 +- soc/Kconfig | 4 ++-- soc/{riscv32 => riscv}/CMakeLists.txt | 1 - .../litex-vexriscv/CMakeLists.txt | 0 .../litex-vexriscv/Kconfig.defconfig | 0 .../litex-vexriscv/Kconfig.soc | 0 .../litex-vexriscv/linker.ld | 2 +- soc/{riscv32 => riscv}/litex-vexriscv/soc.h | 0 .../openisa_rv32m1/CMakeLists.txt | 0 soc/{riscv32 => riscv}/openisa_rv32m1/Kconfig | 4 ++-- .../openisa_rv32m1/Kconfig.defconfig | 4 ++-- .../openisa_rv32m1/Kconfig.soc | 2 +- .../openisa_rv32m1/dts_fixup.h | 0 .../openisa_rv32m1/linker.ld | 6 +++--- soc/{riscv32 => riscv}/openisa_rv32m1/soc.c | 0 soc/{riscv32 => riscv}/openisa_rv32m1/soc.h | 0 .../openisa_rv32m1/soc_context.h | 0 .../openisa_rv32m1/soc_irq.S | 0 .../openisa_rv32m1/soc_offsets.h | 0 .../openisa_rv32m1/soc_ri5cy.h | 0 .../openisa_rv32m1/soc_zero_riscy.h | 0 .../openisa_rv32m1/vector.S | 0 soc/{riscv32 => riscv}/openisa_rv32m1/wdog.S | 0 .../riscv-privilege/CMakeLists.txt | 0 .../riscv-privilege/Kconfig | 2 +- .../riscv-privilege/Kconfig.defconfig | 2 +- .../riscv-privilege/Kconfig.soc | 2 +- .../riscv-privilege/common/CMakeLists.txt | 0 .../riscv-privilege/common/idle.c | 0 .../riscv-privilege/common/soc_common.h | 0 .../riscv-privilege/common/soc_common_irq.c | 0 .../riscv-privilege/common/soc_irq.S | 0 .../riscv-privilege/common/vector.S | 0 .../riscv-privilege/miv/CMakeLists.txt | 0 .../miv/Kconfig.defconfig.series | 0 .../riscv-privilege/miv/Kconfig.series | 2 +- .../riscv-privilege/miv/Kconfig.soc | 0 .../riscv-privilege/miv/dts_fixup.h | 1 - .../riscv-privilege/miv/linker.ld | 2 +- .../riscv-privilege/miv/soc.h | 0 .../sifive-freedom/CMakeLists.txt | 0 .../sifive-freedom/Kconfig.defconfig.series | 0 .../sifive-freedom/Kconfig.series | 2 +- .../sifive-freedom/Kconfig.soc | 0 .../sifive-freedom/fe310_clock.c | 0 .../sifive-freedom/fe310_prci.h | 0 .../riscv-privilege/sifive-freedom/linker.ld | 2 +- .../riscv-privilege/sifive-freedom/soc.h | 0 subsys/debug/openocd.c | 2 +- subsys/logging/log_core.c | 2 +- .../testsuite/include/test_asm_inline_gcc.h | 2 +- tests/kernel/context/src/main.c | 4 ++-- tests/kernel/fatal/src/main.c | 2 +- tests/kernel/gen_isr_table/src/main.c | 4 ++-- tests/kernel/interrupt/src/interrupt.h | 2 +- .../mem_pool_concept/src/test_mpool.h | 2 +- 159 files changed, 125 insertions(+), 118 deletions(-) rename arch/{riscv32 => riscv}/CMakeLists.txt (100%) rename arch/{riscv32 => riscv}/Kconfig (96%) rename arch/{riscv32 => riscv}/core/CMakeLists.txt (100%) rename arch/{riscv32 => riscv}/core/cpu_idle.c (100%) rename arch/{riscv32 => riscv}/core/fatal.c (91%) rename arch/{riscv32 => riscv}/core/irq_manage.c (95%) rename arch/{riscv32 => riscv}/core/irq_offload.c (100%) rename arch/{riscv32 => riscv}/core/isr.S (100%) rename arch/{riscv32 => riscv}/core/offsets/offsets.c (100%) rename arch/{riscv32 => riscv}/core/prep_c.c (100%) rename arch/{riscv32 => riscv}/core/reset.S (100%) rename arch/{riscv32 => riscv}/core/swap.S (100%) rename arch/{riscv32 => riscv}/core/thread.c (100%) rename arch/{riscv32 => riscv}/include/kernel_arch_data.h (73%) rename arch/{riscv32 => riscv}/include/kernel_arch_func.h (72%) rename arch/{riscv32 => riscv}/include/kernel_arch_thread.h (87%) rename arch/{riscv32 => riscv}/include/offsets_short_arch.h (90%) rename boards/{riscv32 => riscv}/hifive1/CMakeLists.txt (100%) rename boards/{riscv32 => riscv}/hifive1/Kconfig.board (100%) rename boards/{riscv32 => riscv}/hifive1/Kconfig.defconfig (100%) rename boards/{riscv32 => riscv}/hifive1/board.cmake (100%) rename boards/{riscv32 => riscv}/hifive1/doc/index.rst (99%) rename boards/{riscv32 => riscv}/hifive1/hifive1.dts (99%) rename boards/{riscv32 => riscv}/hifive1/hifive1.yaml (100%) rename boards/{riscv32 => riscv}/hifive1/hifive1_defconfig (96%) rename boards/{riscv32 => riscv}/hifive1/pinmux.c (100%) rename boards/{riscv32 => riscv}/hifive1/support/openocd.cfg (100%) rename boards/{riscv32 => riscv}/hifive1_revb/CMakeLists.txt (100%) rename boards/{riscv32 => riscv}/hifive1_revb/Kconfig.board (100%) rename boards/{riscv32 => riscv}/hifive1_revb/Kconfig.defconfig (100%) rename boards/{riscv32 => riscv}/hifive1_revb/board.cmake (100%) rename boards/{riscv32 => riscv}/hifive1_revb/doc/index.rst (99%) rename boards/{riscv32 => riscv}/hifive1_revb/hifive1_revb.dts (99%) rename boards/{riscv32 => riscv}/hifive1_revb/hifive1_revb.yaml (100%) rename boards/{riscv32 => riscv}/hifive1_revb/hifive1_revb_defconfig (95%) rename boards/{riscv32 => riscv}/hifive1_revb/pinmux.c (100%) rename boards/{riscv32 => riscv}/index.rst (65%) rename boards/{riscv32 => riscv}/litex_vexriscv/CMakeLists.txt (100%) rename boards/{riscv32 => riscv}/litex_vexriscv/Kconfig.board (100%) rename boards/{riscv32 => riscv}/litex_vexriscv/Kconfig.defconfig (100%) rename boards/{riscv32 => riscv}/litex_vexriscv/doc/litex_vexriscv.rst (100%) rename boards/{riscv32 => riscv}/litex_vexriscv/litex_vexriscv.dts (100%) rename boards/{riscv32 => riscv}/litex_vexriscv/litex_vexriscv.yaml (100%) rename boards/{riscv32 => riscv}/litex_vexriscv/litex_vexriscv_defconfig (95%) rename boards/{riscv32 => riscv}/m2gl025_miv/CMakeLists.txt (100%) rename boards/{riscv32 => riscv}/m2gl025_miv/Kconfig.board (100%) rename boards/{riscv32 => riscv}/m2gl025_miv/Kconfig.defconfig (100%) rename boards/{riscv32 => riscv}/m2gl025_miv/board.cmake (100%) rename boards/{riscv32 => riscv}/m2gl025_miv/doc/index.rst (99%) rename boards/{riscv32 => riscv}/m2gl025_miv/m2gl025_miv.dts (100%) rename boards/{riscv32 => riscv}/m2gl025_miv/m2gl025_miv.yaml (100%) rename boards/{riscv32 => riscv}/m2gl025_miv/m2gl025_miv_defconfig (95%) rename boards/{riscv32 => riscv}/m2gl025_miv/support/m2gl025_miv.resc (100%) rename boards/{riscv32 => riscv}/qemu_riscv32/Kconfig.board (100%) rename boards/{riscv32 => riscv}/qemu_riscv32/Kconfig.defconfig (100%) rename boards/{riscv32 => riscv}/qemu_riscv32/board.cmake (85%) rename boards/{riscv32 => riscv}/qemu_riscv32/doc/index.rst (100%) rename boards/{riscv32 => riscv}/qemu_riscv32/doc/qemu_riscv32.png (100%) rename boards/{riscv32 => riscv}/qemu_riscv32/qemu_riscv32.dts (99%) rename boards/{riscv32 => riscv}/qemu_riscv32/qemu_riscv32.yaml (100%) rename boards/{riscv32 => riscv}/qemu_riscv32/qemu_riscv32_defconfig (96%) rename boards/{riscv32 => riscv}/rv32m1_vega/CMakeLists.txt (100%) rename boards/{riscv32 => riscv}/rv32m1_vega/Kconfig.board (100%) rename boards/{riscv32 => riscv}/rv32m1_vega/Kconfig.defconfig (100%) rename boards/{riscv32 => riscv}/rv32m1_vega/board.cmake (100%) rename boards/{riscv32 => riscv}/rv32m1_vega/doc/index.rst (100%) rename boards/{riscv32 => riscv}/rv32m1_vega/doc/ri5cy_boot.jpg (100%) rename boards/{riscv32 => riscv}/rv32m1_vega/doc/rv32m1_vega.png (100%) rename boards/{riscv32 => riscv}/rv32m1_vega/doc/rv32m1_vega_jtag.jpg (100%) rename boards/{riscv32 => riscv}/rv32m1_vega/pinmux.c (100%) rename boards/{riscv32 => riscv}/rv32m1_vega/rv32m1_vega.dtsi (100%) rename boards/{riscv32 => riscv}/rv32m1_vega/rv32m1_vega_ri5cy.dts (100%) rename boards/{riscv32 => riscv}/rv32m1_vega/rv32m1_vega_ri5cy.yaml (100%) rename boards/{riscv32 => riscv}/rv32m1_vega/rv32m1_vega_ri5cy_defconfig (94%) rename boards/{riscv32 => riscv}/rv32m1_vega/rv32m1_vega_zero_riscy.dts (100%) rename boards/{riscv32 => riscv}/rv32m1_vega/rv32m1_vega_zero_riscy.yaml (100%) rename boards/{riscv32 => riscv}/rv32m1_vega/rv32m1_vega_zero_riscy_defconfig (94%) rename boards/{riscv32 => riscv}/rv32m1_vega/support/openocd_rv32m1_vega_ri5cy.cfg (100%) rename boards/{riscv32 => riscv}/rv32m1_vega/support/openocd_rv32m1_vega_zero_riscy.cfg (100%) rename dts/{riscv32 => riscv}/microsemi-miv.dtsi (100%) rename dts/{riscv32 => riscv}/riscv32-fe310.dtsi (100%) rename dts/{riscv32 => riscv}/riscv32-litex-vexriscv.dtsi (100%) rename dts/{riscv32 => riscv}/rv32m1.dtsi (100%) rename dts/{riscv32 => riscv}/rv32m1_ri5cy.dtsi (98%) rename dts/{riscv32 => riscv}/rv32m1_zero_riscy.dtsi (98%) rename include/arch/{riscv32 => riscv}/arch.h (91%) rename include/arch/{riscv32 => riscv}/common/linker.ld (98%) rename include/arch/{riscv32 => riscv}/exp.h (89%) rename include/arch/{riscv32 => riscv}/riscv-privilege/asm_inline.h (55%) rename include/arch/{riscv32 => riscv}/riscv-privilege/asm_inline_gcc.h (62%) rename soc/{riscv32 => riscv}/CMakeLists.txt (99%) rename soc/{riscv32 => riscv}/litex-vexriscv/CMakeLists.txt (100%) rename soc/{riscv32 => riscv}/litex-vexriscv/Kconfig.defconfig (100%) rename soc/{riscv32 => riscv}/litex-vexriscv/Kconfig.soc (100%) rename soc/{riscv32 => riscv}/litex-vexriscv/linker.ld (72%) rename soc/{riscv32 => riscv}/litex-vexriscv/soc.h (100%) rename soc/{riscv32 => riscv}/openisa_rv32m1/CMakeLists.txt (100%) rename soc/{riscv32 => riscv}/openisa_rv32m1/Kconfig (84%) rename soc/{riscv32 => riscv}/openisa_rv32m1/Kconfig.defconfig (97%) rename soc/{riscv32 => riscv}/openisa_rv32m1/Kconfig.soc (97%) rename soc/{riscv32 => riscv}/openisa_rv32m1/dts_fixup.h (100%) rename soc/{riscv32 => riscv}/openisa_rv32m1/linker.ld (97%) rename soc/{riscv32 => riscv}/openisa_rv32m1/soc.c (100%) rename soc/{riscv32 => riscv}/openisa_rv32m1/soc.h (100%) rename soc/{riscv32 => riscv}/openisa_rv32m1/soc_context.h (100%) rename soc/{riscv32 => riscv}/openisa_rv32m1/soc_irq.S (100%) rename soc/{riscv32 => riscv}/openisa_rv32m1/soc_offsets.h (100%) rename soc/{riscv32 => riscv}/openisa_rv32m1/soc_ri5cy.h (100%) rename soc/{riscv32 => riscv}/openisa_rv32m1/soc_zero_riscy.h (100%) rename soc/{riscv32 => riscv}/openisa_rv32m1/vector.S (100%) rename soc/{riscv32 => riscv}/openisa_rv32m1/wdog.S (100%) rename soc/{riscv32 => riscv}/riscv-privilege/CMakeLists.txt (100%) rename soc/{riscv32 => riscv}/riscv-privilege/Kconfig (92%) rename soc/{riscv32 => riscv}/riscv-privilege/Kconfig.defconfig (74%) rename soc/{riscv32 => riscv}/riscv-privilege/Kconfig.soc (77%) rename soc/{riscv32 => riscv}/riscv-privilege/common/CMakeLists.txt (100%) rename soc/{riscv32 => riscv}/riscv-privilege/common/idle.c (100%) rename soc/{riscv32 => riscv}/riscv-privilege/common/soc_common.h (100%) rename soc/{riscv32 => riscv}/riscv-privilege/common/soc_common_irq.c (100%) rename soc/{riscv32 => riscv}/riscv-privilege/common/soc_irq.S (100%) rename soc/{riscv32 => riscv}/riscv-privilege/common/vector.S (100%) rename soc/{riscv32 => riscv}/riscv-privilege/miv/CMakeLists.txt (100%) rename soc/{riscv32 => riscv}/riscv-privilege/miv/Kconfig.defconfig.series (100%) rename soc/{riscv32 => riscv}/riscv-privilege/miv/Kconfig.series (93%) rename soc/{riscv32 => riscv}/riscv-privilege/miv/Kconfig.soc (100%) rename soc/{riscv32 => riscv}/riscv-privilege/miv/dts_fixup.h (99%) rename soc/{riscv32 => riscv}/riscv-privilege/miv/linker.ld (70%) rename soc/{riscv32 => riscv}/riscv-privilege/miv/soc.h (100%) rename soc/{riscv32 => riscv}/riscv-privilege/sifive-freedom/CMakeLists.txt (100%) rename soc/{riscv32 => riscv}/riscv-privilege/sifive-freedom/Kconfig.defconfig.series (100%) rename soc/{riscv32 => riscv}/riscv-privilege/sifive-freedom/Kconfig.series (94%) rename soc/{riscv32 => riscv}/riscv-privilege/sifive-freedom/Kconfig.soc (100%) rename soc/{riscv32 => riscv}/riscv-privilege/sifive-freedom/fe310_clock.c (100%) rename soc/{riscv32 => riscv}/riscv-privilege/sifive-freedom/fe310_prci.h (100%) rename soc/{riscv32 => riscv}/riscv-privilege/sifive-freedom/linker.ld (81%) rename soc/{riscv32 => riscv}/riscv-privilege/sifive-freedom/soc.h (100%) diff --git a/CODEOWNERS b/CODEOWNERS index 57b339157e2..19625de86c5 100644 --- a/CODEOWNERS +++ b/CODEOWNERS @@ -39,10 +39,10 @@ /arch/x86/ @andrewboie @gnuless /arch/nios2/ @andrewboie @wentongwu /arch/posix/ @aescolar -/arch/riscv32/ @kgugala @pgielda @nategraff-sifive +/arch/riscv/ @kgugala @pgielda @nategraff-sifive /soc/posix/ @aescolar -/soc/riscv32/ @kgugala @pgielda @nategraff-sifive -/soc/riscv32/openisa*/ @MaureenHelm +/soc/riscv/ @kgugala @pgielda @nategraff-sifive +/soc/riscv/openisa*/ @MaureenHelm /arch/x86/core/ @andrewboie @gnuless /arch/x86/core/ia32/crt0.S @andrewboie @gnuless /arch/x86/core/pcie.c @gnuless @@ -88,8 +88,8 @@ /boards/nios2/altera_max10/ @wentongwu /boards/arm/stm32_min_dev/ @cbsiddharth /boards/posix/ @aescolar -/boards/riscv32/ @kgugala @pgielda @nategraff-sifive -/boards/riscv32/rv32m1_vega/ @MaureenHelm +/boards/riscv/ @kgugala @pgielda @nategraff-sifive +/boards/riscv/rv32m1_vega/ @MaureenHelm /boards/shields/ @erwango /boards/x86/ @andrewboie @nashif /boards/x86/up_squared/ @gnuless @@ -178,8 +178,10 @@ /dts/arm/nordic/ @ioannisg @carlescufi /dts/arm/nxp/ @MaureenHelm /dts/arm/microchip/ @franciscomunoz @albertofloyd @scottwcpg -/dts/riscv32/rv32m1* @MaureenHelm -/dts/riscv32/riscv32-litex-vexriscv.dtsi @mateusz-holenko @kgugala @pgielda +/dts/riscv/microsemi-miv.dtsi @galak +/dts/riscv/rv32m1* @MaureenHelm +/dts/riscv/riscv32-fe310.dtsi @nategraff-sifive +/dts/riscv/riscv32-litex-vexriscv.dtsi @mateusz-holenko @kgugala @pgielda /dts/xtensa/xtensa.dtsi @ydamigos /dts/bindings/ @galak /dts/bindings/can/ @alexanderwachter @@ -227,7 +229,7 @@ /include/arch/nios2/ @andrewboie /include/arch/nios2/arch.h @andrewboie /include/arch/posix/ @aescolar -/include/arch/riscv32/ @nategraff-sifive @kgugala @pgielda +/include/arch/riscv/ @nategraff-sifive @kgugala @pgielda /include/arch/x86/ @andrewboie @wentongwu /include/arch/common/ @andrewboie @andyross @nashif /include/arch/x86/ia32/arch.h @andrewboie diff --git a/arch/Kconfig b/arch/Kconfig index 2592793b2a4..08400bb0469 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -41,8 +41,8 @@ config NIOS2 select ATOMIC_OPERATIONS_C select HAS_DTS -config RISCV32 - bool "RISCV32 architecture" +config RISCV + bool "RISCV architecture" select HAS_DTS config XTENSA diff --git a/arch/riscv32/CMakeLists.txt b/arch/riscv/CMakeLists.txt similarity index 100% rename from arch/riscv32/CMakeLists.txt rename to arch/riscv/CMakeLists.txt diff --git a/arch/riscv32/Kconfig b/arch/riscv/Kconfig similarity index 96% rename from arch/riscv32/Kconfig rename to arch/riscv/Kconfig index 973fb99ae66..093ef49e01c 100644 --- a/arch/riscv32/Kconfig +++ b/arch/riscv/Kconfig @@ -4,14 +4,15 @@ # SPDX-License-Identifier: Apache-2.0 # -menu "RISCV32 Options" - depends on RISCV32 +menu "RISCV Options" + depends on RISCV config ARCH string + default "riscv64" if 64BIT default "riscv32" -menu "RISCV32 Processor Options" +menu "RISCV Processor Options" config INCLUDE_RESET_VECTOR bool "Include Reset vector" diff --git a/arch/riscv32/core/CMakeLists.txt b/arch/riscv/core/CMakeLists.txt similarity index 100% rename from arch/riscv32/core/CMakeLists.txt rename to arch/riscv/core/CMakeLists.txt diff --git a/arch/riscv32/core/cpu_idle.c b/arch/riscv/core/cpu_idle.c similarity index 100% rename from arch/riscv32/core/cpu_idle.c rename to arch/riscv/core/cpu_idle.c diff --git a/arch/riscv32/core/fatal.c b/arch/riscv/core/fatal.c similarity index 91% rename from arch/riscv32/core/fatal.c rename to arch/riscv/core/fatal.c index 2ee5581af81..43ce2b1ce7e 100644 --- a/arch/riscv32/core/fatal.c +++ b/arch/riscv/core/fatal.c @@ -9,8 +9,8 @@ #include #include -FUNC_NORETURN void z_riscv32_fatal_error(unsigned int reason, - const z_arch_esf_t *esf) +FUNC_NORETURN void z_riscv_fatal_error(unsigned int reason, + const z_arch_esf_t *esf) { if (esf != NULL) { z_fatal_print("Faulting instruction address = 0x%08x", @@ -61,5 +61,5 @@ FUNC_NORETURN void _Fault(const z_arch_esf_t *esf) z_fatal_print("Exception cause %s (%d)", cause_str(mcause), (int)mcause); - z_riscv32_fatal_error(K_ERR_CPU_EXCEPTION, esf); + z_riscv_fatal_error(K_ERR_CPU_EXCEPTION, esf); } diff --git a/arch/riscv32/core/irq_manage.c b/arch/riscv/core/irq_manage.c similarity index 95% rename from arch/riscv32/core/irq_manage.c rename to arch/riscv/core/irq_manage.c index a4c1a185794..72bec6fe21e 100644 --- a/arch/riscv32/core/irq_manage.c +++ b/arch/riscv/core/irq_manage.c @@ -24,7 +24,7 @@ FUNC_NORETURN void z_irq_spurious(void *unused) riscv_plic_get_irq()); } #endif - z_riscv32_fatal_error(K_ERR_SPURIOUS_IRQ, NULL); + z_riscv_fatal_error(K_ERR_SPURIOUS_IRQ, NULL); } #ifdef CONFIG_DYNAMIC_INTERRUPTS diff --git a/arch/riscv32/core/irq_offload.c b/arch/riscv/core/irq_offload.c similarity index 100% rename from arch/riscv32/core/irq_offload.c rename to arch/riscv/core/irq_offload.c diff --git a/arch/riscv32/core/isr.S b/arch/riscv/core/isr.S similarity index 100% rename from arch/riscv32/core/isr.S rename to arch/riscv/core/isr.S diff --git a/arch/riscv32/core/offsets/offsets.c b/arch/riscv/core/offsets/offsets.c similarity index 100% rename from arch/riscv32/core/offsets/offsets.c rename to arch/riscv/core/offsets/offsets.c diff --git a/arch/riscv32/core/prep_c.c b/arch/riscv/core/prep_c.c similarity index 100% rename from arch/riscv32/core/prep_c.c rename to arch/riscv/core/prep_c.c diff --git a/arch/riscv32/core/reset.S b/arch/riscv/core/reset.S similarity index 100% rename from arch/riscv32/core/reset.S rename to arch/riscv/core/reset.S diff --git a/arch/riscv32/core/swap.S b/arch/riscv/core/swap.S similarity index 100% rename from arch/riscv32/core/swap.S rename to arch/riscv/core/swap.S diff --git a/arch/riscv32/core/thread.c b/arch/riscv/core/thread.c similarity index 100% rename from arch/riscv32/core/thread.c rename to arch/riscv/core/thread.c diff --git a/arch/riscv32/include/kernel_arch_data.h b/arch/riscv/include/kernel_arch_data.h similarity index 73% rename from arch/riscv32/include/kernel_arch_data.h rename to arch/riscv/include/kernel_arch_data.h index 2276556e0bc..8598c9066aa 100644 --- a/arch/riscv32/include/kernel_arch_data.h +++ b/arch/riscv/include/kernel_arch_data.h @@ -9,11 +9,11 @@ * @brief Private kernel definitions * * This file contains private kernel structures definitions and various - * other definitions for the RISCV32 processor architecture. + * other definitions for the RISCV processor architecture. */ -#ifndef ZEPHYR_ARCH_RISCV32_INCLUDE_KERNEL_ARCH_DATA_H_ -#define ZEPHYR_ARCH_RISCV32_INCLUDE_KERNEL_ARCH_DATA_H_ +#ifndef ZEPHYR_ARCH_RISCV_INCLUDE_KERNEL_ARCH_DATA_H_ +#define ZEPHYR_ARCH_RISCV_INCLUDE_KERNEL_ARCH_DATA_H_ #ifdef __cplusplus extern "C" { @@ -35,4 +35,4 @@ extern K_THREAD_STACK_DEFINE(_interrupt_stack, CONFIG_ISR_STACK_SIZE); #endif /* _ASMLANGUAGE */ -#endif /* ZEPHYR_ARCH_RISCV32_INCLUDE_KERNEL_ARCH_DATA_H_ */ +#endif /* ZEPHYR_ARCH_RISCV_INCLUDE_KERNEL_ARCH_DATA_H_ */ diff --git a/arch/riscv32/include/kernel_arch_func.h b/arch/riscv/include/kernel_arch_func.h similarity index 72% rename from arch/riscv32/include/kernel_arch_func.h rename to arch/riscv/include/kernel_arch_func.h index fa1bb924fdc..4827c6c1737 100644 --- a/arch/riscv32/include/kernel_arch_func.h +++ b/arch/riscv/include/kernel_arch_func.h @@ -9,11 +9,11 @@ * @brief Private kernel definitions * * This file contains private kernel function/macro definitions and various - * other definitions for the RISCV32 processor architecture. + * other definitions for the RISCV processor architecture. */ -#ifndef ZEPHYR_ARCH_RISCV32_INCLUDE_KERNEL_ARCH_FUNC_H_ -#define ZEPHYR_ARCH_RISCV32_INCLUDE_KERNEL_ARCH_FUNC_H_ +#ifndef ZEPHYR_ARCH_RISCV_INCLUDE_KERNEL_ARCH_FUNC_H_ +#define ZEPHYR_ARCH_RISCV_INCLUDE_KERNEL_ARCH_FUNC_H_ #include @@ -37,8 +37,8 @@ z_set_thread_return_value(struct k_thread *thread, unsigned int value) thread->arch.swap_return_value = value; } -FUNC_NORETURN void z_riscv32_fatal_error(unsigned int reason, - const z_arch_esf_t *esf); +FUNC_NORETURN void z_riscv_fatal_error(unsigned int reason, + const z_arch_esf_t *esf); #define z_is_in_isr() (_kernel.nested != 0U) @@ -52,4 +52,4 @@ int z_irq_do_offload(void); } #endif -#endif /* ZEPHYR_ARCH_RISCV32_INCLUDE_KERNEL_ARCH_FUNC_H_ */ +#endif /* ZEPHYR_ARCH_RISCV_INCLUDE_KERNEL_ARCH_FUNC_H_ */ diff --git a/arch/riscv32/include/kernel_arch_thread.h b/arch/riscv/include/kernel_arch_thread.h similarity index 87% rename from arch/riscv32/include/kernel_arch_thread.h rename to arch/riscv/include/kernel_arch_thread.h index 0a66521d9fb..4d9b2757645 100644 --- a/arch/riscv32/include/kernel_arch_thread.h +++ b/arch/riscv/include/kernel_arch_thread.h @@ -16,8 +16,8 @@ * necessary to instantiate instances of struct k_thread. */ -#ifndef ZEPHYR_ARCH_RISCV32_INCLUDE_KERNEL_ARCH_THREAD_H_ -#define ZEPHYR_ARCH_RISCV32_INCLUDE_KERNEL_ARCH_THREAD_H_ +#ifndef ZEPHYR_ARCH_RISCV_INCLUDE_KERNEL_ARCH_THREAD_H_ +#define ZEPHYR_ARCH_RISCV_INCLUDE_KERNEL_ARCH_THREAD_H_ #ifndef _ASMLANGUAGE #include @@ -52,5 +52,4 @@ typedef struct _thread_arch _thread_arch_t; #endif /* _ASMLANGUAGE */ -#endif /* ZEPHYR_ARCH_RISCV32_INCLUDE_KERNEL_ARCH_THREAD_H_ */ - +#endif /* ZEPHYR_ARCH_RISCV_INCLUDE_KERNEL_ARCH_THREAD_H_ */ diff --git a/arch/riscv32/include/offsets_short_arch.h b/arch/riscv/include/offsets_short_arch.h similarity index 90% rename from arch/riscv32/include/offsets_short_arch.h rename to arch/riscv/include/offsets_short_arch.h index ed8b6f3c1a9..2f07d4edd12 100644 --- a/arch/riscv32/include/offsets_short_arch.h +++ b/arch/riscv/include/offsets_short_arch.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ -#ifndef ZEPHYR_ARCH_RISCV32_INCLUDE_OFFSETS_SHORT_ARCH_H_ -#define ZEPHYR_ARCH_RISCV32_INCLUDE_OFFSETS_SHORT_ARCH_H_ +#ifndef ZEPHYR_ARCH_RISCV_INCLUDE_OFFSETS_SHORT_ARCH_H_ +#define ZEPHYR_ARCH_RISCV_INCLUDE_OFFSETS_SHORT_ARCH_H_ #include @@ -61,4 +61,4 @@ /* end - threads */ -#endif /* ZEPHYR_ARCH_RISCV32_INCLUDE_OFFSETS_SHORT_ARCH_H_ */ +#endif /* ZEPHYR_ARCH_RISCV_INCLUDE_OFFSETS_SHORT_ARCH_H_ */ diff --git a/boards/index.rst b/boards/index.rst index cd557672dac..9d854f42b6a 100644 --- a/boards/index.rst +++ b/boards/index.rst @@ -19,5 +19,5 @@ under :zephyr_file:`doc/templates/board.tmpl` nios2/index.rst xtensa/index.rst posix/index.rst - riscv32/index.rst + riscv/index.rst shields/index.rst diff --git a/boards/riscv32/hifive1/CMakeLists.txt b/boards/riscv/hifive1/CMakeLists.txt similarity index 100% rename from boards/riscv32/hifive1/CMakeLists.txt rename to boards/riscv/hifive1/CMakeLists.txt diff --git a/boards/riscv32/hifive1/Kconfig.board b/boards/riscv/hifive1/Kconfig.board similarity index 100% rename from boards/riscv32/hifive1/Kconfig.board rename to boards/riscv/hifive1/Kconfig.board diff --git a/boards/riscv32/hifive1/Kconfig.defconfig b/boards/riscv/hifive1/Kconfig.defconfig similarity index 100% rename from boards/riscv32/hifive1/Kconfig.defconfig rename to boards/riscv/hifive1/Kconfig.defconfig diff --git a/boards/riscv32/hifive1/board.cmake b/boards/riscv/hifive1/board.cmake similarity index 100% rename from boards/riscv32/hifive1/board.cmake rename to boards/riscv/hifive1/board.cmake diff --git a/boards/riscv32/hifive1/doc/index.rst b/boards/riscv/hifive1/doc/index.rst similarity index 99% rename from boards/riscv32/hifive1/doc/index.rst rename to boards/riscv/hifive1/doc/index.rst index e7b99b9c5d8..3a74d97a80a 100644 --- a/boards/riscv32/hifive1/doc/index.rst +++ b/boards/riscv/hifive1/doc/index.rst @@ -56,4 +56,3 @@ Debugging ========= Refer to the detailed overview about :ref:`application_debugging`. - diff --git a/boards/riscv32/hifive1/hifive1.dts b/boards/riscv/hifive1/hifive1.dts similarity index 99% rename from boards/riscv32/hifive1/hifive1.dts rename to boards/riscv/hifive1/hifive1.dts index ecd7eeb5ff8..a6a43a6af60 100644 --- a/boards/riscv32/hifive1/hifive1.dts +++ b/boards/riscv/hifive1/hifive1.dts @@ -94,4 +94,3 @@ status = "okay"; clock-frequency = <16000000>; }; - diff --git a/boards/riscv32/hifive1/hifive1.yaml b/boards/riscv/hifive1/hifive1.yaml similarity index 100% rename from boards/riscv32/hifive1/hifive1.yaml rename to boards/riscv/hifive1/hifive1.yaml diff --git a/boards/riscv32/hifive1/hifive1_defconfig b/boards/riscv/hifive1/hifive1_defconfig similarity index 96% rename from boards/riscv32/hifive1/hifive1_defconfig rename to boards/riscv/hifive1/hifive1_defconfig index e9928398b06..e1c08228a80 100644 --- a/boards/riscv32/hifive1/hifive1_defconfig +++ b/boards/riscv/hifive1/hifive1_defconfig @@ -1,6 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_RISCV32=y +CONFIG_RISCV=y CONFIG_SOC_SERIES_RISCV32_SIFIVE_FREEDOM=y CONFIG_SOC_RISCV32_SIFIVE_FREEDOM=y CONFIG_BOARD_HIFIVE1=y diff --git a/boards/riscv32/hifive1/pinmux.c b/boards/riscv/hifive1/pinmux.c similarity index 100% rename from boards/riscv32/hifive1/pinmux.c rename to boards/riscv/hifive1/pinmux.c diff --git a/boards/riscv32/hifive1/support/openocd.cfg b/boards/riscv/hifive1/support/openocd.cfg similarity index 100% rename from boards/riscv32/hifive1/support/openocd.cfg rename to boards/riscv/hifive1/support/openocd.cfg diff --git a/boards/riscv32/hifive1_revb/CMakeLists.txt b/boards/riscv/hifive1_revb/CMakeLists.txt similarity index 100% rename from boards/riscv32/hifive1_revb/CMakeLists.txt rename to boards/riscv/hifive1_revb/CMakeLists.txt diff --git a/boards/riscv32/hifive1_revb/Kconfig.board b/boards/riscv/hifive1_revb/Kconfig.board similarity index 100% rename from boards/riscv32/hifive1_revb/Kconfig.board rename to boards/riscv/hifive1_revb/Kconfig.board diff --git a/boards/riscv32/hifive1_revb/Kconfig.defconfig b/boards/riscv/hifive1_revb/Kconfig.defconfig similarity index 100% rename from boards/riscv32/hifive1_revb/Kconfig.defconfig rename to boards/riscv/hifive1_revb/Kconfig.defconfig diff --git a/boards/riscv32/hifive1_revb/board.cmake b/boards/riscv/hifive1_revb/board.cmake similarity index 100% rename from boards/riscv32/hifive1_revb/board.cmake rename to boards/riscv/hifive1_revb/board.cmake diff --git a/boards/riscv32/hifive1_revb/doc/index.rst b/boards/riscv/hifive1_revb/doc/index.rst similarity index 99% rename from boards/riscv32/hifive1_revb/doc/index.rst rename to boards/riscv/hifive1_revb/doc/index.rst index d96f70b1496..349753dcaad 100644 --- a/boards/riscv32/hifive1_revb/doc/index.rst +++ b/boards/riscv/hifive1_revb/doc/index.rst @@ -43,4 +43,3 @@ Debugging ========= Refer to the detailed overview about :ref:`application_debugging`. - diff --git a/boards/riscv32/hifive1_revb/hifive1_revb.dts b/boards/riscv/hifive1_revb/hifive1_revb.dts similarity index 99% rename from boards/riscv32/hifive1_revb/hifive1_revb.dts rename to boards/riscv/hifive1_revb/hifive1_revb.dts index ecadd8d3d96..f46fba3aa90 100644 --- a/boards/riscv32/hifive1_revb/hifive1_revb.dts +++ b/boards/riscv/hifive1_revb/hifive1_revb.dts @@ -98,4 +98,3 @@ input-frequency = <16000000>; clock-frequency = <100000>; }; - diff --git a/boards/riscv32/hifive1_revb/hifive1_revb.yaml b/boards/riscv/hifive1_revb/hifive1_revb.yaml similarity index 100% rename from boards/riscv32/hifive1_revb/hifive1_revb.yaml rename to boards/riscv/hifive1_revb/hifive1_revb.yaml diff --git a/boards/riscv32/hifive1_revb/hifive1_revb_defconfig b/boards/riscv/hifive1_revb/hifive1_revb_defconfig similarity index 95% rename from boards/riscv32/hifive1_revb/hifive1_revb_defconfig rename to boards/riscv/hifive1_revb/hifive1_revb_defconfig index 3388b875279..f96425513ed 100644 --- a/boards/riscv32/hifive1_revb/hifive1_revb_defconfig +++ b/boards/riscv/hifive1_revb/hifive1_revb_defconfig @@ -1,4 +1,4 @@ -CONFIG_RISCV32=y +CONFIG_RISCV=y CONFIG_SOC_SERIES_RISCV32_SIFIVE_FREEDOM=y CONFIG_SOC_RISCV32_SIFIVE_FREEDOM=y CONFIG_BOARD_HIFIVE1_REVB=y diff --git a/boards/riscv32/hifive1_revb/pinmux.c b/boards/riscv/hifive1_revb/pinmux.c similarity index 100% rename from boards/riscv32/hifive1_revb/pinmux.c rename to boards/riscv/hifive1_revb/pinmux.c diff --git a/boards/riscv32/index.rst b/boards/riscv/index.rst similarity index 65% rename from boards/riscv32/index.rst rename to boards/riscv/index.rst index 832948f4ece..85b481d09fa 100644 --- a/boards/riscv32/index.rst +++ b/boards/riscv/index.rst @@ -1,6 +1,6 @@ -.. _boards-riscv32: +.. _boards-riscv: -RISCV32 Boards +RISCV Boards ############## .. toctree:: diff --git a/boards/riscv32/litex_vexriscv/CMakeLists.txt b/boards/riscv/litex_vexriscv/CMakeLists.txt similarity index 100% rename from boards/riscv32/litex_vexriscv/CMakeLists.txt rename to boards/riscv/litex_vexriscv/CMakeLists.txt diff --git a/boards/riscv32/litex_vexriscv/Kconfig.board b/boards/riscv/litex_vexriscv/Kconfig.board similarity index 100% rename from boards/riscv32/litex_vexriscv/Kconfig.board rename to boards/riscv/litex_vexriscv/Kconfig.board diff --git a/boards/riscv32/litex_vexriscv/Kconfig.defconfig b/boards/riscv/litex_vexriscv/Kconfig.defconfig similarity index 100% rename from boards/riscv32/litex_vexriscv/Kconfig.defconfig rename to boards/riscv/litex_vexriscv/Kconfig.defconfig diff --git a/boards/riscv32/litex_vexriscv/doc/litex_vexriscv.rst b/boards/riscv/litex_vexriscv/doc/litex_vexriscv.rst similarity index 100% rename from boards/riscv32/litex_vexriscv/doc/litex_vexriscv.rst rename to boards/riscv/litex_vexriscv/doc/litex_vexriscv.rst diff --git a/boards/riscv32/litex_vexriscv/litex_vexriscv.dts b/boards/riscv/litex_vexriscv/litex_vexriscv.dts similarity index 100% rename from boards/riscv32/litex_vexriscv/litex_vexriscv.dts rename to boards/riscv/litex_vexriscv/litex_vexriscv.dts diff --git a/boards/riscv32/litex_vexriscv/litex_vexriscv.yaml b/boards/riscv/litex_vexriscv/litex_vexriscv.yaml similarity index 100% rename from boards/riscv32/litex_vexriscv/litex_vexriscv.yaml rename to boards/riscv/litex_vexriscv/litex_vexriscv.yaml diff --git a/boards/riscv32/litex_vexriscv/litex_vexriscv_defconfig b/boards/riscv/litex_vexriscv/litex_vexriscv_defconfig similarity index 95% rename from boards/riscv32/litex_vexriscv/litex_vexriscv_defconfig rename to boards/riscv/litex_vexriscv/litex_vexriscv_defconfig index af1bc566f68..b042cbab5a5 100644 --- a/boards/riscv32/litex_vexriscv/litex_vexriscv_defconfig +++ b/boards/riscv/litex_vexriscv/litex_vexriscv_defconfig @@ -4,7 +4,7 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_RISCV32=y +CONFIG_RISCV=y CONFIG_SOC_RISCV32_LITEX_VEXRISCV=y CONFIG_BOARD_LITEX_VEXRISCV=y CONFIG_VEXRISCV_LITEX_IRQ=y diff --git a/boards/riscv32/m2gl025_miv/CMakeLists.txt b/boards/riscv/m2gl025_miv/CMakeLists.txt similarity index 100% rename from boards/riscv32/m2gl025_miv/CMakeLists.txt rename to boards/riscv/m2gl025_miv/CMakeLists.txt diff --git a/boards/riscv32/m2gl025_miv/Kconfig.board b/boards/riscv/m2gl025_miv/Kconfig.board similarity index 100% rename from boards/riscv32/m2gl025_miv/Kconfig.board rename to boards/riscv/m2gl025_miv/Kconfig.board diff --git a/boards/riscv32/m2gl025_miv/Kconfig.defconfig b/boards/riscv/m2gl025_miv/Kconfig.defconfig similarity index 100% rename from boards/riscv32/m2gl025_miv/Kconfig.defconfig rename to boards/riscv/m2gl025_miv/Kconfig.defconfig diff --git a/boards/riscv32/m2gl025_miv/board.cmake b/boards/riscv/m2gl025_miv/board.cmake similarity index 100% rename from boards/riscv32/m2gl025_miv/board.cmake rename to boards/riscv/m2gl025_miv/board.cmake diff --git a/boards/riscv32/m2gl025_miv/doc/index.rst b/boards/riscv/m2gl025_miv/doc/index.rst similarity index 99% rename from boards/riscv32/m2gl025_miv/doc/index.rst rename to boards/riscv/m2gl025_miv/doc/index.rst index af159c9f3af..857b2871497 100644 --- a/boards/riscv32/m2gl025_miv/doc/index.rst +++ b/boards/riscv/m2gl025_miv/doc/index.rst @@ -64,4 +64,3 @@ Debugging ========= Refer to the detailed overview of :ref:`application_debugging`. - diff --git a/boards/riscv32/m2gl025_miv/m2gl025_miv.dts b/boards/riscv/m2gl025_miv/m2gl025_miv.dts similarity index 100% rename from boards/riscv32/m2gl025_miv/m2gl025_miv.dts rename to boards/riscv/m2gl025_miv/m2gl025_miv.dts diff --git a/boards/riscv32/m2gl025_miv/m2gl025_miv.yaml b/boards/riscv/m2gl025_miv/m2gl025_miv.yaml similarity index 100% rename from boards/riscv32/m2gl025_miv/m2gl025_miv.yaml rename to boards/riscv/m2gl025_miv/m2gl025_miv.yaml diff --git a/boards/riscv32/m2gl025_miv/m2gl025_miv_defconfig b/boards/riscv/m2gl025_miv/m2gl025_miv_defconfig similarity index 95% rename from boards/riscv32/m2gl025_miv/m2gl025_miv_defconfig rename to boards/riscv/m2gl025_miv/m2gl025_miv_defconfig index 7a58598a1aa..f0a8c135c52 100644 --- a/boards/riscv32/m2gl025_miv/m2gl025_miv_defconfig +++ b/boards/riscv/m2gl025_miv/m2gl025_miv_defconfig @@ -1,6 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_RISCV32=y +CONFIG_RISCV=y CONFIG_SOC_SERIES_RISCV32_MIV=y CONFIG_SOC_RISCV32_MIV=y CONFIG_BOARD_M2GL025_MIV=y diff --git a/boards/riscv32/m2gl025_miv/support/m2gl025_miv.resc b/boards/riscv/m2gl025_miv/support/m2gl025_miv.resc similarity index 100% rename from boards/riscv32/m2gl025_miv/support/m2gl025_miv.resc rename to boards/riscv/m2gl025_miv/support/m2gl025_miv.resc diff --git a/boards/riscv32/qemu_riscv32/Kconfig.board b/boards/riscv/qemu_riscv32/Kconfig.board similarity index 100% rename from boards/riscv32/qemu_riscv32/Kconfig.board rename to boards/riscv/qemu_riscv32/Kconfig.board diff --git a/boards/riscv32/qemu_riscv32/Kconfig.defconfig b/boards/riscv/qemu_riscv32/Kconfig.defconfig similarity index 100% rename from boards/riscv32/qemu_riscv32/Kconfig.defconfig rename to boards/riscv/qemu_riscv32/Kconfig.defconfig diff --git a/boards/riscv32/qemu_riscv32/board.cmake b/boards/riscv/qemu_riscv32/board.cmake similarity index 85% rename from boards/riscv32/qemu_riscv32/board.cmake rename to boards/riscv/qemu_riscv32/board.cmake index 408303f3860..56a403a4397 100644 --- a/boards/riscv32/qemu_riscv32/board.cmake +++ b/boards/riscv/qemu_riscv32/board.cmake @@ -2,6 +2,7 @@ set(EMU_PLATFORM qemu) +set(QEMU_binary_suffix riscv32) set(QEMU_CPU_TYPE_${ARCH} riscv32) set(QEMU_FLAGS_${ARCH} diff --git a/boards/riscv32/qemu_riscv32/doc/index.rst b/boards/riscv/qemu_riscv32/doc/index.rst similarity index 100% rename from boards/riscv32/qemu_riscv32/doc/index.rst rename to boards/riscv/qemu_riscv32/doc/index.rst diff --git a/boards/riscv32/qemu_riscv32/doc/qemu_riscv32.png b/boards/riscv/qemu_riscv32/doc/qemu_riscv32.png similarity index 100% rename from boards/riscv32/qemu_riscv32/doc/qemu_riscv32.png rename to boards/riscv/qemu_riscv32/doc/qemu_riscv32.png diff --git a/boards/riscv32/qemu_riscv32/qemu_riscv32.dts b/boards/riscv/qemu_riscv32/qemu_riscv32.dts similarity index 99% rename from boards/riscv32/qemu_riscv32/qemu_riscv32.dts rename to boards/riscv/qemu_riscv32/qemu_riscv32.dts index f34a8d226cd..a6411c96934 100644 --- a/boards/riscv32/qemu_riscv32/qemu_riscv32.dts +++ b/boards/riscv/qemu_riscv32/qemu_riscv32.dts @@ -46,4 +46,3 @@ spi-max-frequency = <0>; }; }; - diff --git a/boards/riscv32/qemu_riscv32/qemu_riscv32.yaml b/boards/riscv/qemu_riscv32/qemu_riscv32.yaml similarity index 100% rename from boards/riscv32/qemu_riscv32/qemu_riscv32.yaml rename to boards/riscv/qemu_riscv32/qemu_riscv32.yaml diff --git a/boards/riscv32/qemu_riscv32/qemu_riscv32_defconfig b/boards/riscv/qemu_riscv32/qemu_riscv32_defconfig similarity index 96% rename from boards/riscv32/qemu_riscv32/qemu_riscv32_defconfig rename to boards/riscv/qemu_riscv32/qemu_riscv32_defconfig index 21cfea5c97f..ffc9bf644f0 100644 --- a/boards/riscv32/qemu_riscv32/qemu_riscv32_defconfig +++ b/boards/riscv/qemu_riscv32/qemu_riscv32_defconfig @@ -1,6 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_RISCV32=y +CONFIG_RISCV=y CONFIG_SOC_SERIES_RISCV32_SIFIVE_FREEDOM=y CONFIG_SOC_RISCV32_SIFIVE_FREEDOM=y CONFIG_BOARD_QEMU_RISCV32=y diff --git a/boards/riscv32/rv32m1_vega/CMakeLists.txt b/boards/riscv/rv32m1_vega/CMakeLists.txt similarity index 100% rename from boards/riscv32/rv32m1_vega/CMakeLists.txt rename to boards/riscv/rv32m1_vega/CMakeLists.txt diff --git a/boards/riscv32/rv32m1_vega/Kconfig.board b/boards/riscv/rv32m1_vega/Kconfig.board similarity index 100% rename from boards/riscv32/rv32m1_vega/Kconfig.board rename to boards/riscv/rv32m1_vega/Kconfig.board diff --git a/boards/riscv32/rv32m1_vega/Kconfig.defconfig b/boards/riscv/rv32m1_vega/Kconfig.defconfig similarity index 100% rename from boards/riscv32/rv32m1_vega/Kconfig.defconfig rename to boards/riscv/rv32m1_vega/Kconfig.defconfig diff --git a/boards/riscv32/rv32m1_vega/board.cmake b/boards/riscv/rv32m1_vega/board.cmake similarity index 100% rename from boards/riscv32/rv32m1_vega/board.cmake rename to boards/riscv/rv32m1_vega/board.cmake diff --git a/boards/riscv32/rv32m1_vega/doc/index.rst b/boards/riscv/rv32m1_vega/doc/index.rst similarity index 100% rename from boards/riscv32/rv32m1_vega/doc/index.rst rename to boards/riscv/rv32m1_vega/doc/index.rst diff --git a/boards/riscv32/rv32m1_vega/doc/ri5cy_boot.jpg b/boards/riscv/rv32m1_vega/doc/ri5cy_boot.jpg similarity index 100% rename from boards/riscv32/rv32m1_vega/doc/ri5cy_boot.jpg rename to boards/riscv/rv32m1_vega/doc/ri5cy_boot.jpg diff --git a/boards/riscv32/rv32m1_vega/doc/rv32m1_vega.png b/boards/riscv/rv32m1_vega/doc/rv32m1_vega.png similarity index 100% rename from boards/riscv32/rv32m1_vega/doc/rv32m1_vega.png rename to boards/riscv/rv32m1_vega/doc/rv32m1_vega.png diff --git a/boards/riscv32/rv32m1_vega/doc/rv32m1_vega_jtag.jpg b/boards/riscv/rv32m1_vega/doc/rv32m1_vega_jtag.jpg similarity index 100% rename from boards/riscv32/rv32m1_vega/doc/rv32m1_vega_jtag.jpg rename to boards/riscv/rv32m1_vega/doc/rv32m1_vega_jtag.jpg diff --git a/boards/riscv32/rv32m1_vega/pinmux.c b/boards/riscv/rv32m1_vega/pinmux.c similarity index 100% rename from boards/riscv32/rv32m1_vega/pinmux.c rename to boards/riscv/rv32m1_vega/pinmux.c diff --git a/boards/riscv32/rv32m1_vega/rv32m1_vega.dtsi b/boards/riscv/rv32m1_vega/rv32m1_vega.dtsi similarity index 100% rename from boards/riscv32/rv32m1_vega/rv32m1_vega.dtsi rename to boards/riscv/rv32m1_vega/rv32m1_vega.dtsi diff --git a/boards/riscv32/rv32m1_vega/rv32m1_vega_ri5cy.dts b/boards/riscv/rv32m1_vega/rv32m1_vega_ri5cy.dts similarity index 100% rename from boards/riscv32/rv32m1_vega/rv32m1_vega_ri5cy.dts rename to boards/riscv/rv32m1_vega/rv32m1_vega_ri5cy.dts diff --git a/boards/riscv32/rv32m1_vega/rv32m1_vega_ri5cy.yaml b/boards/riscv/rv32m1_vega/rv32m1_vega_ri5cy.yaml similarity index 100% rename from boards/riscv32/rv32m1_vega/rv32m1_vega_ri5cy.yaml rename to boards/riscv/rv32m1_vega/rv32m1_vega_ri5cy.yaml diff --git a/boards/riscv32/rv32m1_vega/rv32m1_vega_ri5cy_defconfig b/boards/riscv/rv32m1_vega/rv32m1_vega_ri5cy_defconfig similarity index 94% rename from boards/riscv32/rv32m1_vega/rv32m1_vega_ri5cy_defconfig rename to boards/riscv/rv32m1_vega/rv32m1_vega_ri5cy_defconfig index 7b94138c722..0e11327d962 100644 --- a/boards/riscv32/rv32m1_vega/rv32m1_vega_ri5cy_defconfig +++ b/boards/riscv/rv32m1_vega/rv32m1_vega_ri5cy_defconfig @@ -1,6 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_RISCV32=y +CONFIG_RISCV=y CONFIG_SOC_OPENISA_RV32M1_RISCV32=y CONFIG_SOC_OPENISA_RV32M1_RI5CY=y CONFIG_BOARD_RV32M1_VEGA=y diff --git a/boards/riscv32/rv32m1_vega/rv32m1_vega_zero_riscy.dts b/boards/riscv/rv32m1_vega/rv32m1_vega_zero_riscy.dts similarity index 100% rename from boards/riscv32/rv32m1_vega/rv32m1_vega_zero_riscy.dts rename to boards/riscv/rv32m1_vega/rv32m1_vega_zero_riscy.dts diff --git a/boards/riscv32/rv32m1_vega/rv32m1_vega_zero_riscy.yaml b/boards/riscv/rv32m1_vega/rv32m1_vega_zero_riscy.yaml similarity index 100% rename from boards/riscv32/rv32m1_vega/rv32m1_vega_zero_riscy.yaml rename to boards/riscv/rv32m1_vega/rv32m1_vega_zero_riscy.yaml diff --git a/boards/riscv32/rv32m1_vega/rv32m1_vega_zero_riscy_defconfig b/boards/riscv/rv32m1_vega/rv32m1_vega_zero_riscy_defconfig similarity index 94% rename from boards/riscv32/rv32m1_vega/rv32m1_vega_zero_riscy_defconfig rename to boards/riscv/rv32m1_vega/rv32m1_vega_zero_riscy_defconfig index 6b75db41c19..f390108ef6b 100644 --- a/boards/riscv32/rv32m1_vega/rv32m1_vega_zero_riscy_defconfig +++ b/boards/riscv/rv32m1_vega/rv32m1_vega_zero_riscy_defconfig @@ -1,4 +1,4 @@ -CONFIG_RISCV32=y +CONFIG_RISCV=y CONFIG_SOC_OPENISA_RV32M1_RISCV32=y CONFIG_SOC_OPENISA_RV32M1_ZERO_RISCY=y CONFIG_BOARD_RV32M1_VEGA=y diff --git a/boards/riscv32/rv32m1_vega/support/openocd_rv32m1_vega_ri5cy.cfg b/boards/riscv/rv32m1_vega/support/openocd_rv32m1_vega_ri5cy.cfg similarity index 100% rename from boards/riscv32/rv32m1_vega/support/openocd_rv32m1_vega_ri5cy.cfg rename to boards/riscv/rv32m1_vega/support/openocd_rv32m1_vega_ri5cy.cfg diff --git a/boards/riscv32/rv32m1_vega/support/openocd_rv32m1_vega_zero_riscy.cfg b/boards/riscv/rv32m1_vega/support/openocd_rv32m1_vega_zero_riscy.cfg similarity index 100% rename from boards/riscv32/rv32m1_vega/support/openocd_rv32m1_vega_zero_riscy.cfg rename to boards/riscv/rv32m1_vega/support/openocd_rv32m1_vega_zero_riscy.cfg diff --git a/cmake/toolchain/xtools/target.cmake b/cmake/toolchain/xtools/target.cmake index 3fb986375ec..00ecf28e0b9 100644 --- a/cmake/toolchain/xtools/target.cmake +++ b/cmake/toolchain/xtools/target.cmake @@ -9,7 +9,7 @@ endif() set(CROSS_COMPILE_TARGET_arm arm-zephyr-eabi) set(CROSS_COMPILE_TARGET_nios2 nios2-zephyr-elf) -set(CROSS_COMPILE_TARGET_riscv32 riscv32-zephyr-elf) +set(CROSS_COMPILE_TARGET_riscv riscv32-zephyr-elf) set(CROSS_COMPILE_TARGET_mips mipsel-zephyr-elf) set(CROSS_COMPILE_TARGET_xtensa xtensa-zephyr-elf) set(CROSS_COMPILE_TARGET_arc arc-zephyr-elf) diff --git a/cmake/toolchain/zephyr/0.10.0/target.cmake b/cmake/toolchain/zephyr/0.10.0/target.cmake index 56e5e0b8ba9..2b45d3f52c9 100644 --- a/cmake/toolchain/zephyr/0.10.0/target.cmake +++ b/cmake/toolchain/zephyr/0.10.0/target.cmake @@ -9,7 +9,7 @@ endif() set(CROSS_COMPILE_TARGET_arm arm-zephyr-eabi) set(CROSS_COMPILE_TARGET_nios2 nios2-zephyr-elf) -set(CROSS_COMPILE_TARGET_riscv32 riscv32-zephyr-elf) +set(CROSS_COMPILE_TARGET_riscv riscv32-zephyr-elf) set(CROSS_COMPILE_TARGET_mips mipsel-zephyr-elf) set(CROSS_COMPILE_TARGET_xtensa xtensa-zephyr-elf) set(CROSS_COMPILE_TARGET_arc arc-zephyr-elf) diff --git a/cmake/toolchain/zephyr/0.10.1/target.cmake b/cmake/toolchain/zephyr/0.10.1/target.cmake index 2f57bd7c32c..81df3f8aa48 100644 --- a/cmake/toolchain/zephyr/0.10.1/target.cmake +++ b/cmake/toolchain/zephyr/0.10.1/target.cmake @@ -9,7 +9,7 @@ endif() set(CROSS_COMPILE_TARGET_arm arm-zephyr-eabi) set(CROSS_COMPILE_TARGET_nios2 nios2-zephyr-elf) -set(CROSS_COMPILE_TARGET_riscv32 riscv32-zephyr-elf) +set(CROSS_COMPILE_TARGET_riscv riscv32-zephyr-elf) set(CROSS_COMPILE_TARGET_mips mipsel-zephyr-elf) set(CROSS_COMPILE_TARGET_xtensa xtensa-zephyr-elf) set(CROSS_COMPILE_TARGET_arc arc-zephyr-elf) diff --git a/doc/conf.py b/doc/conf.py index eb94942f9e4..546e7d35255 100644 --- a/doc/conf.py +++ b/doc/conf.py @@ -402,10 +402,18 @@ html_redirect_pages = [ ('boards/nios2/altera_max10/doc/board', 'boards/nios2/altera_max10/doc/index'), ('boards/nios2/qemu_nios2/doc/board', 'boards/nios2/qemu_nios2/doc/index'), ('boards/posix/native_posix/doc/board', 'boards/posix/native_posix/doc/index'), - ('boards/riscv32/hifive1/doc/hifive1', 'boards/riscv32/hifive1/doc/index'), - ('boards/riscv32/m2gl025_miv/doc/m2g1025_miv', 'boards/riscv32/m2gl025_miv/doc/index'), - ('boards/riscv32/qemu_riscv32/doc/board', 'boards/riscv32/qemu_riscv32/doc/index'), - ('boards/riscv32/zedboard_pulpino/doc/zedboard_pulpino', 'boards/riscv32/zedboard_pulpino/doc/index'), + ('boards/riscv32/hifive1/doc/hifive1', 'boards/riscv/hifive1/doc/index'), + ('boards/riscv32/m2gl025_miv/doc/m2g1025_miv', 'boards/riscv/m2gl025_miv/doc/index'), + ('boards/riscv32/qemu_riscv32/doc/board', 'boards/riscv/qemu_riscv32/doc/index'), + ('boards/riscv32/zedboard_pulpino/doc/zedboard_pulpino', 'boards/riscv/zedboard_pulpino/doc/index'), + ('boards/riscv32/hifive1/doc/index', 'boards/riscv/hifive1/doc/index'), + ('boards/riscv32/hifive1_revb/doc/index', 'boards/riscv/hifive1_revb/doc/index'), + ('boards/riscv32/litex_vexriscv/doc/litex_vexriscv', 'boards/riscv/litex_vexriscv/doc/litex_vexriscv'), + ('boards/riscv32/m2gl025_miv/doc/index', 'boards/riscv/m2gl025_miv/doc/index'), + ('boards/riscv32/qemu_riscv32/doc/index', 'boards/riscv/qemu_riscv32/doc/index'), + ('boards/riscv32/rv32m1_vega/doc/index', 'boards/riscv/rv32m1_vega/doc/index'), + ('boards/x86/arduino_101/doc/board', 'boards/x86/arduino_101/doc/index'), + ('boards/x86/galileo/doc/galileo', 'boards/x86/galileo/doc/index'), ('boards/x86/minnowboard/doc/minnowboard', 'boards/x86/minnowboard/doc/index'), ('boards/x86/qemu_x86/doc/board', 'boards/x86/qemu_x86/doc/index'), ('boards/x86/tinytile/doc/board', 'boards/x86/tinytile/doc/index'), diff --git a/drivers/interrupt_controller/plic.c b/drivers/interrupt_controller/plic.c index 26f2e0fe63c..1cec889a1f2 100644 --- a/drivers/interrupt_controller/plic.c +++ b/drivers/interrupt_controller/plic.c @@ -100,7 +100,7 @@ int riscv_plic_irq_is_enabled(u32_t irq) * @brief Set priority of a riscv PLIC-specific interrupt line * * This routine set the priority of a RISCV PLIC-specific interrupt line. - * riscv_plic_irq_set_prio is called by riscv32 Z_ARCH_IRQ_CONNECT to set + * riscv_plic_irq_set_prio is called by riscv Z_ARCH_IRQ_CONNECT to set * the priority of an interrupt whenever CONFIG_RISCV_HAS_PLIC variable is set. * @param irq IRQ number for which to set priority * diff --git a/dts/riscv32/microsemi-miv.dtsi b/dts/riscv/microsemi-miv.dtsi similarity index 100% rename from dts/riscv32/microsemi-miv.dtsi rename to dts/riscv/microsemi-miv.dtsi diff --git a/dts/riscv32/riscv32-fe310.dtsi b/dts/riscv/riscv32-fe310.dtsi similarity index 100% rename from dts/riscv32/riscv32-fe310.dtsi rename to dts/riscv/riscv32-fe310.dtsi diff --git a/dts/riscv32/riscv32-litex-vexriscv.dtsi b/dts/riscv/riscv32-litex-vexriscv.dtsi similarity index 100% rename from dts/riscv32/riscv32-litex-vexriscv.dtsi rename to dts/riscv/riscv32-litex-vexriscv.dtsi diff --git a/dts/riscv32/rv32m1.dtsi b/dts/riscv/rv32m1.dtsi similarity index 100% rename from dts/riscv32/rv32m1.dtsi rename to dts/riscv/rv32m1.dtsi diff --git a/dts/riscv32/rv32m1_ri5cy.dtsi b/dts/riscv/rv32m1_ri5cy.dtsi similarity index 98% rename from dts/riscv32/rv32m1_ri5cy.dtsi rename to dts/riscv/rv32m1_ri5cy.dtsi index 713908069e7..4f464a21b34 100644 --- a/dts/riscv32/rv32m1_ri5cy.dtsi +++ b/dts/riscv/rv32m1_ri5cy.dtsi @@ -3,7 +3,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include / { aliases { diff --git a/dts/riscv32/rv32m1_zero_riscy.dtsi b/dts/riscv/rv32m1_zero_riscy.dtsi similarity index 98% rename from dts/riscv32/rv32m1_zero_riscy.dtsi rename to dts/riscv/rv32m1_zero_riscy.dtsi index f14f580b01f..2f5fb7dd544 100644 --- a/dts/riscv32/rv32m1_zero_riscy.dtsi +++ b/dts/riscv/rv32m1_zero_riscy.dtsi @@ -3,7 +3,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include / { aliases { diff --git a/include/arch/cpu.h b/include/arch/cpu.h index 8e219e8dca0..03d851006af 100644 --- a/include/arch/cpu.h +++ b/include/arch/cpu.h @@ -19,8 +19,8 @@ #include #elif defined(CONFIG_NIOS2) #include -#elif defined(CONFIG_RISCV32) -#include +#elif defined(CONFIG_RISCV) +#include #elif defined(CONFIG_XTENSA) #include #elif defined(CONFIG_ARCH_POSIX) diff --git a/include/arch/riscv32/arch.h b/include/arch/riscv/arch.h similarity index 91% rename from include/arch/riscv32/arch.h rename to include/arch/riscv/arch.h index edba48887e2..83ed6d4eb4a 100644 --- a/include/arch/riscv32/arch.h +++ b/include/arch/riscv/arch.h @@ -7,13 +7,13 @@ /** * @file - * @brief RISCV32 specific kernel interface header - * This header contains the RISCV32 specific kernel interface. It is + * @brief RISCV specific kernel interface header + * This header contains the RISCV specific kernel interface. It is * included by the generic kernel interface header (arch/cpu.h) */ -#ifndef ZEPHYR_INCLUDE_ARCH_RISCV32_ARCH_H_ -#define ZEPHYR_INCLUDE_ARCH_RISCV32_ARCH_H_ +#ifndef ZEPHYR_INCLUDE_ARCH_RISCV_ARCH_H_ +#define ZEPHYR_INCLUDE_ARCH_RISCV_ARCH_H_ #include "exp.h" #include @@ -37,7 +37,7 @@ extern "C" { #define STACK_ROUND_UP(x) ROUND_UP(x, STACK_ALIGN) #define STACK_ROUND_DOWN(x) ROUND_DOWN(x, STACK_ALIGN) -/* macros convert value of it's argument to a string */ +/* macros convert value of its argument to a string */ #define DO_TOSTR(s) #s #define TOSTR(s) DO_TOSTR(s) @@ -147,7 +147,7 @@ extern u32_t z_timer_cycle_get_32(void); #endif /*_ASMLANGUAGE */ #if defined(CONFIG_SOC_FAMILY_RISCV_PRIVILEGE) -#include +#include #endif #ifdef __cplusplus diff --git a/include/arch/riscv32/common/linker.ld b/include/arch/riscv/common/linker.ld similarity index 98% rename from include/arch/riscv32/common/linker.ld rename to include/arch/riscv/common/linker.ld index b1fb8e2991d..c429a17bb2c 100644 --- a/include/arch/riscv32/common/linker.ld +++ b/include/arch/riscv/common/linker.ld @@ -8,7 +8,7 @@ * @file * @brief Linker command/script file * - * Generic Linker script for the riscv32 platform + * Generic Linker script for the riscv platform */ #define _LINKER diff --git a/include/arch/riscv32/exp.h b/include/arch/riscv/exp.h similarity index 89% rename from include/arch/riscv32/exp.h rename to include/arch/riscv/exp.h index c8173ee3921..7b26b6b19b8 100644 --- a/include/arch/riscv32/exp.h +++ b/include/arch/riscv/exp.h @@ -7,13 +7,13 @@ /** * @file - * @brief RISCV32 public exception handling + * @brief RISCV public exception handling * - * RISCV32-specific kernel exception handling interface. + * RISCV-specific kernel exception handling interface. */ -#ifndef ZEPHYR_INCLUDE_ARCH_RISCV32_EXP_H_ -#define ZEPHYR_INCLUDE_ARCH_RISCV32_EXP_H_ +#ifndef ZEPHYR_INCLUDE_ARCH_RISCV_EXP_H_ +#define ZEPHYR_INCLUDE_ARCH_RISCV_EXP_H_ #ifdef __cplusplus extern "C" { @@ -81,4 +81,4 @@ typedef struct soc_esf soc_esf_t; } #endif -#endif /* ZEPHYR_INCLUDE_ARCH_RISCV32_EXP_H_ */ +#endif /* ZEPHYR_INCLUDE_ARCH_RISCV_EXP_H_ */ diff --git a/include/arch/riscv32/riscv-privilege/asm_inline.h b/include/arch/riscv/riscv-privilege/asm_inline.h similarity index 55% rename from include/arch/riscv32/riscv-privilege/asm_inline.h rename to include/arch/riscv/riscv-privilege/asm_inline.h index 54dadf0b57c..dd3239518b5 100644 --- a/include/arch/riscv32/riscv-privilege/asm_inline.h +++ b/include/arch/riscv/riscv-privilege/asm_inline.h @@ -5,8 +5,8 @@ * SPDX-License-Identifier: Apache-2.0 */ -#ifndef ZEPHYR_INCLUDE_ARCH_RISCV32_RISCV_PRIVILEGE_ASM_INLINE_H_ -#define ZEPHYR_INCLUDE_ARCH_RISCV32_RISCV_PRIVILEGE_ASM_INLINE_H_ +#ifndef ZEPHYR_INCLUDE_ARCH_RISCV_RISCV_PRIVILEGE_ASM_INLINE_H_ +#define ZEPHYR_INCLUDE_ARCH_RISCV_RISCV_PRIVILEGE_ASM_INLINE_H_ /* * The file must not be included directly @@ -14,9 +14,9 @@ */ #if defined(__GNUC__) -#include +#include #else #error "Supports only GNU C compiler" #endif -#endif /* ZEPHYR_INCLUDE_ARCH_RISCV32_RISCV_PRIVILEGE_ASM_INLINE_H_ */ +#endif /* ZEPHYR_INCLUDE_ARCH_RISCV_RISCV_PRIVILEGE_ASM_INLINE_H_ */ diff --git a/include/arch/riscv32/riscv-privilege/asm_inline_gcc.h b/include/arch/riscv/riscv-privilege/asm_inline_gcc.h similarity index 62% rename from include/arch/riscv32/riscv-privilege/asm_inline_gcc.h rename to include/arch/riscv/riscv-privilege/asm_inline_gcc.h index eb60dc0eac7..a62c1a2e4fd 100644 --- a/include/arch/riscv32/riscv-privilege/asm_inline_gcc.h +++ b/include/arch/riscv/riscv-privilege/asm_inline_gcc.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ -#ifndef ZEPHYR_INCLUDE_ARCH_RISCV32_RISCV_PRIVILEGE_ASM_INLINE_GCC_H_ -#define ZEPHYR_INCLUDE_ARCH_RISCV32_RISCV_PRIVILEGE_ASM_INLINE_GCC_H_ +#ifndef ZEPHYR_INCLUDE_ARCH_RISCV_RISCV_PRIVILEGE_ASM_INLINE_GCC_H_ +#define ZEPHYR_INCLUDE_ARCH_RISCV_RISCV_PRIVILEGE_ASM_INLINE_GCC_H_ #ifdef __cplusplus extern "C" { @@ -28,4 +28,4 @@ extern "C" { } #endif -#endif /* ZEPHYR_INCLUDE_ARCH_RISCV32_RISCV_PRIVILEGE_ASM_INLINE_GCC_H_ */ +#endif /* ZEPHYR_INCLUDE_ARCH_RISCV_RISCV_PRIVILEGE_ASM_INLINE_GCC_H_ */ diff --git a/include/linker/linker-tool-gcc.h b/include/linker/linker-tool-gcc.h index a0c44f1301c..015090e22ea 100644 --- a/include/linker/linker-tool-gcc.h +++ b/include/linker/linker-tool-gcc.h @@ -34,9 +34,13 @@ #endif #elif defined(CONFIG_NIOS2) OUTPUT_FORMAT("elf32-littlenios2", "elf32-bignios2", "elf32-littlenios2") -#elif defined(CONFIG_RISCV32) +#elif defined(CONFIG_RISCV) OUTPUT_ARCH("riscv") +#ifdef CONFIG_64BIT + OUTPUT_FORMAT("elf64-littleriscv") +#else OUTPUT_FORMAT("elf32-littleriscv") +#endif #elif defined(CONFIG_XTENSA) /* Not needed */ #elif defined(CONFIG_ARCH_POSIX) diff --git a/include/toolchain/common.h b/include/toolchain/common.h index f9b4a43bdb4..edbbe411521 100644 --- a/include/toolchain/common.h +++ b/include/toolchain/common.h @@ -70,7 +70,7 @@ #define PERFOPT_ALIGN .balign 4 - #elif defined(CONFIG_NIOS2) || defined(CONFIG_RISCV32) || \ + #elif defined(CONFIG_NIOS2) || defined(CONFIG_RISCV) || \ defined(CONFIG_XTENSA) #define PERFOPT_ALIGN .balign 4 diff --git a/include/toolchain/gcc.h b/include/toolchain/gcc.h index b45e5b2cfd3..615f1ed96b2 100644 --- a/include/toolchain/gcc.h +++ b/include/toolchain/gcc.h @@ -208,7 +208,7 @@ do { \ #if defined(_ASMLANGUAGE) && !defined(_LINKER) -#if defined(CONFIG_ARM) || defined(CONFIG_NIOS2) || defined(CONFIG_RISCV32) \ +#if defined(CONFIG_ARM) || defined(CONFIG_NIOS2) || defined(CONFIG_RISCV) \ || defined(CONFIG_XTENSA) #define GTEXT(sym) .global sym; .type sym, %function #define GDATA(sym) .global sym; .type sym, %object @@ -354,7 +354,7 @@ do { \ ",%0" \ "\n\t.type\t" #name ",@object" : : "n"(value)) -#elif defined(CONFIG_NIOS2) || defined(CONFIG_RISCV32) || defined(CONFIG_XTENSA) +#elif defined(CONFIG_NIOS2) || defined(CONFIG_RISCV) || defined(CONFIG_XTENSA) /* No special prefixes necessary for constants in this arch AFAICT */ #define GEN_ABSOLUTE_SYM(name, value) \ diff --git a/kernel/Kconfig b/kernel/Kconfig index 609e6b343fe..27f386a2a06 100644 --- a/kernel/Kconfig +++ b/kernel/Kconfig @@ -148,7 +148,7 @@ config SCHED_CPU_MASK config MAIN_STACK_SIZE int "Size of stack for initialization and main thread" default 2048 if COVERAGE_GCOV - default 512 if ZTEST && !RISCV32 + default 512 if ZTEST && !RISCV default 1024 help When the initialization is complete, the thread executing it then @@ -161,7 +161,7 @@ config IDLE_STACK_SIZE int "Size of stack for idle thread" default 2048 if COVERAGE_GCOV default 1024 if XTENSA - default 512 if RISCV32 + default 512 if RISCV default 320 if ARC || (ARM && CPU_HAS_FPU) default 256 help diff --git a/lib/libc/newlib/libc-hooks.c b/lib/libc/newlib/libc-hooks.c index 9e1be418737..2ca7911b9d4 100644 --- a/lib/libc/newlib/libc-hooks.c +++ b/lib/libc/newlib/libc-hooks.c @@ -42,7 +42,7 @@ MALLOC_BSS static unsigned char __aligned(CONFIG_NEWLIB_LIBC_ALIGNED_HEAP_SIZE) #include #define USED_RAM_SIZE (USED_RAM_END_ADDR - _RAM_ADDR) #define MAX_HEAP_SIZE (_RAM_SIZE - USED_RAM_SIZE) -#elif CONFIG_RISCV32 +#elif CONFIG_RISCV #include #define USED_RAM_SIZE (USED_RAM_END_ADDR - RISCV_RAM_BASE) #define MAX_HEAP_SIZE (RISCV_RAM_SIZE - USED_RAM_SIZE) diff --git a/soc/Kconfig b/soc/Kconfig index c695e2db053..78f0be73551 100644 --- a/soc/Kconfig +++ b/soc/Kconfig @@ -35,7 +35,7 @@ config SOC_COMPATIBLE_NRF52832 # SOC_*_LD: SoC specific Linker script additions # -if ARC || ARM || X86 || NIOS2 || RISCV32 +if ARC || ARM || X86 || NIOS2 || RISCV config SOC_NOINIT_LD bool @@ -70,4 +70,4 @@ config SOC_RWDATA_LD This only has effect if the SoC uses the common linker script under include/arch/. -endif # ARC || ARM || X86 || NIOS2 || RISCV32 +endif # ARC || ARM || X86 || NIOS2 || RISCV diff --git a/soc/riscv32/CMakeLists.txt b/soc/riscv/CMakeLists.txt similarity index 99% rename from soc/riscv32/CMakeLists.txt rename to soc/riscv/CMakeLists.txt index b42e9be8863..b826da926ca 100644 --- a/soc/riscv32/CMakeLists.txt +++ b/soc/riscv/CMakeLists.txt @@ -5,4 +5,3 @@ if(SOC_FAMILY) else() add_subdirectory(${SOC_NAME}) endif() - diff --git a/soc/riscv32/litex-vexriscv/CMakeLists.txt b/soc/riscv/litex-vexriscv/CMakeLists.txt similarity index 100% rename from soc/riscv32/litex-vexriscv/CMakeLists.txt rename to soc/riscv/litex-vexriscv/CMakeLists.txt diff --git a/soc/riscv32/litex-vexriscv/Kconfig.defconfig b/soc/riscv/litex-vexriscv/Kconfig.defconfig similarity index 100% rename from soc/riscv32/litex-vexriscv/Kconfig.defconfig rename to soc/riscv/litex-vexriscv/Kconfig.defconfig diff --git a/soc/riscv32/litex-vexriscv/Kconfig.soc b/soc/riscv/litex-vexriscv/Kconfig.soc similarity index 100% rename from soc/riscv32/litex-vexriscv/Kconfig.soc rename to soc/riscv/litex-vexriscv/Kconfig.soc diff --git a/soc/riscv32/litex-vexriscv/linker.ld b/soc/riscv/litex-vexriscv/linker.ld similarity index 72% rename from soc/riscv32/litex-vexriscv/linker.ld rename to soc/riscv/litex-vexriscv/linker.ld index c6f3699488a..29e121f55cb 100644 --- a/soc/riscv32/litex-vexriscv/linker.ld +++ b/soc/riscv/litex-vexriscv/linker.ld @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/riscv32/litex-vexriscv/soc.h b/soc/riscv/litex-vexriscv/soc.h similarity index 100% rename from soc/riscv32/litex-vexriscv/soc.h rename to soc/riscv/litex-vexriscv/soc.h diff --git a/soc/riscv32/openisa_rv32m1/CMakeLists.txt b/soc/riscv/openisa_rv32m1/CMakeLists.txt similarity index 100% rename from soc/riscv32/openisa_rv32m1/CMakeLists.txt rename to soc/riscv/openisa_rv32m1/CMakeLists.txt diff --git a/soc/riscv32/openisa_rv32m1/Kconfig b/soc/riscv/openisa_rv32m1/Kconfig similarity index 84% rename from soc/riscv32/openisa_rv32m1/Kconfig rename to soc/riscv/openisa_rv32m1/Kconfig index 94fa8365843..0508766c3d5 100644 --- a/soc/riscv32/openisa_rv32m1/Kconfig +++ b/soc/riscv/openisa_rv32m1/Kconfig @@ -2,7 +2,7 @@ # # SPDX-License-Identifier: Apache-2.0 -# The OpenISA RV32M1 SoC directory in riscv32 supports the RISC-V +# The OpenISA RV32M1 SoC directory in riscv supports the RISC-V # cores on OpenISA RV32M1 SoCs. # # The Zephyr "soc" abstraction isn't a great fit here. These SoCs (in @@ -11,7 +11,7 @@ # # However, due to constraints imposed by Zephyr's file hierarchy # conventions, those "other" cores would need to be supported under a -# different soc subdirectory, e.g. soc/arm instead of soc/riscv32. +# different soc subdirectory, e.g. soc/arm instead of soc/riscv. if SOC_OPENISA_RV32M1_RISCV32 diff --git a/soc/riscv32/openisa_rv32m1/Kconfig.defconfig b/soc/riscv/openisa_rv32m1/Kconfig.defconfig similarity index 97% rename from soc/riscv32/openisa_rv32m1/Kconfig.defconfig rename to soc/riscv/openisa_rv32m1/Kconfig.defconfig index 3614102bb79..aaff42f0a2a 100644 --- a/soc/riscv32/openisa_rv32m1/Kconfig.defconfig +++ b/soc/riscv/openisa_rv32m1/Kconfig.defconfig @@ -51,12 +51,12 @@ config WDOG_INIT # The event unit looks for vector tables at the end of each core's # flash space. These vector tables are not relocatable. -config RISCV32_RV32M1_VECTOR_BASE_ADDR +config RISCV_RV32M1_VECTOR_BASE_ADDR hex default 0x000FFF00 if SOC_OPENISA_RV32M1_RI5CY default 0x0103FF00 if SOC_OPENISA_RV32M1_ZERO_RISCY -config RISCV32_RV32M1_VECTOR_SIZE +config RISCV_RV32M1_VECTOR_SIZE hex default 0x100 diff --git a/soc/riscv32/openisa_rv32m1/Kconfig.soc b/soc/riscv/openisa_rv32m1/Kconfig.soc similarity index 97% rename from soc/riscv32/openisa_rv32m1/Kconfig.soc rename to soc/riscv/openisa_rv32m1/Kconfig.soc index 77f28c14672..15019754c07 100644 --- a/soc/riscv32/openisa_rv32m1/Kconfig.soc +++ b/soc/riscv/openisa_rv32m1/Kconfig.soc @@ -4,7 +4,7 @@ config SOC_OPENISA_RV32M1_RISCV32 bool "OpenISA RV32M1 RISC-V cores" - depends on RISCV32 + depends on RISCV # The following select is due to limitations in the linker script. # (We can't make it a 'depends on' without causing a dependency loop). select XIP diff --git a/soc/riscv32/openisa_rv32m1/dts_fixup.h b/soc/riscv/openisa_rv32m1/dts_fixup.h similarity index 100% rename from soc/riscv32/openisa_rv32m1/dts_fixup.h rename to soc/riscv/openisa_rv32m1/dts_fixup.h diff --git a/soc/riscv32/openisa_rv32m1/linker.ld b/soc/riscv/openisa_rv32m1/linker.ld similarity index 97% rename from soc/riscv32/openisa_rv32m1/linker.ld rename to soc/riscv/openisa_rv32m1/linker.ld index 8fe0aa6049a..0800b57fd08 100644 --- a/soc/riscv32/openisa_rv32m1/linker.ld +++ b/soc/riscv/openisa_rv32m1/linker.ld @@ -6,8 +6,8 @@ * This file is based on: * * - include/arch/arm/cortex_m/scripts/linker.ld - * - include/arch/riscv32/common/linker.ld - * - include/arch/riscv32/pulpino/linker.ld + * - include/arch/riscv/common/linker.ld + * - include/arch/riscv/pulpino/linker.ld * * SPDX-License-Identifier: Apache-2.0 */ @@ -29,7 +29,7 @@ #define ROMABLE_REGION ROM #define RAMABLE_REGION RAM -#define VECTOR_SIZE CONFIG_RISCV32_RV32M1_VECTOR_SIZE +#define VECTOR_SIZE CONFIG_RISCV_RV32M1_VECTOR_SIZE #ifdef CONFIG_USE_CODE_PARTITION diff --git a/soc/riscv32/openisa_rv32m1/soc.c b/soc/riscv/openisa_rv32m1/soc.c similarity index 100% rename from soc/riscv32/openisa_rv32m1/soc.c rename to soc/riscv/openisa_rv32m1/soc.c diff --git a/soc/riscv32/openisa_rv32m1/soc.h b/soc/riscv/openisa_rv32m1/soc.h similarity index 100% rename from soc/riscv32/openisa_rv32m1/soc.h rename to soc/riscv/openisa_rv32m1/soc.h diff --git a/soc/riscv32/openisa_rv32m1/soc_context.h b/soc/riscv/openisa_rv32m1/soc_context.h similarity index 100% rename from soc/riscv32/openisa_rv32m1/soc_context.h rename to soc/riscv/openisa_rv32m1/soc_context.h diff --git a/soc/riscv32/openisa_rv32m1/soc_irq.S b/soc/riscv/openisa_rv32m1/soc_irq.S similarity index 100% rename from soc/riscv32/openisa_rv32m1/soc_irq.S rename to soc/riscv/openisa_rv32m1/soc_irq.S diff --git a/soc/riscv32/openisa_rv32m1/soc_offsets.h b/soc/riscv/openisa_rv32m1/soc_offsets.h similarity index 100% rename from soc/riscv32/openisa_rv32m1/soc_offsets.h rename to soc/riscv/openisa_rv32m1/soc_offsets.h diff --git a/soc/riscv32/openisa_rv32m1/soc_ri5cy.h b/soc/riscv/openisa_rv32m1/soc_ri5cy.h similarity index 100% rename from soc/riscv32/openisa_rv32m1/soc_ri5cy.h rename to soc/riscv/openisa_rv32m1/soc_ri5cy.h diff --git a/soc/riscv32/openisa_rv32m1/soc_zero_riscy.h b/soc/riscv/openisa_rv32m1/soc_zero_riscy.h similarity index 100% rename from soc/riscv32/openisa_rv32m1/soc_zero_riscy.h rename to soc/riscv/openisa_rv32m1/soc_zero_riscy.h diff --git a/soc/riscv32/openisa_rv32m1/vector.S b/soc/riscv/openisa_rv32m1/vector.S similarity index 100% rename from soc/riscv32/openisa_rv32m1/vector.S rename to soc/riscv/openisa_rv32m1/vector.S diff --git a/soc/riscv32/openisa_rv32m1/wdog.S b/soc/riscv/openisa_rv32m1/wdog.S similarity index 100% rename from soc/riscv32/openisa_rv32m1/wdog.S rename to soc/riscv/openisa_rv32m1/wdog.S diff --git a/soc/riscv32/riscv-privilege/CMakeLists.txt b/soc/riscv/riscv-privilege/CMakeLists.txt similarity index 100% rename from soc/riscv32/riscv-privilege/CMakeLists.txt rename to soc/riscv/riscv-privilege/CMakeLists.txt diff --git a/soc/riscv32/riscv-privilege/Kconfig b/soc/riscv/riscv-privilege/Kconfig similarity index 92% rename from soc/riscv32/riscv-privilege/Kconfig rename to soc/riscv/riscv-privilege/Kconfig index 5d56a880843..7278c403ad5 100644 --- a/soc/riscv32/riscv-privilege/Kconfig +++ b/soc/riscv/riscv-privilege/Kconfig @@ -22,4 +22,4 @@ config RISCV_HAS_PLIC Does the SOC provide support for a Platform Level Interrupt Controller -source "soc/riscv32/riscv-privilege/*/Kconfig.soc" +source "soc/riscv/riscv-privilege/*/Kconfig.soc" diff --git a/soc/riscv32/riscv-privilege/Kconfig.defconfig b/soc/riscv/riscv-privilege/Kconfig.defconfig similarity index 74% rename from soc/riscv32/riscv-privilege/Kconfig.defconfig rename to soc/riscv/riscv-privilege/Kconfig.defconfig index 88b2819e3f6..e4f9de07f63 100644 --- a/soc/riscv32/riscv-privilege/Kconfig.defconfig +++ b/soc/riscv/riscv-privilege/Kconfig.defconfig @@ -4,4 +4,4 @@ # # SPDX-License-Identifier: Apache-2.0 # -source "soc/riscv32/riscv-privilege/*/Kconfig.defconfig.series" +source "soc/riscv/riscv-privilege/*/Kconfig.defconfig.series" diff --git a/soc/riscv32/riscv-privilege/Kconfig.soc b/soc/riscv/riscv-privilege/Kconfig.soc similarity index 77% rename from soc/riscv32/riscv-privilege/Kconfig.soc rename to soc/riscv/riscv-privilege/Kconfig.soc index 87fc63fdb83..72625e803a7 100644 --- a/soc/riscv32/riscv-privilege/Kconfig.soc +++ b/soc/riscv/riscv-privilege/Kconfig.soc @@ -5,4 +5,4 @@ # SPDX-License-Identifier: Apache-2.0 # -source "soc/riscv32/riscv-privilege/*/Kconfig.series" +source "soc/riscv/riscv-privilege/*/Kconfig.series" diff --git a/soc/riscv32/riscv-privilege/common/CMakeLists.txt b/soc/riscv/riscv-privilege/common/CMakeLists.txt similarity index 100% rename from soc/riscv32/riscv-privilege/common/CMakeLists.txt rename to soc/riscv/riscv-privilege/common/CMakeLists.txt diff --git a/soc/riscv32/riscv-privilege/common/idle.c b/soc/riscv/riscv-privilege/common/idle.c similarity index 100% rename from soc/riscv32/riscv-privilege/common/idle.c rename to soc/riscv/riscv-privilege/common/idle.c diff --git a/soc/riscv32/riscv-privilege/common/soc_common.h b/soc/riscv/riscv-privilege/common/soc_common.h similarity index 100% rename from soc/riscv32/riscv-privilege/common/soc_common.h rename to soc/riscv/riscv-privilege/common/soc_common.h diff --git a/soc/riscv32/riscv-privilege/common/soc_common_irq.c b/soc/riscv/riscv-privilege/common/soc_common_irq.c similarity index 100% rename from soc/riscv32/riscv-privilege/common/soc_common_irq.c rename to soc/riscv/riscv-privilege/common/soc_common_irq.c diff --git a/soc/riscv32/riscv-privilege/common/soc_irq.S b/soc/riscv/riscv-privilege/common/soc_irq.S similarity index 100% rename from soc/riscv32/riscv-privilege/common/soc_irq.S rename to soc/riscv/riscv-privilege/common/soc_irq.S diff --git a/soc/riscv32/riscv-privilege/common/vector.S b/soc/riscv/riscv-privilege/common/vector.S similarity index 100% rename from soc/riscv32/riscv-privilege/common/vector.S rename to soc/riscv/riscv-privilege/common/vector.S diff --git a/soc/riscv32/riscv-privilege/miv/CMakeLists.txt b/soc/riscv/riscv-privilege/miv/CMakeLists.txt similarity index 100% rename from soc/riscv32/riscv-privilege/miv/CMakeLists.txt rename to soc/riscv/riscv-privilege/miv/CMakeLists.txt diff --git a/soc/riscv32/riscv-privilege/miv/Kconfig.defconfig.series b/soc/riscv/riscv-privilege/miv/Kconfig.defconfig.series similarity index 100% rename from soc/riscv32/riscv-privilege/miv/Kconfig.defconfig.series rename to soc/riscv/riscv-privilege/miv/Kconfig.defconfig.series diff --git a/soc/riscv32/riscv-privilege/miv/Kconfig.series b/soc/riscv/riscv-privilege/miv/Kconfig.series similarity index 93% rename from soc/riscv32/riscv-privilege/miv/Kconfig.series rename to soc/riscv/riscv-privilege/miv/Kconfig.series index 3f0a4fbebeb..e6704df1857 100644 --- a/soc/riscv32/riscv-privilege/miv/Kconfig.series +++ b/soc/riscv/riscv-privilege/miv/Kconfig.series @@ -7,7 +7,7 @@ config SOC_SERIES_RISCV32_MIV bool "Microsemi Mi-V implementation" - depends on RISCV32 + depends on RISCV select SOC_FAMILY_RISCV_PRIVILEGE help Enable support for Microsemi Mi-V diff --git a/soc/riscv32/riscv-privilege/miv/Kconfig.soc b/soc/riscv/riscv-privilege/miv/Kconfig.soc similarity index 100% rename from soc/riscv32/riscv-privilege/miv/Kconfig.soc rename to soc/riscv/riscv-privilege/miv/Kconfig.soc diff --git a/soc/riscv32/riscv-privilege/miv/dts_fixup.h b/soc/riscv/riscv-privilege/miv/dts_fixup.h similarity index 99% rename from soc/riscv32/riscv-privilege/miv/dts_fixup.h rename to soc/riscv/riscv-privilege/miv/dts_fixup.h index d59b510b884..77de5c83cf8 100644 --- a/soc/riscv32/riscv-privilege/miv/dts_fixup.h +++ b/soc/riscv/riscv-privilege/miv/dts_fixup.h @@ -16,4 +16,3 @@ #define DT_MIV_UART_0_CLOCK_FREQUENCY DT_MICROSEMI_COREUART_70001000_CLOCK_FREQUENCY #define DT_MIV_UART_0_BAUD_RATE DT_MICROSEMI_COREUART_70001000_CURRENT_SPEED #define DT_MIV_UART_0_NAME DT_MICROSEMI_COREUART_70001000_LABEL - diff --git a/soc/riscv32/riscv-privilege/miv/linker.ld b/soc/riscv/riscv-privilege/miv/linker.ld similarity index 70% rename from soc/riscv32/riscv-privilege/miv/linker.ld rename to soc/riscv/riscv-privilege/miv/linker.ld index 8ddbffd17de..85e12127189 100644 --- a/soc/riscv32/riscv-privilege/miv/linker.ld +++ b/soc/riscv/riscv-privilege/miv/linker.ld @@ -4,4 +4,4 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include diff --git a/soc/riscv32/riscv-privilege/miv/soc.h b/soc/riscv/riscv-privilege/miv/soc.h similarity index 100% rename from soc/riscv32/riscv-privilege/miv/soc.h rename to soc/riscv/riscv-privilege/miv/soc.h diff --git a/soc/riscv32/riscv-privilege/sifive-freedom/CMakeLists.txt b/soc/riscv/riscv-privilege/sifive-freedom/CMakeLists.txt similarity index 100% rename from soc/riscv32/riscv-privilege/sifive-freedom/CMakeLists.txt rename to soc/riscv/riscv-privilege/sifive-freedom/CMakeLists.txt diff --git a/soc/riscv32/riscv-privilege/sifive-freedom/Kconfig.defconfig.series b/soc/riscv/riscv-privilege/sifive-freedom/Kconfig.defconfig.series similarity index 100% rename from soc/riscv32/riscv-privilege/sifive-freedom/Kconfig.defconfig.series rename to soc/riscv/riscv-privilege/sifive-freedom/Kconfig.defconfig.series diff --git a/soc/riscv32/riscv-privilege/sifive-freedom/Kconfig.series b/soc/riscv/riscv-privilege/sifive-freedom/Kconfig.series similarity index 94% rename from soc/riscv32/riscv-privilege/sifive-freedom/Kconfig.series rename to soc/riscv/riscv-privilege/sifive-freedom/Kconfig.series index 19f9d8d8040..4ba73b1b6ab 100644 --- a/soc/riscv32/riscv-privilege/sifive-freedom/Kconfig.series +++ b/soc/riscv/riscv-privilege/sifive-freedom/Kconfig.series @@ -7,7 +7,7 @@ config SOC_SERIES_RISCV32_SIFIVE_FREEDOM bool "SiFive Freedom SOC implementation" - depends on RISCV32 + depends on RISCV select SOC_FAMILY_RISCV_PRIVILEGE help Enable support for SiFive Freedom SOC diff --git a/soc/riscv32/riscv-privilege/sifive-freedom/Kconfig.soc b/soc/riscv/riscv-privilege/sifive-freedom/Kconfig.soc similarity index 100% rename from soc/riscv32/riscv-privilege/sifive-freedom/Kconfig.soc rename to soc/riscv/riscv-privilege/sifive-freedom/Kconfig.soc diff --git a/soc/riscv32/riscv-privilege/sifive-freedom/fe310_clock.c b/soc/riscv/riscv-privilege/sifive-freedom/fe310_clock.c similarity index 100% rename from soc/riscv32/riscv-privilege/sifive-freedom/fe310_clock.c rename to soc/riscv/riscv-privilege/sifive-freedom/fe310_clock.c diff --git a/soc/riscv32/riscv-privilege/sifive-freedom/fe310_prci.h b/soc/riscv/riscv-privilege/sifive-freedom/fe310_prci.h similarity index 100% rename from soc/riscv32/riscv-privilege/sifive-freedom/fe310_prci.h rename to soc/riscv/riscv-privilege/sifive-freedom/fe310_prci.h diff --git a/soc/riscv32/riscv-privilege/sifive-freedom/linker.ld b/soc/riscv/riscv-privilege/sifive-freedom/linker.ld similarity index 81% rename from soc/riscv32/riscv-privilege/sifive-freedom/linker.ld rename to soc/riscv/riscv-privilege/sifive-freedom/linker.ld index f0dfc64bb8f..d766f7fcbfd 100644 --- a/soc/riscv32/riscv-privilege/sifive-freedom/linker.ld +++ b/soc/riscv/riscv-privilege/sifive-freedom/linker.ld @@ -8,4 +8,4 @@ * @brief Linker script for the SiFive Freedom processor */ -#include +#include diff --git a/soc/riscv32/riscv-privilege/sifive-freedom/soc.h b/soc/riscv/riscv-privilege/sifive-freedom/soc.h similarity index 100% rename from soc/riscv32/riscv-privilege/sifive-freedom/soc.h rename to soc/riscv/riscv-privilege/sifive-freedom/soc.h diff --git a/subsys/debug/openocd.c b/subsys/debug/openocd.c index dc79dd49d64..15bd2ad9b87 100644 --- a/subsys/debug/openocd.c +++ b/subsys/debug/openocd.c @@ -56,7 +56,7 @@ size_t _kernel_openocd_offsets[] = { #elif defined(CONFIG_NIOS2) [OPENOCD_OFFSET_T_STACK_PTR] = offsetof(struct k_thread, callee_saved.sp), -#elif defined(CONFIG_RISCV32) +#elif defined(CONFIG_RISCV) [OPENOCD_OFFSET_T_STACK_PTR] = offsetof(struct k_thread, callee_saved.sp), #else diff --git a/subsys/logging/log_core.c b/subsys/logging/log_core.c index cdb0182eeba..244f2bda060 100644 --- a/subsys/logging/log_core.c +++ b/subsys/logging/log_core.c @@ -131,7 +131,7 @@ static bool is_rodata(const void *addr) extern const char *_image_rodata_end[]; #define RO_START _image_rodata_start #define RO_END _image_rodata_end -#elif defined(CONFIG_NIOS2) || defined(CONFIG_RISCV32) +#elif defined(CONFIG_NIOS2) || defined(CONFIG_RISCV) extern const char *_image_rom_start[]; extern const char *_image_rom_end[]; #define RO_START _image_rom_start diff --git a/subsys/testsuite/include/test_asm_inline_gcc.h b/subsys/testsuite/include/test_asm_inline_gcc.h index fdc1ca15007..518952eebd3 100644 --- a/subsys/testsuite/include/test_asm_inline_gcc.h +++ b/subsys/testsuite/include/test_asm_inline_gcc.h @@ -44,7 +44,7 @@ static inline void timestamp_serialize(void) #define timestamp_serialize() #elif defined(CONFIG_NIOS2) #define timestamp_serialize() -#elif defined(CONFIG_RISCV32) +#elif defined(CONFIG_RISCV) #define timestamp_serialize() #else #error implementation of timestamp_serialize() not provided for your CPU target diff --git a/tests/kernel/context/src/main.c b/tests/kernel/context/src/main.c index 25887ae96f6..14b96db44b6 100644 --- a/tests/kernel/context/src/main.c +++ b/tests/kernel/context/src/main.c @@ -86,11 +86,11 @@ #error Timer type is not defined for this platform #endif -/* Nios II and RISCV32 without CONFIG_RISCV_HAS_CPU_IDLE +/* Nios II and RISCV without CONFIG_RISCV_HAS_CPU_IDLE * do have a power saving instruction, so k_cpu_idle() returns immediately */ #if !defined(CONFIG_NIOS2) && \ - (!defined(CONFIG_RISCV32) || defined(CONFIG_RISCV_HAS_CPU_IDLE)) + (!defined(CONFIG_RISCV) || defined(CONFIG_RISCV_HAS_CPU_IDLE)) #define HAS_POWERSAVE_INSTRUCTION #endif diff --git a/tests/kernel/fatal/src/main.c b/tests/kernel/fatal/src/main.c index bea9c60f411..d32463e350d 100644 --- a/tests/kernel/fatal/src/main.c +++ b/tests/kernel/fatal/src/main.c @@ -59,7 +59,7 @@ void alt_thread1(void) #elif defined(CONFIG_ARC) __asm__ volatile ("swi"); #else - /* Triggers usage fault on ARM, illegal instruction on RISCV32 + /* Triggers usage fault on ARM, illegal instruction on RISCV * and xtensa */ { diff --git a/tests/kernel/gen_isr_table/src/main.c b/tests/kernel/gen_isr_table/src/main.c index 182bf9176f5..41ff54654f1 100644 --- a/tests/kernel/gen_isr_table/src/main.c +++ b/tests/kernel/gen_isr_table/src/main.c @@ -18,7 +18,7 @@ extern u32_t _irq_vector_table[]; #define ISR1_OFFSET 0 #define ISR2_OFFSET 1 -#if defined(CONFIG_RISCV32) +#if defined(CONFIG_RISCV) /* RISC-V has very few IRQ lines which can be triggered from software */ #define ISR3_OFFSET 1 #define ISR5_OFFSET 5 @@ -56,7 +56,7 @@ void trigger_irq(int irq) NVIC->STIR = irq; #endif } -#elif defined(CONFIG_RISCV32) +#elif defined(CONFIG_RISCV) void trigger_irq(int irq) { u32_t mip; diff --git a/tests/kernel/interrupt/src/interrupt.h b/tests/kernel/interrupt/src/interrupt.h index 26718a68d6a..d6987e10e98 100644 --- a/tests/kernel/interrupt/src/interrupt.h +++ b/tests/kernel/interrupt/src/interrupt.h @@ -22,7 +22,7 @@ static void trigger_irq(int irq) #endif } -#elif defined(CONFIG_RISCV32) +#elif defined(CONFIG_RISCV) static void trigger_irq(int irq) { u32_t mip; diff --git a/tests/kernel/mem_pool/mem_pool_concept/src/test_mpool.h b/tests/kernel/mem_pool/mem_pool_concept/src/test_mpool.h index 12e316e8059..cad8e687399 100644 --- a/tests/kernel/mem_pool/mem_pool_concept/src/test_mpool.h +++ b/tests/kernel/mem_pool/mem_pool_concept/src/test_mpool.h @@ -5,7 +5,7 @@ */ #define TIMEOUT 2000 -#ifdef CONFIG_RISCV32 +#ifdef CONFIG_RISCV #define STACK_SIZE (1024 + CONFIG_TEST_EXTRA_STACKSIZE) #else #define STACK_SIZE (512 + CONFIG_TEST_EXTRA_STACKSIZE)