riscv32: rename to riscv
With the upcoming riscv64 support, it is best to use "riscv" as the subdirectory name and common symbols as riscv32 and riscv64 support code is almost identical. Then later decide whether 32-bit or 64-bit compilation is wanted. Redirects for the web documentation are also included. Then zephyrbot complained about this: " New files added that are not covered in CODEOWNERS: dts/riscv/microsemi-miv.dtsi dts/riscv/riscv32-fe310.dtsi Please add one or more entries in the CODEOWNERS file to cover those files " So I assigned them to those who created them. Feel free to readjust as necessary. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
This commit is contained in:
Nicolas Pitre
Andrew Boie
parent
48b4ad4b33
commit
1f4b5ddd0f
159 changed files with 125 additions and 118 deletions
282
soc/riscv/openisa_rv32m1/linker.ld
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282
soc/riscv/openisa_rv32m1/linker.ld
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/*
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* Copyright (c) 2013-2014 Wind River Systems, Inc.
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* Copyright (c) 2016-2017 Jean-Paul Etienne <fractalclone@gmail.com>
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* Copyright (c) 2018 Foundries.io Ltd
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*
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* This file is based on:
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*
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* - include/arch/arm/cortex_m/scripts/linker.ld
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* - include/arch/riscv/common/linker.ld
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* - include/arch/riscv/pulpino/linker.ld
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define _LINKER
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#define _ASMLANGUAGE
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#include <generated_dts_board.h>
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#include <autoconf.h>
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#include <linker/sections.h>
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#include <linker/linker-defs.h>
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#include <linker/linker-tool.h>
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/*
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* Extra efforts would need to be taken to ensure the IRQ handlers are within
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* jumping distance of the vector table in non-XIP builds, so avoid them.
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*/
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#define ROMABLE_REGION ROM
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#define RAMABLE_REGION RAM
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#define VECTOR_SIZE CONFIG_RISCV_RV32M1_VECTOR_SIZE
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#ifdef CONFIG_USE_CODE_PARTITION
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#ifdef CONFIG_BOOTLOADER_MCUBOOT
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#define ROM_BASE (DT_CODE_PARTITION_OFFSET)
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#define ROM_SIZE (DT_CODE_PARTITION_SIZE)
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#define VECTOR_BASE (ROM_BASE + CONFIG_TEXT_SECTION_OFFSET)
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#else
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#define ROM_BASE DT_CODE_PARTITION_OFFSET
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#define ROM_SIZE (DT_CODE_PARTITION_SIZE - VECTOR_SIZE)
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#define VECTOR_BASE (ROM_BASE + ROM_SIZE)
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#endif
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#else
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#define ROM_BASE DT_FLASH_BASE_ADDRESS
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#define ROM_SIZE (KB(DT_FLASH_SIZE) - VECTOR_SIZE)
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#define VECTOR_BASE (ROM_BASE + ROM_SIZE)
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#endif
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#define RAM_BASE DT_SRAM_BASE_ADDRESS
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#define RAM_SIZE KB(DT_SRAM_SIZE)
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MEMORY
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{
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ROM (rx) : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE
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/*
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* Each RISC-V core on this chip (RI5CY and ZERO-RISCY) has
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* a vector table at the end of its flash bank. They are relocatable
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* at runtime, but we need to put the reset vectors in hardcoded places.
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*
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* (The Arm core vector tables are at the beginning of each
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* flash bank.)
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*/
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#ifndef CONFIG_BOOTLOADER_MCUBOOT
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VECTORS (rx) : ORIGIN = VECTOR_BASE, LENGTH = VECTOR_SIZE
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#endif
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RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE
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/*
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* Special section, not included in the final binary, used
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* to generate interrupt tables. See include/linker/intlist.ld.
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*/
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IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K
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}
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ENTRY(CONFIG_KERNEL_ENTRY)
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SECTIONS
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{
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#include <linker/rel-sections.ld>
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SECTION_PROLOGUE(.plt,,)
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{
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*(.plt)
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}
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SECTION_PROLOGUE(.iplt,,)
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{
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*(.iplt)
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}
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GROUP_START(ROM)
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_image_rom_start = ROM_BASE;
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SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)
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{
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. = CONFIG_TEXT_SECTION_OFFSET;
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. = ALIGN(4);
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/*
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* Respect for CONFIG_TEXT_SECTION_OFFSET is mandatory
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* for MCUboot support, so .reset.* and .exception.*
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* must come after that offset from ROM_BASE.
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*/
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#ifdef CONFIG_BOOTLOADER_MCUBOOT
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/*
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* For CONFIG_BOOTLOADER_MCUBOOT, the vector table is located at the
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* end of the image header of the MCUboot. After the tagert image is
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* boot, the register Machine Trap-Vector Base Address (MTVEC) is
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* set with the value of _vector_start in the reset handler.
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*/
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_vector_start = .;
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KEEP(*(.vectors.*))
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_vector_end = .;
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. = ALIGN(4);
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#endif
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KEEP(*(.reset.*))
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KEEP(*(".exception.entry.*")) /* contains __irq_wrapper */
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*(".exception.other.*")
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KEEP(*(.openocd_debug))
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KEEP(*(".openocd_debug.*"))
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_image_text_start = .;
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*(.text .text.*)
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*(.gnu.linkonce.t.*)
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*(.eh_frame)
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} GROUP_LINK_IN(ROM)
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_image_text_end = .;
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_image_rodata_start = .;
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#include <linker/common-rom.ld>
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SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)
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{
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. = ALIGN(4);
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*(.srodata)
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*(".srodata.*")
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*(.rodata)
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*(.rodata.*)
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*(.gnu.linkonce.r.*)
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/* Located in generated directory. This file is populated by the
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* zephyr_linker_sources() Cmake function.
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*/
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#include <snippets-rodata.ld>
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} GROUP_LINK_IN(ROMABLE_REGION)
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_image_rodata_end = .;
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_image_rom_end = .;
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#ifndef CONFIG_BOOTLOADER_MCUBOOT
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/* The vector table goes into core-dependent flash locations. */
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SECTION_PROLOGUE(vectors,,)
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{
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_vector_start = .;
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KEEP(*(.vectors.*))
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} GROUP_LINK_IN(VECTORS)
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_vector_end = .;
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#endif
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GROUP_END(ROM)
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GROUP_START(RAM)
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SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)
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{
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. = ALIGN(4);
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_image_ram_start = .;
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__data_ram_start = .;
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*(.data)
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*(.data.*)
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*(.gnu.linkonce.s.*)
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/* https://groups.google.com/a/groups.riscv.org/d/msg/sw-dev/60IdaZj27dY/TKT3hbNlAgAJ */
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*(.sdata .sdata.* .gnu.linkonce.s.*)
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*(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
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/* Located in generated directory. This file is populated by the
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* zephyr_linker_sources() Cmake function.
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*/
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#include <snippets-rwdata.ld>
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} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
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#include <linker/common-ram.ld>
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__data_ram_end = .;
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__data_rom_start = LOADADDR(_DATA_SECTION_NAME);
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SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)
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{
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/*
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* For performance, BSS section is assumed to be 4 byte aligned and
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* a multiple of 4 bytes, so it can be cleared in words.
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*/
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. = ALIGN(4);
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__bss_start = .;
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*(.bss .bss.*)
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*(.sbss .sbss.*)
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COMMON_SYMBOLS
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/* Ensure 4 byte alignment for the entire section. */
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. = ALIGN(4);
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__bss_end = .;
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} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
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SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)
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{
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/*
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* This section is used for non-initialized objects that
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* will not be cleared during the boot process.
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*/
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*(.noinit .noinit.*)
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/* Located in generated directory. This file is populated by the
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* zephyr_linker_sources() Cmake function.
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*/
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#include <snippets-noinit.ld>
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} GROUP_LINK_IN(RAMABLE_REGION)
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/* Located in generated directory. This file is populated by the
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* zephyr_linker_sources() Cmake function.
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*/
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#include <snippets-ram-sections.ld>
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_image_ram_end = .;
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_end = .; /* end of image */
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GROUP_END(RAM)
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#ifdef CONFIG_CUSTOM_SECTIONS_LD
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/* Located in project source directory */
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#include <custom-sections.ld>
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#endif
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/* Located in generated directory. This file is populated by the
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* zephyr_linker_sources() Cmake function.
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*/
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#include <snippets-sections.ld>
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#ifdef CONFIG_GEN_ISR_TABLES
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/* Bogus section, post-processed during the build to initialize interrupts. */
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#include <linker/intlist.ld>
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#endif
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#include <linker/debug-sections.ld>
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SECTION_PROLOGUE(.riscv.attributes, 0,)
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{
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KEEP(*(.riscv.attributes))
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KEEP(*(.gnu.attributes))
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}
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/*
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* Pulpino toolchains emit these sections; we don't care about them,
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* but need to avoid build system warnings about orphaned sections.
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*/
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SECTION_PROLOGUE(.Pulp_Chip.Info,,)
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{
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*(.Pulp_Chip.*)
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}
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}
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