riscv32: rename to riscv

With the upcoming riscv64 support, it is best to use "riscv" as the
subdirectory name and common symbols as riscv32 and riscv64 support
code is almost identical. Then later decide whether 32-bit or 64-bit
compilation is wanted.

Redirects for the web documentation are also included.

Then zephyrbot complained about this:

"
New files added that are not covered in CODEOWNERS:

dts/riscv/microsemi-miv.dtsi
dts/riscv/riscv32-fe310.dtsi

Please add one or more entries in the CODEOWNERS file to cover
those files
"

So I assigned them to those who created them. Feel free to readjust
as necessary.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>

arch/riscv/include/kernel_arch_func.h

@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Private kernel definitions
+ *
+ * This file contains private kernel function/macro definitions and various
+ * other definitions for the RISCV processor architecture.
+ */
+
+#ifndef ZEPHYR_ARCH_RISCV_INCLUDE_KERNEL_ARCH_FUNC_H_
+#define ZEPHYR_ARCH_RISCV_INCLUDE_KERNEL_ARCH_FUNC_H_
+
+#include <soc.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef _ASMLANGUAGE
+void k_cpu_idle(void);
+void k_cpu_atomic_idle(unsigned int key);
+
+static ALWAYS_INLINE void kernel_arch_init(void)
+{
+	_kernel.irq_stack =
+		Z_THREAD_STACK_BUFFER(_interrupt_stack) + CONFIG_ISR_STACK_SIZE;
+}
+
+static ALWAYS_INLINE void
+z_set_thread_return_value(struct k_thread *thread, unsigned int value)
+{
+	thread->arch.swap_return_value = value;
+}
+
+FUNC_NORETURN void z_riscv_fatal_error(unsigned int reason,
+				       const z_arch_esf_t *esf);
+
+#define z_is_in_isr() (_kernel.nested != 0U)
+
+#ifdef CONFIG_IRQ_OFFLOAD
+int z_irq_do_offload(void);
+#endif
+
+#endif /* _ASMLANGUAGE */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ZEPHYR_ARCH_RISCV_INCLUDE_KERNEL_ARCH_FUNC_H_ */