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include: drivers: stm32 clock_control: Replace OPT by DOMAIN

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In the continuation of the previous commit, replace _OPT_ by _DOMAIN_
in macros relating to this feature.
hen, adapt drivers and tests to this new wording.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2022-08-04 11:08:15 +02:00 • committed by Carles Cufí
commit 1ef9e9eb9b
8 changed files with 88 additions and 88 deletions
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2
drivers/flash/flash_stm32_ospi.c
View file

@ -1581,7 +1581,7 @@ static int flash_stm32_ospi_init(const struct device *dev)
if (clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), if (clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
(clock_control_subsys_t) &dev_cfg->pclken[1], (clock_control_subsys_t) &dev_cfg->pclken[1],
NULL) != 0) { NULL) != 0) {
LOG_ERR("Could not select OSPI source clock pclk[1]"); LOG_ERR("Could not select OSPI domain clock pclk[1]");
return -EIO; return -EIO;
} }
if (clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), if (clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),

14
drivers/serial/uart_stm32.c
View file

@ -39,11 +39,11 @@
LOG_MODULE_REGISTER(uart_stm32, CONFIG_UART_LOG_LEVEL); LOG_MODULE_REGISTER(uart_stm32, CONFIG_UART_LOG_LEVEL);
/* This symbol takes the value 1 if one of the device instances */ /* This symbol takes the value 1 if one of the device instances */
/* is configured in dts with an optional clock */ /* is configured in dts with a domain clock */
#if STM32_DT_INST_DEV_OPT_CLOCK_SUPPORT #if STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT
#define STM32_UART_OPT_CLOCK_SUPPORT 1 #define STM32_UART_DOMAIN_CLOCK_SUPPORT 1
#else #else
#define STM32_UART_OPT_CLOCK_SUPPORT 0 #define STM32_UART_DOMAIN_CLOCK_SUPPORT 0
#endif #endif
#define HAS_LPUART_1 (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(lpuart1), \ #define HAS_LPUART_1 (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(lpuart1), \
@ -107,7 +107,7 @@ static inline void uart_stm32_set_baudrate(const struct device *dev, uint32_t ba
uint32_t clock_rate; uint32_t clock_rate;
/* Get clock rate */ /* Get clock rate */
if (IS_ENABLED(STM32_UART_OPT_CLOCK_SUPPORT) && (config->pclk_len > 1)) { if (IS_ENABLED(STM32_UART_DOMAIN_CLOCK_SUPPORT) && (config->pclk_len > 1)) {
if (clock_control_get_rate(data->clock, if (clock_control_get_rate(data->clock,
(clock_control_subsys_t)&config->pclken[1], (clock_control_subsys_t)&config->pclken[1],
&clock_rate) < 0) { &clock_rate) < 0) {
@ -1570,12 +1570,12 @@ static int uart_stm32_init(const struct device *dev)
return err; return err;
} }
if (IS_ENABLED(STM32_UART_OPT_CLOCK_SUPPORT) && (config->pclk_len > 1)) { if (IS_ENABLED(STM32_UART_DOMAIN_CLOCK_SUPPORT) && (config->pclk_len > 1)) {
err = clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), err = clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
(clock_control_subsys_t) &config->pclken[1], (clock_control_subsys_t) &config->pclken[1],
NULL); NULL);
if (err != 0) { if (err != 0) {
LOG_ERR("Could not select UART source clock"); LOG_ERR("Could not select UART domain clock");
return err; return err;
} }
} }

6
drivers/spi/spi_ll_stm32.c
View file

@ -485,7 +485,7 @@ static int spi_stm32_configure(const struct device *dev,
#endif #endif
} }
if (IS_ENABLED(STM32_SPI_OPT_CLOCK_SUPPORT) && (cfg->pclk_len > 1)) { if (IS_ENABLED(STM32_SPI_DOMAIN_CLOCK_SUPPORT) && (cfg->pclk_len > 1)) {
if (clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), if (clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
(clock_control_subsys_t) &cfg->pclken[1], &clock) < 0) { (clock_control_subsys_t) &cfg->pclken[1], &clock) < 0) {
LOG_ERR("Failed call clock_control_get_rate(pclk[1])"); LOG_ERR("Failed call clock_control_get_rate(pclk[1])");
@ -869,12 +869,12 @@ static int spi_stm32_init(const struct device *dev)
return err; return err;
} }
if (IS_ENABLED(STM32_SPI_OPT_CLOCK_SUPPORT) && (cfg->pclk_len > 1)) { if (IS_ENABLED(STM32_SPI_DOMAIN_CLOCK_SUPPORT) && (cfg->pclk_len > 1)) {
err = clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), err = clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
(clock_control_subsys_t) &cfg->pclken[1], (clock_control_subsys_t) &cfg->pclken[1],
NULL); NULL);
if (err < 0) { if (err < 0) {
LOG_ERR("Could not select SPI source clock"); LOG_ERR("Could not select SPI domain clock");
return err; return err;
} }
} }

8
drivers/spi/spi_ll_stm32.h
View file

@ -12,11 +12,11 @@
typedef void (*irq_config_func_t)(const struct device *port); typedef void (*irq_config_func_t)(const struct device *port);
/* This symbol takes the value 1 if one of the device instances */ /* This symbol takes the value 1 if one of the device instances */
/* is configured in dts with an optional clock */ /* is configured in dts with a domain clock */
#if STM32_DT_INST_DEV_OPT_CLOCK_SUPPORT #if STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT
#define STM32_SPI_OPT_CLOCK_SUPPORT 1 #define STM32_SPI_DOMAIN_CLOCK_SUPPORT 1
#else #else
#define STM32_SPI_OPT_CLOCK_SUPPORT 0 #define STM32_SPI_DOMAIN_CLOCK_SUPPORT 0
#endif #endif
struct spi_stm32_config { struct spi_stm32_config {

12
include/zephyr/drivers/clock_control/stm32_clock_control.h
View file

@ -345,13 +345,13 @@ struct stm32_pclken {
#define STM32_DT_INST_CLOCKS(inst) \ #define STM32_DT_INST_CLOCKS(inst) \
STM32_DT_CLOCKS(DT_DRV_INST(inst)) STM32_DT_CLOCKS(DT_DRV_INST(inst))
#define STM32_OPT_CLOCK_INST_SUPPORT(inst) DT_INST_CLOCKS_HAS_IDX(inst, 1) || #define STM32_DOMAIN_CLOCK_INST_SUPPORT(inst) DT_INST_CLOCKS_HAS_IDX(inst, 1) ||
#define STM32_DT_INST_DEV_OPT_CLOCK_SUPPORT \ #define STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT \
(DT_INST_FOREACH_STATUS_OKAY(STM32_OPT_CLOCK_INST_SUPPORT) 0) (DT_INST_FOREACH_STATUS_OKAY(STM32_DOMAIN_CLOCK_INST_SUPPORT) 0)
#define STM32_OPT_CLOCK_SUPPORT(id) DT_CLOCKS_HAS_IDX(DT_NODELABEL(id), 1) || #define STM32_DOMAIN_CLOCK_SUPPORT(id) DT_CLOCKS_HAS_IDX(DT_NODELABEL(id), 1) ||
#define STM32_DT_DEV_OPT_CLOCK_SUPPORT \ #define STM32_DT_DEV_DOMAIN_CLOCK_SUPPORT \
(DT_FOREACH_STATUS_OKAY(STM32_OPT_CLOCK_SUPPORT) 0) (DT_FOREACH_STATUS_OKAY(STM32_DOMAIN_CLOCK_SUPPORT) 0)
/** Clock source binding accessors */ /** Clock source binding accessors */

48
tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/src/test_stm32_clock_configuration.c
View file

@ -33,10 +33,10 @@ static void test_sysclk_freq(void)
#define DT_DRV_COMPAT st_stm32_i2c_v2 #define DT_DRV_COMPAT st_stm32_i2c_v2
#endif #endif
#if STM32_DT_INST_DEV_OPT_CLOCK_SUPPORT #if STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT
#define STM32_I2C_OPT_CLOCK_SUPPORT 1 #define STM32_I2C_DOMAIN_CLOCK_SUPPORT 1
#else #else
#define STM32_I2C_OPT_CLOCK_SUPPORT 0 #define STM32_I2C_DOMAIN_CLOCK_SUPPORT 0
#endif #endif
static void test_i2c_clk_config(void) static void test_i2c_clk_config(void)
@ -55,13 +55,13 @@ static void test_i2c_clk_config(void)
zassert_true(__HAL_RCC_I2C1_IS_CLK_ENABLED(), "I2C1 gating clock should be on"); zassert_true(__HAL_RCC_I2C1_IS_CLK_ENABLED(), "I2C1 gating clock should be on");
TC_PRINT("I2C1 gating clock on\n"); TC_PRINT("I2C1 gating clock on\n");
if (IS_ENABLED(STM32_I2C_OPT_CLOCK_SUPPORT) && DT_NUM_CLOCKS(DT_NODELABEL(i2c1)) > 1) { if (IS_ENABLED(STM32_I2C_DOMAIN_CLOCK_SUPPORT) && DT_NUM_CLOCKS(DT_NODELABEL(i2c1)) > 1) {
/* Test clock_on(ker_clk) */ /* Test clock_on(domain_clk) */
r = clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), r = clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
(clock_control_subsys_t) &pclken[1], (clock_control_subsys_t) &pclken[1],
NULL); NULL);
zassert_true((r == 0), "Could not enable I2C soure clock"); zassert_true((r == 0), "Could not enable I2C domain clock");
TC_PRINT("I2C1 source clock configured\n"); TC_PRINT("I2C1 domain clock configured\n");
/* Test clock source */ /* Test clock source */
dev_actual_clk_src = __HAL_RCC_GET_I2C1_SOURCE(); dev_actual_clk_src = __HAL_RCC_GET_I2C1_SOURCE();
@ -75,7 +75,7 @@ static void test_i2c_clk_config(void)
"Expected I2C src: SYSCLK (0x%lx). Actual I2C src: 0x%x", "Expected I2C src: SYSCLK (0x%lx). Actual I2C src: 0x%x",
RCC_I2C1CLKSOURCE_SYSCLK, dev_actual_clk_src); RCC_I2C1CLKSOURCE_SYSCLK, dev_actual_clk_src);
} else { } else {
zassert_true(0, "Unexpected src clk (%d)", dev_actual_clk_src); zassert_true(0, "Unexpected domain clk (%d)", dev_actual_clk_src);
} }
/* Test get_rate(srce clk) */ /* Test get_rate(srce clk) */
@ -92,7 +92,7 @@ static void test_i2c_clk_config(void)
TC_PRINT("I2C1 clock source rate: %d Hz\n", dev_dt_clk_freq); TC_PRINT("I2C1 clock source rate: %d Hz\n", dev_dt_clk_freq);
} else { } else {
zassert_true((DT_NUM_CLOCKS(DT_NODELABEL(i2c1)) == 1), "test config issue"); zassert_true((DT_NUM_CLOCKS(DT_NODELABEL(i2c1)) == 1), "test config issue");
/* No alt clock available, get rate from gating clock */ /* No domain clock available, get rate from gating clock */
/* Test get_rate */ /* Test get_rate */
r = clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), r = clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
@ -128,7 +128,7 @@ static void test_i2c_clk_config(void) {}
#undef DT_DRV_COMPAT #undef DT_DRV_COMPAT
#define DT_DRV_COMPAT st_stm32_lptim #define DT_DRV_COMPAT st_stm32_lptim
#if STM32_DT_INST_DEV_OPT_CLOCK_SUPPORT #if STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT
#define STM32_LPTIM_OPT_CLOCK_SUPPORT 1 #define STM32_LPTIM_OPT_CLOCK_SUPPORT 1
#else #else
#define STM32_LPTIM_OPT_CLOCK_SUPPORT 0 #define STM32_LPTIM_OPT_CLOCK_SUPPORT 0
@ -151,11 +151,11 @@ static void test_lptim_clk_config(void)
TC_PRINT("LPTIM1 gating clock on\n"); TC_PRINT("LPTIM1 gating clock on\n");
if (IS_ENABLED(STM32_LPTIM_OPT_CLOCK_SUPPORT) && DT_NUM_CLOCKS(DT_NODELABEL(lptim1)) > 1) { if (IS_ENABLED(STM32_LPTIM_OPT_CLOCK_SUPPORT) && DT_NUM_CLOCKS(DT_NODELABEL(lptim1)) > 1) {
/* Test clock_on(ker_clk) */ /* Test clock_on(domain_clk) */
r = clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), r = clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
(clock_control_subsys_t) &pclken[1], (clock_control_subsys_t) &pclken[1],
NULL); NULL);
zassert_true((r == 0), "Could not enable LPTIM1 soure clock"); zassert_true((r == 0), "Could not enable LPTIM1 domain clock");
TC_PRINT("LPTIM1 source clock configured\n"); TC_PRINT("LPTIM1 source clock configured\n");
/* Test clock source */ /* Test clock source */
@ -170,7 +170,7 @@ static void test_lptim_clk_config(void)
"Expected LPTIM1 src: LSI (0x%lx). Actual LPTIM1 src: 0x%x", "Expected LPTIM1 src: LSI (0x%lx). Actual LPTIM1 src: 0x%x",
RCC_LPTIM1CLKSOURCE_LSI, dev_actual_clk_src); RCC_LPTIM1CLKSOURCE_LSI, dev_actual_clk_src);
} else { } else {
zassert_true(0, "Unexpected src clk (%d)", dev_actual_clk_src); zassert_true(0, "Unexpected domain clk (%d)", dev_actual_clk_src);
} }
/* Test get_rate(srce clk) */ /* Test get_rate(srce clk) */
@ -187,7 +187,7 @@ static void test_lptim_clk_config(void)
TC_PRINT("LPTIM1 clock source rate: %d Hz\n", dev_dt_clk_freq); TC_PRINT("LPTIM1 clock source rate: %d Hz\n", dev_dt_clk_freq);
} else { } else {
zassert_true((DT_NUM_CLOCKS(DT_NODELABEL(lptim1)) == 1), "test config issue"); zassert_true((DT_NUM_CLOCKS(DT_NODELABEL(lptim1)) == 1), "test config issue");
/* No alt clock available, get rate from gating clock */ /* No domain clock available, get rate from gating clock */
/* Test get_rate */ /* Test get_rate */
r = clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), r = clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
@ -211,7 +211,7 @@ static void test_lptim_clk_config(void)
zassert_true(!__HAL_RCC_LPTIM1_IS_CLK_ENABLED(), "LPTIM1 gating clk should be off"); zassert_true(!__HAL_RCC_LPTIM1_IS_CLK_ENABLED(), "LPTIM1 gating clk should be off");
TC_PRINT("LPTIM1 gating clk off\n"); TC_PRINT("LPTIM1 gating clk off\n");
/* Test clock_off(srce) */ /* Test clock_off(domain clk) */
/* Not supported today */ /* Not supported today */
} }
#else #else
@ -223,10 +223,10 @@ static void test_lptim_clk_config(void) {}
#undef DT_DRV_COMPAT #undef DT_DRV_COMPAT
#define DT_DRV_COMPAT st_stm32_adc #define DT_DRV_COMPAT st_stm32_adc
#if STM32_DT_INST_DEV_OPT_CLOCK_SUPPORT #if STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT
#define STM32_ADC_OPT_CLOCK_SUPPORT 1 #define STM32_ADC_DOMAIN_CLOCK_SUPPORT 1
#else #else
#define STM32_ADC_OPT_CLOCK_SUPPORT 0 #define STM32_ADC_DOMAIN_CLOCK_SUPPORT 0
#endif #endif
#if defined(__HAL_RCC_GET_ADC12_SOURCE) #if defined(__HAL_RCC_GET_ADC12_SOURCE)
@ -271,12 +271,12 @@ static void test_adc_clk_config(void)
zassert_true(ADC_IS_CLK_ENABLED(), "ADC1 gating clock should be on"); zassert_true(ADC_IS_CLK_ENABLED(), "ADC1 gating clock should be on");
TC_PRINT("ADC1 gating clock on\n"); TC_PRINT("ADC1 gating clock on\n");
if (IS_ENABLED(STM32_ADC_OPT_CLOCK_SUPPORT) && DT_NUM_CLOCKS(DT_NODELABEL(adc1)) > 1) { if (IS_ENABLED(STM32_ADC_DOMAIN_CLOCK_SUPPORT) && DT_NUM_CLOCKS(DT_NODELABEL(adc1)) > 1) {
/* Test clock_on(ker_clk) */ /* Test clock_on(domain_clk) */
r = clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), r = clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
(clock_control_subsys_t) &pclken[1], (clock_control_subsys_t) &pclken[1],
NULL); NULL);
zassert_true((r == 0), "Could not enable ADC1 soure clock"); zassert_true((r == 0), "Could not enable ADC1 domain clock");
TC_PRINT("ADC1 source clock configured\n"); TC_PRINT("ADC1 source clock configured\n");
/* Test clock source */ /* Test clock source */
@ -309,10 +309,10 @@ static void test_adc_clk_config(void)
TC_PRINT("ADC1 clock source rate: %d Hz\n", dev_dt_clk_freq); TC_PRINT("ADC1 clock source rate: %d Hz\n", dev_dt_clk_freq);
} else { } else {
zassert_true((DT_NUM_CLOCKS(DT_NODELABEL(adc1)) == 1), "test config issue"); zassert_true((DT_NUM_CLOCKS(DT_NODELABEL(adc1)) == 1), "test config issue");
/* No alt clock available, don't check gating clock as for adc there is no /* No domain clock available, don't check gating clock as for adc there is no
* uniform way to verify via hal. * uniform way to verify via hal.
*/ */
TC_PRINT("ADC1 no alt clock defined. Skipped check\n"); TC_PRINT("ADC1 no domain clock defined. Skipped check\n");
} }
/* Test clock_off(reg_clk) */ /* Test clock_off(reg_clk) */
@ -323,7 +323,7 @@ static void test_adc_clk_config(void)
zassert_true(!ADC_IS_CLK_ENABLED(), "ADC1 gating clk should be off"); zassert_true(!ADC_IS_CLK_ENABLED(), "ADC1 gating clk should be off");
TC_PRINT("ADC1 gating clk off\n"); TC_PRINT("ADC1 gating clk off\n");
/* Test clock_off(srce) */ /* Test clock_off(domain clk) */
/* Not supported today */ /* Not supported today */
} }
#else #else

54
tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/src/test_stm32_clock_configuration.c
View file

@ -13,10 +13,10 @@ LOG_MODULE_REGISTER(test);
#define DT_DRV_COMPAT st_stm32_spi #define DT_DRV_COMPAT st_stm32_spi
#if STM32_DT_INST_DEV_OPT_CLOCK_SUPPORT #if STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT
#define STM32_SPI_OPT_CLOCK_SUPPORT 1 #define STM32_SPI_DOMAIN_CLOCK_SUPPORT 1
#else #else
#define STM32_SPI_OPT_CLOCK_SUPPORT 0 #define STM32_SPI_DOMAIN_CLOCK_SUPPORT 0
#endif #endif
#define DT_NO_CLOCK 0xFFFFU #define DT_NO_CLOCK 0xFFFFU
@ -38,7 +38,7 @@ static void test_spi_clk_config(void)
static const struct stm32_pclken pclken[] = STM32_DT_CLOCKS(DT_NODELABEL(spi1)); static const struct stm32_pclken pclken[] = STM32_DT_CLOCKS(DT_NODELABEL(spi1));
struct stm32_pclken spi1_reg_clk_cfg = pclken[0]; struct stm32_pclken spi1_reg_clk_cfg = pclken[0];
uint32_t spi1_actual_clk_src, spi1_dt_ker_clk_src; uint32_t spi1_actual_domain_clk, spi1_dt_domain_clk;
uint32_t spi1_dt_clk_freq, spi1_actual_clk_freq; uint32_t spi1_dt_clk_freq, spi1_actual_clk_freq;
int r; int r;
@ -50,42 +50,42 @@ static void test_spi_clk_config(void)
zassert_true(__HAL_RCC_SPI1_IS_CLK_ENABLED(), "SPI1 reg_clk should be on"); zassert_true(__HAL_RCC_SPI1_IS_CLK_ENABLED(), "SPI1 reg_clk should be on");
TC_PRINT("SPI1 reg_clk on\n"); TC_PRINT("SPI1 reg_clk on\n");
if (IS_ENABLED(STM32_SPI_OPT_CLOCK_SUPPORT) && DT_NUM_CLOCKS(DT_NODELABEL(spi1)) > 1) { if (IS_ENABLED(STM32_SPI_DOMAIN_CLOCK_SUPPORT) && DT_NUM_CLOCKS(DT_NODELABEL(spi1)) > 1) {
struct stm32_pclken spi1_ker_clk_cfg = pclken[1]; struct stm32_pclken spi1_domain_clk_cfg = pclken[1];
/* Select ker_clk as device source clock */ /* Select domain_clk as device source clock */
r = clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), r = clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
(clock_control_subsys_t) &spi1_ker_clk_cfg, (clock_control_subsys_t) &spi1_domain_clk_cfg,
NULL); NULL);
zassert_true((r == 0), "Could not enable SPI ker_clk"); zassert_true((r == 0), "Could not enable SPI domain_clk");
TC_PRINT("SPI1 ker_clk on\n"); TC_PRINT("SPI1 domain_clk on\n");
/* Test ker_clk is configured as device's source clock */ /* Test domain_clk is configured as device's source clock */
spi1_dt_ker_clk_src = COND_CODE_1(DT_CLOCKS_HAS_NAME(DT_NODELABEL(spi1), kernel), spi1_dt_domain_clk = COND_CODE_1(DT_CLOCKS_HAS_NAME(DT_NODELABEL(spi1), kernel),
(DT_CLOCKS_CELL_BY_NAME(DT_NODELABEL(spi1), (DT_CLOCKS_CELL_BY_NAME(DT_NODELABEL(spi1),
kernel, bus)), kernel, bus)),
(DT_NO_CLOCK)); (DT_NO_CLOCK));
spi1_actual_clk_src = __HAL_RCC_GET_SPI1_SOURCE(); spi1_actual_domain_clk = __HAL_RCC_GET_SPI1_SOURCE();
if (spi1_dt_ker_clk_src == STM32_SRC_PLL1_Q) { if (spi1_dt_domain_clk == STM32_SRC_PLL1_Q) {
zassert_equal(spi1_actual_clk_src, RCC_SPI123CLKSOURCE_PLL, zassert_equal(spi1_actual_domain_clk, RCC_SPI123CLKSOURCE_PLL,
"Expected SPI src: PLLQ (%d). Actual SPI src: %d", "Expected SPI src: PLLQ (%d). Actual SPI src: %d",
spi1_actual_clk_src, RCC_SPI123CLKSOURCE_PLL); spi1_actual_domain_clk, RCC_SPI123CLKSOURCE_PLL);
} else if (spi1_dt_ker_clk_src == STM32_SRC_PLL3_P) { } else if (spi1_dt_domain_clk == STM32_SRC_PLL3_P) {
zassert_equal(spi1_actual_clk_src, RCC_SPI123CLKSOURCE_PLL3, zassert_equal(spi1_actual_domain_clk, RCC_SPI123CLKSOURCE_PLL3,
"Expected SPI src: PLLQ (%d). Actual SPI src: %d", "Expected SPI src: PLLQ (%d). Actual SPI src: %d",
spi1_actual_clk_src, RCC_SPI123CLKSOURCE_PLL3); spi1_actual_domain_clk, RCC_SPI123CLKSOURCE_PLL3);
} else if (spi1_dt_ker_clk_src == STM32_SRC_CKPER) { } else if (spi1_dt_domain_clk == STM32_SRC_CKPER) {
zassert_equal(spi1_actual_clk_src, RCC_SPI123CLKSOURCE_CLKP, zassert_equal(spi1_actual_domain_clk, RCC_SPI123CLKSOURCE_CLKP,
"Expected SPI src: PLLQ (%d). Actual SPI src: %d", "Expected SPI src: PLLQ (%d). Actual SPI src: %d",
spi1_actual_clk_src, RCC_SPI123CLKSOURCE_CLKP); spi1_actual_domain_clk, RCC_SPI123CLKSOURCE_CLKP);
} else { } else {
zassert_true(1, "Unexpected ker_clk src(%d)", spi1_dt_ker_clk_src); zassert_true(1, "Unexpected domain_clk src(%d)", spi1_dt_domain_clk);
} }
/* Test get_rate(ker_clk) */ /* Test get_rate(domain_clk) */
r = clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), r = clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
(clock_control_subsys_t) &spi1_ker_clk_cfg, (clock_control_subsys_t) &spi1_domain_clk_cfg,
&spi1_dt_clk_freq); &spi1_dt_clk_freq);
zassert_true((r == 0), "Could not get SPI clk freq"); zassert_true((r == 0), "Could not get SPI clk freq");
@ -94,7 +94,7 @@ static void test_spi_clk_config(void)
"Expected SPI clk: (%d). Actual SPI clk: %d", "Expected SPI clk: (%d). Actual SPI clk: %d",
spi1_dt_clk_freq, spi1_actual_clk_freq); spi1_dt_clk_freq, spi1_actual_clk_freq);
} else { } else {
/* No alt clock available, get rate from reg_clk */ /* No domain clock available, get rate from reg_clk */
/* Test get_rate(reg_clk) */ /* Test get_rate(reg_clk) */
r = clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), r = clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
@ -118,7 +118,7 @@ static void test_spi_clk_config(void)
zassert_true(!__HAL_RCC_SPI1_IS_CLK_ENABLED(), "SPI1 reg_clk should be off"); zassert_true(!__HAL_RCC_SPI1_IS_CLK_ENABLED(), "SPI1 reg_clk should be off");
TC_PRINT("SPI1 reg_clk off\n"); TC_PRINT("SPI1 reg_clk off\n");
/* Test clock_off(ker_clk) */ /* Test clock_off(domain_clk) */
/* Not supported today */ /* Not supported today */
} }

32
tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/src/test_stm32_clock_configuration.c
View file

@ -13,10 +13,10 @@ LOG_MODULE_REGISTER(test);
#define DT_DRV_COMPAT st_stm32_spi #define DT_DRV_COMPAT st_stm32_spi
#if STM32_DT_INST_DEV_OPT_CLOCK_SUPPORT #if STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT
#define STM32_SPI_OPT_CLOCK_SUPPORT 1 #define STM32_SPI_DOMAIN_CLOCK_SUPPORT 1
#else #else
#define STM32_SPI_OPT_CLOCK_SUPPORT 0 #define STM32_SPI_DOMAIN_CLOCK_SUPPORT 0
#endif #endif
#define DT_NO_CLOCK 0xFFFFU #define DT_NO_CLOCK 0xFFFFU
@ -37,7 +37,7 @@ static void test_spi_clk_config(void)
{ {
static const struct stm32_pclken pclken[] = STM32_DT_CLOCKS(DT_NODELABEL(spi1)); static const struct stm32_pclken pclken[] = STM32_DT_CLOCKS(DT_NODELABEL(spi1));
uint32_t spi1_actual_clk_src; uint32_t spi1_actual_domain_clk;
uint32_t spi1_dt_clk_freq, spi1_actual_clk_freq; uint32_t spi1_dt_clk_freq, spi1_actual_clk_freq;
int r; int r;
@ -49,27 +49,27 @@ static void test_spi_clk_config(void)
zassert_true(__HAL_RCC_SPI1_IS_CLK_ENABLED(), "SPI1 gating clock should be on"); zassert_true(__HAL_RCC_SPI1_IS_CLK_ENABLED(), "SPI1 gating clock should be on");
TC_PRINT("SPI1 gating clock on\n"); TC_PRINT("SPI1 gating clock on\n");
if (IS_ENABLED(STM32_SPI_OPT_CLOCK_SUPPORT) && DT_NUM_CLOCKS(DT_NODELABEL(spi1)) > 1) { if (IS_ENABLED(STM32_SPI_DOMAIN_CLOCK_SUPPORT) && DT_NUM_CLOCKS(DT_NODELABEL(spi1)) > 1) {
/* Test clock_on(alt source) */ /* Test clock_on(domain source) */
r = clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), r = clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
(clock_control_subsys_t) &pclken[1], (clock_control_subsys_t) &pclken[1],
NULL); NULL);
zassert_true((r == 0), "Could not configure SPI source clk"); zassert_true((r == 0), "Could not configure SPI domain clk");
TC_PRINT("SPI1 clk source configured\n"); TC_PRINT("SPI1 domain clk configured\n");
/* Test clk source */ /* Test clk source */
spi1_actual_clk_src = __HAL_RCC_GET_SPI1_SOURCE(); spi1_actual_domain_clk = __HAL_RCC_GET_SPI1_SOURCE();
if (pclken[1].bus == STM32_SRC_HSI16) { if (pclken[1].bus == STM32_SRC_HSI16) {
zassert_equal(spi1_actual_clk_src, RCC_SPI1CLKSOURCE_HSI, zassert_equal(spi1_actual_domain_clk, RCC_SPI1CLKSOURCE_HSI,
"Expected SPI src: HSI (%d). Actual SPI src: %d", "Expected SPI src: HSI (%d). Actual SPI src: %d",
RCC_SPI1CLKSOURCE_HSI, spi1_actual_clk_src); RCC_SPI1CLKSOURCE_HSI, spi1_actual_domain_clk);
} else if (pclken[1].bus == STM32_SRC_SYSCLK) { } else if (pclken[1].bus == STM32_SRC_SYSCLK) {
zassert_equal(spi1_actual_clk_src, RCC_SPI1CLKSOURCE_SYSCLK, zassert_equal(spi1_actual_domain_clk, RCC_SPI1CLKSOURCE_SYSCLK,
"Expected SPI src: SYSCLK (%d). Actual SPI src: %d", "Expected SPI src: SYSCLK (%d). Actual SPI src: %d",
RCC_SPI1CLKSOURCE_SYSCLK, spi1_actual_clk_src); RCC_SPI1CLKSOURCE_SYSCLK, spi1_actual_domain_clk);
} else { } else {
zassert_true(1, "Unexpected clk src(%d)", spi1_actual_clk_src); zassert_true(1, "Unexpected clk src(%d)", spi1_actual_domain_clk);
} }
/* Test get_rate(source clk) */ /* Test get_rate(source clk) */
@ -83,7 +83,7 @@ static void test_spi_clk_config(void)
"Expected SPI clk: (%d). Actual SPI clk: %d", "Expected SPI clk: (%d). Actual SPI clk: %d",
spi1_dt_clk_freq, spi1_actual_clk_freq); spi1_dt_clk_freq, spi1_actual_clk_freq);
} else { } else {
/* No alt clock available, get rate from gating clock */ /* No domain clock available, get rate from gating clock */
/* Test get_rate(gating clock) */ /* Test get_rate(gating clock) */
r = clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), r = clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
@ -105,7 +105,7 @@ static void test_spi_clk_config(void)
zassert_true(!__HAL_RCC_SPI1_IS_CLK_ENABLED(), "SPI1 gating clock should be off"); zassert_true(!__HAL_RCC_SPI1_IS_CLK_ENABLED(), "SPI1 gating clock should be off");
TC_PRINT("SPI1 gating clock off\n"); TC_PRINT("SPI1 gating clock off\n");
/* Test clock_off(source clk) */ /* Test clock_off(domain clk) */
/* Not supported today */ /* Not supported today */
} }