From 1ef9e9eb9b04f06756e06d3b87e6fdce729b4c1c Mon Sep 17 00:00:00 2001 From: Erwan Gouriou Date: Thu, 4 Aug 2022 11:08:15 +0200 Subject: [PATCH] include: drivers: stm32 clock_control: Replace OPT by DOMAIN In the continuation of the previous commit, replace _OPT_ by _DOMAIN_ in macros relating to this feature. hen, adapt drivers and tests to this new wording. Signed-off-by: Erwan Gouriou --- drivers/flash/flash_stm32_ospi.c | 2 +- drivers/serial/uart_stm32.c | 14 ++--- drivers/spi/spi_ll_stm32.c | 6 +-- drivers/spi/spi_ll_stm32.h | 8 +-- .../clock_control/stm32_clock_control.h | 12 ++--- .../src/test_stm32_clock_configuration.c | 48 ++++++++--------- .../src/test_stm32_clock_configuration.c | 54 +++++++++---------- .../src/test_stm32_clock_configuration.c | 32 +++++------ 8 files changed, 88 insertions(+), 88 deletions(-) diff --git a/drivers/flash/flash_stm32_ospi.c b/drivers/flash/flash_stm32_ospi.c index e839526aa61..865dbd2a299 100644 --- a/drivers/flash/flash_stm32_ospi.c +++ b/drivers/flash/flash_stm32_ospi.c @@ -1581,7 +1581,7 @@ static int flash_stm32_ospi_init(const struct device *dev) if (clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), (clock_control_subsys_t) &dev_cfg->pclken[1], NULL) != 0) { - LOG_ERR("Could not select OSPI source clock pclk[1]"); + LOG_ERR("Could not select OSPI domain clock pclk[1]"); return -EIO; } if (clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), diff --git a/drivers/serial/uart_stm32.c b/drivers/serial/uart_stm32.c index 4dc463f796a..5c8ab00850b 100644 --- a/drivers/serial/uart_stm32.c +++ b/drivers/serial/uart_stm32.c @@ -39,11 +39,11 @@ LOG_MODULE_REGISTER(uart_stm32, CONFIG_UART_LOG_LEVEL); /* This symbol takes the value 1 if one of the device instances */ -/* is configured in dts with an optional clock */ -#if STM32_DT_INST_DEV_OPT_CLOCK_SUPPORT -#define STM32_UART_OPT_CLOCK_SUPPORT 1 +/* is configured in dts with a domain clock */ +#if STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT +#define STM32_UART_DOMAIN_CLOCK_SUPPORT 1 #else -#define STM32_UART_OPT_CLOCK_SUPPORT 0 +#define STM32_UART_DOMAIN_CLOCK_SUPPORT 0 #endif #define HAS_LPUART_1 (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(lpuart1), \ @@ -107,7 +107,7 @@ static inline void uart_stm32_set_baudrate(const struct device *dev, uint32_t ba uint32_t clock_rate; /* Get clock rate */ - if (IS_ENABLED(STM32_UART_OPT_CLOCK_SUPPORT) && (config->pclk_len > 1)) { + if (IS_ENABLED(STM32_UART_DOMAIN_CLOCK_SUPPORT) && (config->pclk_len > 1)) { if (clock_control_get_rate(data->clock, (clock_control_subsys_t)&config->pclken[1], &clock_rate) < 0) { @@ -1570,12 +1570,12 @@ static int uart_stm32_init(const struct device *dev) return err; } - if (IS_ENABLED(STM32_UART_OPT_CLOCK_SUPPORT) && (config->pclk_len > 1)) { + if (IS_ENABLED(STM32_UART_DOMAIN_CLOCK_SUPPORT) && (config->pclk_len > 1)) { err = clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), (clock_control_subsys_t) &config->pclken[1], NULL); if (err != 0) { - LOG_ERR("Could not select UART source clock"); + LOG_ERR("Could not select UART domain clock"); return err; } } diff --git a/drivers/spi/spi_ll_stm32.c b/drivers/spi/spi_ll_stm32.c index 61d3e171699..83a7108be36 100644 --- a/drivers/spi/spi_ll_stm32.c +++ b/drivers/spi/spi_ll_stm32.c @@ -485,7 +485,7 @@ static int spi_stm32_configure(const struct device *dev, #endif } - if (IS_ENABLED(STM32_SPI_OPT_CLOCK_SUPPORT) && (cfg->pclk_len > 1)) { + if (IS_ENABLED(STM32_SPI_DOMAIN_CLOCK_SUPPORT) && (cfg->pclk_len > 1)) { if (clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), (clock_control_subsys_t) &cfg->pclken[1], &clock) < 0) { LOG_ERR("Failed call clock_control_get_rate(pclk[1])"); @@ -869,12 +869,12 @@ static int spi_stm32_init(const struct device *dev) return err; } - if (IS_ENABLED(STM32_SPI_OPT_CLOCK_SUPPORT) && (cfg->pclk_len > 1)) { + if (IS_ENABLED(STM32_SPI_DOMAIN_CLOCK_SUPPORT) && (cfg->pclk_len > 1)) { err = clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), (clock_control_subsys_t) &cfg->pclken[1], NULL); if (err < 0) { - LOG_ERR("Could not select SPI source clock"); + LOG_ERR("Could not select SPI domain clock"); return err; } } diff --git a/drivers/spi/spi_ll_stm32.h b/drivers/spi/spi_ll_stm32.h index 38c5342047c..bd2a6d2fe30 100644 --- a/drivers/spi/spi_ll_stm32.h +++ b/drivers/spi/spi_ll_stm32.h @@ -12,11 +12,11 @@ typedef void (*irq_config_func_t)(const struct device *port); /* This symbol takes the value 1 if one of the device instances */ -/* is configured in dts with an optional clock */ -#if STM32_DT_INST_DEV_OPT_CLOCK_SUPPORT -#define STM32_SPI_OPT_CLOCK_SUPPORT 1 +/* is configured in dts with a domain clock */ +#if STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT +#define STM32_SPI_DOMAIN_CLOCK_SUPPORT 1 #else -#define STM32_SPI_OPT_CLOCK_SUPPORT 0 +#define STM32_SPI_DOMAIN_CLOCK_SUPPORT 0 #endif struct spi_stm32_config { diff --git a/include/zephyr/drivers/clock_control/stm32_clock_control.h b/include/zephyr/drivers/clock_control/stm32_clock_control.h index 25e3baf4adb..735ca704ea4 100644 --- a/include/zephyr/drivers/clock_control/stm32_clock_control.h +++ b/include/zephyr/drivers/clock_control/stm32_clock_control.h @@ -345,13 +345,13 @@ struct stm32_pclken { #define STM32_DT_INST_CLOCKS(inst) \ STM32_DT_CLOCKS(DT_DRV_INST(inst)) -#define STM32_OPT_CLOCK_INST_SUPPORT(inst) DT_INST_CLOCKS_HAS_IDX(inst, 1) || -#define STM32_DT_INST_DEV_OPT_CLOCK_SUPPORT \ - (DT_INST_FOREACH_STATUS_OKAY(STM32_OPT_CLOCK_INST_SUPPORT) 0) +#define STM32_DOMAIN_CLOCK_INST_SUPPORT(inst) DT_INST_CLOCKS_HAS_IDX(inst, 1) || +#define STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT \ + (DT_INST_FOREACH_STATUS_OKAY(STM32_DOMAIN_CLOCK_INST_SUPPORT) 0) -#define STM32_OPT_CLOCK_SUPPORT(id) DT_CLOCKS_HAS_IDX(DT_NODELABEL(id), 1) || -#define STM32_DT_DEV_OPT_CLOCK_SUPPORT \ - (DT_FOREACH_STATUS_OKAY(STM32_OPT_CLOCK_SUPPORT) 0) +#define STM32_DOMAIN_CLOCK_SUPPORT(id) DT_CLOCKS_HAS_IDX(DT_NODELABEL(id), 1) || +#define STM32_DT_DEV_DOMAIN_CLOCK_SUPPORT \ + (DT_FOREACH_STATUS_OKAY(STM32_DOMAIN_CLOCK_SUPPORT) 0) /** Clock source binding accessors */ diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/src/test_stm32_clock_configuration.c b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/src/test_stm32_clock_configuration.c index 8ce71eef9c0..dd8dac96ea3 100644 --- a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/src/test_stm32_clock_configuration.c +++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/src/test_stm32_clock_configuration.c @@ -33,10 +33,10 @@ static void test_sysclk_freq(void) #define DT_DRV_COMPAT st_stm32_i2c_v2 #endif -#if STM32_DT_INST_DEV_OPT_CLOCK_SUPPORT -#define STM32_I2C_OPT_CLOCK_SUPPORT 1 +#if STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT +#define STM32_I2C_DOMAIN_CLOCK_SUPPORT 1 #else -#define STM32_I2C_OPT_CLOCK_SUPPORT 0 +#define STM32_I2C_DOMAIN_CLOCK_SUPPORT 0 #endif static void test_i2c_clk_config(void) @@ -55,13 +55,13 @@ static void test_i2c_clk_config(void) zassert_true(__HAL_RCC_I2C1_IS_CLK_ENABLED(), "I2C1 gating clock should be on"); TC_PRINT("I2C1 gating clock on\n"); - if (IS_ENABLED(STM32_I2C_OPT_CLOCK_SUPPORT) && DT_NUM_CLOCKS(DT_NODELABEL(i2c1)) > 1) { - /* Test clock_on(ker_clk) */ + if (IS_ENABLED(STM32_I2C_DOMAIN_CLOCK_SUPPORT) && DT_NUM_CLOCKS(DT_NODELABEL(i2c1)) > 1) { + /* Test clock_on(domain_clk) */ r = clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), (clock_control_subsys_t) &pclken[1], NULL); - zassert_true((r == 0), "Could not enable I2C soure clock"); - TC_PRINT("I2C1 source clock configured\n"); + zassert_true((r == 0), "Could not enable I2C domain clock"); + TC_PRINT("I2C1 domain clock configured\n"); /* Test clock source */ dev_actual_clk_src = __HAL_RCC_GET_I2C1_SOURCE(); @@ -75,7 +75,7 @@ static void test_i2c_clk_config(void) "Expected I2C src: SYSCLK (0x%lx). Actual I2C src: 0x%x", RCC_I2C1CLKSOURCE_SYSCLK, dev_actual_clk_src); } else { - zassert_true(0, "Unexpected src clk (%d)", dev_actual_clk_src); + zassert_true(0, "Unexpected domain clk (%d)", dev_actual_clk_src); } /* Test get_rate(srce clk) */ @@ -92,7 +92,7 @@ static void test_i2c_clk_config(void) TC_PRINT("I2C1 clock source rate: %d Hz\n", dev_dt_clk_freq); } else { zassert_true((DT_NUM_CLOCKS(DT_NODELABEL(i2c1)) == 1), "test config issue"); - /* No alt clock available, get rate from gating clock */ + /* No domain clock available, get rate from gating clock */ /* Test get_rate */ r = clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), @@ -128,7 +128,7 @@ static void test_i2c_clk_config(void) {} #undef DT_DRV_COMPAT #define DT_DRV_COMPAT st_stm32_lptim -#if STM32_DT_INST_DEV_OPT_CLOCK_SUPPORT +#if STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT #define STM32_LPTIM_OPT_CLOCK_SUPPORT 1 #else #define STM32_LPTIM_OPT_CLOCK_SUPPORT 0 @@ -151,11 +151,11 @@ static void test_lptim_clk_config(void) TC_PRINT("LPTIM1 gating clock on\n"); if (IS_ENABLED(STM32_LPTIM_OPT_CLOCK_SUPPORT) && DT_NUM_CLOCKS(DT_NODELABEL(lptim1)) > 1) { - /* Test clock_on(ker_clk) */ + /* Test clock_on(domain_clk) */ r = clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), (clock_control_subsys_t) &pclken[1], NULL); - zassert_true((r == 0), "Could not enable LPTIM1 soure clock"); + zassert_true((r == 0), "Could not enable LPTIM1 domain clock"); TC_PRINT("LPTIM1 source clock configured\n"); /* Test clock source */ @@ -170,7 +170,7 @@ static void test_lptim_clk_config(void) "Expected LPTIM1 src: LSI (0x%lx). Actual LPTIM1 src: 0x%x", RCC_LPTIM1CLKSOURCE_LSI, dev_actual_clk_src); } else { - zassert_true(0, "Unexpected src clk (%d)", dev_actual_clk_src); + zassert_true(0, "Unexpected domain clk (%d)", dev_actual_clk_src); } /* Test get_rate(srce clk) */ @@ -187,7 +187,7 @@ static void test_lptim_clk_config(void) TC_PRINT("LPTIM1 clock source rate: %d Hz\n", dev_dt_clk_freq); } else { zassert_true((DT_NUM_CLOCKS(DT_NODELABEL(lptim1)) == 1), "test config issue"); - /* No alt clock available, get rate from gating clock */ + /* No domain clock available, get rate from gating clock */ /* Test get_rate */ r = clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), @@ -211,7 +211,7 @@ static void test_lptim_clk_config(void) zassert_true(!__HAL_RCC_LPTIM1_IS_CLK_ENABLED(), "LPTIM1 gating clk should be off"); TC_PRINT("LPTIM1 gating clk off\n"); - /* Test clock_off(srce) */ + /* Test clock_off(domain clk) */ /* Not supported today */ } #else @@ -223,10 +223,10 @@ static void test_lptim_clk_config(void) {} #undef DT_DRV_COMPAT #define DT_DRV_COMPAT st_stm32_adc -#if STM32_DT_INST_DEV_OPT_CLOCK_SUPPORT -#define STM32_ADC_OPT_CLOCK_SUPPORT 1 +#if STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT +#define STM32_ADC_DOMAIN_CLOCK_SUPPORT 1 #else -#define STM32_ADC_OPT_CLOCK_SUPPORT 0 +#define STM32_ADC_DOMAIN_CLOCK_SUPPORT 0 #endif #if defined(__HAL_RCC_GET_ADC12_SOURCE) @@ -271,12 +271,12 @@ static void test_adc_clk_config(void) zassert_true(ADC_IS_CLK_ENABLED(), "ADC1 gating clock should be on"); TC_PRINT("ADC1 gating clock on\n"); - if (IS_ENABLED(STM32_ADC_OPT_CLOCK_SUPPORT) && DT_NUM_CLOCKS(DT_NODELABEL(adc1)) > 1) { - /* Test clock_on(ker_clk) */ + if (IS_ENABLED(STM32_ADC_DOMAIN_CLOCK_SUPPORT) && DT_NUM_CLOCKS(DT_NODELABEL(adc1)) > 1) { + /* Test clock_on(domain_clk) */ r = clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), (clock_control_subsys_t) &pclken[1], NULL); - zassert_true((r == 0), "Could not enable ADC1 soure clock"); + zassert_true((r == 0), "Could not enable ADC1 domain clock"); TC_PRINT("ADC1 source clock configured\n"); /* Test clock source */ @@ -309,10 +309,10 @@ static void test_adc_clk_config(void) TC_PRINT("ADC1 clock source rate: %d Hz\n", dev_dt_clk_freq); } else { zassert_true((DT_NUM_CLOCKS(DT_NODELABEL(adc1)) == 1), "test config issue"); - /* No alt clock available, don't check gating clock as for adc there is no + /* No domain clock available, don't check gating clock as for adc there is no * uniform way to verify via hal. */ - TC_PRINT("ADC1 no alt clock defined. Skipped check\n"); + TC_PRINT("ADC1 no domain clock defined. Skipped check\n"); } /* Test clock_off(reg_clk) */ @@ -323,7 +323,7 @@ static void test_adc_clk_config(void) zassert_true(!ADC_IS_CLK_ENABLED(), "ADC1 gating clk should be off"); TC_PRINT("ADC1 gating clk off\n"); - /* Test clock_off(srce) */ + /* Test clock_off(domain clk) */ /* Not supported today */ } #else diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/src/test_stm32_clock_configuration.c b/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/src/test_stm32_clock_configuration.c index b674b9d87a8..16fc2ca38a4 100644 --- a/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/src/test_stm32_clock_configuration.c +++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/src/test_stm32_clock_configuration.c @@ -13,10 +13,10 @@ LOG_MODULE_REGISTER(test); #define DT_DRV_COMPAT st_stm32_spi -#if STM32_DT_INST_DEV_OPT_CLOCK_SUPPORT -#define STM32_SPI_OPT_CLOCK_SUPPORT 1 +#if STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT +#define STM32_SPI_DOMAIN_CLOCK_SUPPORT 1 #else -#define STM32_SPI_OPT_CLOCK_SUPPORT 0 +#define STM32_SPI_DOMAIN_CLOCK_SUPPORT 0 #endif #define DT_NO_CLOCK 0xFFFFU @@ -38,7 +38,7 @@ static void test_spi_clk_config(void) static const struct stm32_pclken pclken[] = STM32_DT_CLOCKS(DT_NODELABEL(spi1)); struct stm32_pclken spi1_reg_clk_cfg = pclken[0]; - uint32_t spi1_actual_clk_src, spi1_dt_ker_clk_src; + uint32_t spi1_actual_domain_clk, spi1_dt_domain_clk; uint32_t spi1_dt_clk_freq, spi1_actual_clk_freq; int r; @@ -50,42 +50,42 @@ static void test_spi_clk_config(void) zassert_true(__HAL_RCC_SPI1_IS_CLK_ENABLED(), "SPI1 reg_clk should be on"); TC_PRINT("SPI1 reg_clk on\n"); - if (IS_ENABLED(STM32_SPI_OPT_CLOCK_SUPPORT) && DT_NUM_CLOCKS(DT_NODELABEL(spi1)) > 1) { - struct stm32_pclken spi1_ker_clk_cfg = pclken[1]; + if (IS_ENABLED(STM32_SPI_DOMAIN_CLOCK_SUPPORT) && DT_NUM_CLOCKS(DT_NODELABEL(spi1)) > 1) { + struct stm32_pclken spi1_domain_clk_cfg = pclken[1]; - /* Select ker_clk as device source clock */ + /* Select domain_clk as device source clock */ r = clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), - (clock_control_subsys_t) &spi1_ker_clk_cfg, + (clock_control_subsys_t) &spi1_domain_clk_cfg, NULL); - zassert_true((r == 0), "Could not enable SPI ker_clk"); - TC_PRINT("SPI1 ker_clk on\n"); + zassert_true((r == 0), "Could not enable SPI domain_clk"); + TC_PRINT("SPI1 domain_clk on\n"); - /* Test ker_clk is configured as device's source clock */ - spi1_dt_ker_clk_src = COND_CODE_1(DT_CLOCKS_HAS_NAME(DT_NODELABEL(spi1), kernel), + /* Test domain_clk is configured as device's source clock */ + spi1_dt_domain_clk = COND_CODE_1(DT_CLOCKS_HAS_NAME(DT_NODELABEL(spi1), kernel), (DT_CLOCKS_CELL_BY_NAME(DT_NODELABEL(spi1), kernel, bus)), (DT_NO_CLOCK)); - spi1_actual_clk_src = __HAL_RCC_GET_SPI1_SOURCE(); + spi1_actual_domain_clk = __HAL_RCC_GET_SPI1_SOURCE(); - if (spi1_dt_ker_clk_src == STM32_SRC_PLL1_Q) { - zassert_equal(spi1_actual_clk_src, RCC_SPI123CLKSOURCE_PLL, + if (spi1_dt_domain_clk == STM32_SRC_PLL1_Q) { + zassert_equal(spi1_actual_domain_clk, RCC_SPI123CLKSOURCE_PLL, "Expected SPI src: PLLQ (%d). Actual SPI src: %d", - spi1_actual_clk_src, RCC_SPI123CLKSOURCE_PLL); - } else if (spi1_dt_ker_clk_src == STM32_SRC_PLL3_P) { - zassert_equal(spi1_actual_clk_src, RCC_SPI123CLKSOURCE_PLL3, + spi1_actual_domain_clk, RCC_SPI123CLKSOURCE_PLL); + } else if (spi1_dt_domain_clk == STM32_SRC_PLL3_P) { + zassert_equal(spi1_actual_domain_clk, RCC_SPI123CLKSOURCE_PLL3, "Expected SPI src: PLLQ (%d). Actual SPI src: %d", - spi1_actual_clk_src, RCC_SPI123CLKSOURCE_PLL3); - } else if (spi1_dt_ker_clk_src == STM32_SRC_CKPER) { - zassert_equal(spi1_actual_clk_src, RCC_SPI123CLKSOURCE_CLKP, + spi1_actual_domain_clk, RCC_SPI123CLKSOURCE_PLL3); + } else if (spi1_dt_domain_clk == STM32_SRC_CKPER) { + zassert_equal(spi1_actual_domain_clk, RCC_SPI123CLKSOURCE_CLKP, "Expected SPI src: PLLQ (%d). Actual SPI src: %d", - spi1_actual_clk_src, RCC_SPI123CLKSOURCE_CLKP); + spi1_actual_domain_clk, RCC_SPI123CLKSOURCE_CLKP); } else { - zassert_true(1, "Unexpected ker_clk src(%d)", spi1_dt_ker_clk_src); + zassert_true(1, "Unexpected domain_clk src(%d)", spi1_dt_domain_clk); } - /* Test get_rate(ker_clk) */ + /* Test get_rate(domain_clk) */ r = clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), - (clock_control_subsys_t) &spi1_ker_clk_cfg, + (clock_control_subsys_t) &spi1_domain_clk_cfg, &spi1_dt_clk_freq); zassert_true((r == 0), "Could not get SPI clk freq"); @@ -94,7 +94,7 @@ static void test_spi_clk_config(void) "Expected SPI clk: (%d). Actual SPI clk: %d", spi1_dt_clk_freq, spi1_actual_clk_freq); } else { - /* No alt clock available, get rate from reg_clk */ + /* No domain clock available, get rate from reg_clk */ /* Test get_rate(reg_clk) */ r = clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), @@ -118,7 +118,7 @@ static void test_spi_clk_config(void) zassert_true(!__HAL_RCC_SPI1_IS_CLK_ENABLED(), "SPI1 reg_clk should be off"); TC_PRINT("SPI1 reg_clk off\n"); - /* Test clock_off(ker_clk) */ + /* Test clock_off(domain_clk) */ /* Not supported today */ } diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/src/test_stm32_clock_configuration.c b/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/src/test_stm32_clock_configuration.c index 13bfa105c33..251dc28b6c8 100644 --- a/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/src/test_stm32_clock_configuration.c +++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/src/test_stm32_clock_configuration.c @@ -13,10 +13,10 @@ LOG_MODULE_REGISTER(test); #define DT_DRV_COMPAT st_stm32_spi -#if STM32_DT_INST_DEV_OPT_CLOCK_SUPPORT -#define STM32_SPI_OPT_CLOCK_SUPPORT 1 +#if STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT +#define STM32_SPI_DOMAIN_CLOCK_SUPPORT 1 #else -#define STM32_SPI_OPT_CLOCK_SUPPORT 0 +#define STM32_SPI_DOMAIN_CLOCK_SUPPORT 0 #endif #define DT_NO_CLOCK 0xFFFFU @@ -37,7 +37,7 @@ static void test_spi_clk_config(void) { static const struct stm32_pclken pclken[] = STM32_DT_CLOCKS(DT_NODELABEL(spi1)); - uint32_t spi1_actual_clk_src; + uint32_t spi1_actual_domain_clk; uint32_t spi1_dt_clk_freq, spi1_actual_clk_freq; int r; @@ -49,27 +49,27 @@ static void test_spi_clk_config(void) zassert_true(__HAL_RCC_SPI1_IS_CLK_ENABLED(), "SPI1 gating clock should be on"); TC_PRINT("SPI1 gating clock on\n"); - if (IS_ENABLED(STM32_SPI_OPT_CLOCK_SUPPORT) && DT_NUM_CLOCKS(DT_NODELABEL(spi1)) > 1) { - /* Test clock_on(alt source) */ + if (IS_ENABLED(STM32_SPI_DOMAIN_CLOCK_SUPPORT) && DT_NUM_CLOCKS(DT_NODELABEL(spi1)) > 1) { + /* Test clock_on(domain source) */ r = clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), (clock_control_subsys_t) &pclken[1], NULL); - zassert_true((r == 0), "Could not configure SPI source clk"); - TC_PRINT("SPI1 clk source configured\n"); + zassert_true((r == 0), "Could not configure SPI domain clk"); + TC_PRINT("SPI1 domain clk configured\n"); /* Test clk source */ - spi1_actual_clk_src = __HAL_RCC_GET_SPI1_SOURCE(); + spi1_actual_domain_clk = __HAL_RCC_GET_SPI1_SOURCE(); if (pclken[1].bus == STM32_SRC_HSI16) { - zassert_equal(spi1_actual_clk_src, RCC_SPI1CLKSOURCE_HSI, + zassert_equal(spi1_actual_domain_clk, RCC_SPI1CLKSOURCE_HSI, "Expected SPI src: HSI (%d). Actual SPI src: %d", - RCC_SPI1CLKSOURCE_HSI, spi1_actual_clk_src); + RCC_SPI1CLKSOURCE_HSI, spi1_actual_domain_clk); } else if (pclken[1].bus == STM32_SRC_SYSCLK) { - zassert_equal(spi1_actual_clk_src, RCC_SPI1CLKSOURCE_SYSCLK, + zassert_equal(spi1_actual_domain_clk, RCC_SPI1CLKSOURCE_SYSCLK, "Expected SPI src: SYSCLK (%d). Actual SPI src: %d", - RCC_SPI1CLKSOURCE_SYSCLK, spi1_actual_clk_src); + RCC_SPI1CLKSOURCE_SYSCLK, spi1_actual_domain_clk); } else { - zassert_true(1, "Unexpected clk src(%d)", spi1_actual_clk_src); + zassert_true(1, "Unexpected clk src(%d)", spi1_actual_domain_clk); } /* Test get_rate(source clk) */ @@ -83,7 +83,7 @@ static void test_spi_clk_config(void) "Expected SPI clk: (%d). Actual SPI clk: %d", spi1_dt_clk_freq, spi1_actual_clk_freq); } else { - /* No alt clock available, get rate from gating clock */ + /* No domain clock available, get rate from gating clock */ /* Test get_rate(gating clock) */ r = clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), @@ -105,7 +105,7 @@ static void test_spi_clk_config(void) zassert_true(!__HAL_RCC_SPI1_IS_CLK_ENABLED(), "SPI1 gating clock should be off"); TC_PRINT("SPI1 gating clock off\n"); - /* Test clock_off(source clk) */ + /* Test clock_off(domain clk) */ /* Not supported today */ }