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dts: stm32: Add WWDG in STM32 dtsi files

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Added System WWDG support for STM32 devices.

Signed-off-by: Ioannis Konstantelias <ikonstadel@gmail.com>
This commit is contained in:
Ioannis Konstantelias 2019-07-15 15:36:31 +03:00 • committed by Kumar Gala
commit 1db2685b57
14 changed files with 151 additions and 0 deletions
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10
dts/arm/st/f0/stm32f0.dtsi
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@ -1,5 +1,6 @@
/* /*
* Copyright (c) 2017 RnDity Sp. z o.o. * Copyright (c) 2017 RnDity Sp. z o.o.
* Copyright (c) 2019 Centaur Analytics, Inc
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -164,6 +165,15 @@
label = "IWDG"; label = "IWDG";
}; };
wwdg: watchdog@40002c00 {
compatible = "st,stm32-window-watchdog";
reg = <0x40002C00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
label = "WWDG";
interrupts = <0 7>;
status = "disabled";
};
timers1: timers@40012c00 { timers1: timers@40012c00 {
compatible = "st,stm32-timers"; compatible = "st,stm32-timers";
reg = <0x40012c00 0x400>; reg = <0x40012c00 0x400>;

10
dts/arm/st/f1/stm32f1.dtsi
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@ -1,5 +1,6 @@
/* /*
* Copyright (c) 2017 Linaro Limited * Copyright (c) 2017 Linaro Limited
* Copyright (c) 2019 Centaur Analytics, Inc
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -162,6 +163,15 @@
status = "disabled"; status = "disabled";
}; };
wwdg: watchdog@40002c00 {
compatible = "st,stm32-window-watchdog";
reg = <0x40002C00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
label = "WWDG";
interrupts = <0 7>;
status = "disabled";
};
timers1: timers@40012c00 { timers1: timers@40012c00 {
compatible = "st,stm32-timers"; compatible = "st,stm32-timers";
reg = <0x40012c00 0x400>; reg = <0x40012c00 0x400>;

10
dts/arm/st/f2/stm32f2.dtsi
View file

@ -1,5 +1,6 @@
/* /*
* Copyright (c) 2018 qianfan Zhao * Copyright (c) 2018 qianfan Zhao
* Copyright (c) 2019 Centaur Analytics, Inc
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -145,6 +146,15 @@
status = "disabled"; status = "disabled";
}; };
wwdg: watchdog@40002c00 {
compatible = "st,stm32-window-watchdog";
reg = <0x40002C00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
label = "WWDG";
interrupts = <0 7>;
status = "disabled";
};
usart1: serial@40011000 { usart1: serial@40011000 {
compatible = "st,stm32-usart", "st,stm32-uart"; compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40011000 0x400>; reg = <0x40011000 0x400>;

10
dts/arm/st/f3/stm32f3.dtsi
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@ -1,5 +1,6 @@
/* /*
* Copyright (c) 2017 I-SENSE group of ICCS * Copyright (c) 2017 I-SENSE group of ICCS
* Copyright (c) 2019 Centaur Analytics, Inc
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -111,6 +112,15 @@
status = "disabled"; status = "disabled";
}; };
wwdg: watchdog@40002c00 {
compatible = "st,stm32-window-watchdog";
reg = <0x40002C00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
label = "WWDG";
interrupts = <0 7>;
status = "disabled";
};
usart1: serial@40013800 { usart1: serial@40013800 {
compatible = "st,stm32-usart", "st,stm32-uart"; compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>; reg = <0x40013800 0x400>;

10
dts/arm/st/f4/stm32f4.dtsi
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@ -1,5 +1,6 @@
/* /*
* Copyright (c) 2017 Linaro Limited * Copyright (c) 2017 Linaro Limited
* Copyright (c) 2019 Centaur Analytics, Inc
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -119,6 +120,15 @@
status = "disabled"; status = "disabled";
}; };
wwdg: watchdog@40002c00 {
compatible = "st,stm32-window-watchdog";
reg = <0x40002C00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
label = "WWDG";
interrupts = <0 7>;
status = "disabled";
};
usart1: serial@40011000 { usart1: serial@40011000 {
compatible = "st,stm32-usart", "st,stm32-uart"; compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40011000 0x400>; reg = <0x40011000 0x400>;

10
dts/arm/st/f7/stm32f7.dtsi
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@ -1,5 +1,6 @@
/* /*
* Copyright (c) 2018 Yurii Hamann * Copyright (c) 2018 Yurii Hamann
* Copyright (c) 2019 Centaur Analytics, Inc
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -149,6 +150,15 @@
status = "disabled"; status = "disabled";
}; };
wwdg: watchdog@40002c00 {
compatible = "st,stm32-window-watchdog";
reg = <0x40002C00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
label = "WWDG";
interrupts = <0 7>;
status = "disabled";
};
usart1: serial@40011000 { usart1: serial@40011000 {
compatible = "st,stm32-usart", "st,stm32-uart"; compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40011000 0x400>; reg = <0x40011000 0x400>;

10
dts/arm/st/g0/stm32g0.dtsi
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@ -1,6 +1,7 @@
/* /*
* Copyright (c) 2019 Philippe Retornaz <philippe@shapescale.com> * Copyright (c) 2019 Philippe Retornaz <philippe@shapescale.com>
* Copyright (c) 2019 ST Microelectronics * Copyright (c) 2019 ST Microelectronics
* Copyright (c) 2019 Centaur Analytics, Inc
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -104,6 +105,15 @@
}; };
}; };
wwdg: watchdog@40002c00 {
compatible = "st,stm32-window-watchdog";
reg = <0x40002C00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
label = "WWDG";
interrupts = <0 7>;
status = "disabled";
};
usart1: serial@40013800 { usart1: serial@40013800 {
compatible = "st,stm32-usart", "st,stm32-uart"; compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>; reg = <0x40013800 0x400>;

10
dts/arm/st/h7/stm32h7.dtsi
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@ -1,5 +1,6 @@
/* /*
* Copyright (c) 2019 Linaro Limited * Copyright (c) 2019 Linaro Limited
* Copyright (c) 2019 Centaur Analytics, Inc
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -157,6 +158,15 @@
}; };
}; };
wwdg1: watchdog@50003000 {
compatible = "st,stm32-window-watchdog";
reg = <0x50003000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000800>;
interrupts = <0 7>;
status = "disabled";
label = "WWDG_1";
};
usart1: serial@40011000 { usart1: serial@40011000 {
compatible = "st,stm32-usart", "st,stm32-uart"; compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40011000 0x400>; reg = <0x40011000 0x400>;

10
dts/arm/st/l0/stm32l0.dtsi
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@ -1,5 +1,6 @@
/* /*
* Copyright (c) 2018 Endre Karlson <endre.karlson@gmail.com> * Copyright (c) 2018 Endre Karlson <endre.karlson@gmail.com>
* Copyright (c) 2019 Centaur Analytics, Inc
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -110,6 +111,15 @@
status = "disabled"; status = "disabled";
}; };
wwdg: watchdog@40002c00 {
compatible = "st,stm32-window-watchdog";
reg = <0x40002C00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
label = "WWDG";
interrupts = <0 7>;
status = "disabled";
};
usart1: serial@40013800 { usart1: serial@40013800 {
compatible = "st,stm32-usart", "st,stm32-uart"; compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>; reg = <0x40013800 0x400>;

10
dts/arm/st/l1/stm32l1.dtsi
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@ -1,5 +1,6 @@
/* /*
* Copyright (c) 2019 Linaro Ltd. * Copyright (c) 2019 Linaro Ltd.
* Copyright (c) 2019 Centaur Analytics, Inc
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -141,6 +142,15 @@
}; };
}; };
wwdg: watchdog@40002c00 {
compatible = "st,stm32-window-watchdog";
reg = <0x40002C00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
interrupts = <0 7>;
status = "disabled";
label = "WWDG";
};
rcc: rcc@40023800 { rcc: rcc@40023800 {
compatible = "st,stm32-rcc"; compatible = "st,stm32-rcc";
#clock-cells = <2>; #clock-cells = <2>;

10
dts/arm/st/l4/stm32l4.dtsi
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@ -1,5 +1,6 @@
/* /*
* Copyright (c) 2017 Linaro Limited * Copyright (c) 2017 Linaro Limited
* Copyright (c) 2019 Centaur Analytics, Inc
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -103,6 +104,15 @@
status = "disabled"; status = "disabled";
}; };
wwdg: watchdog@40002c00 {
compatible = "st,stm32-window-watchdog";
reg = <0x40002C00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
label = "WWDG";
interrupts = <0 7>;
status = "disabled";
};
usart1: serial@40013800 { usart1: serial@40013800 {
compatible = "st,stm32-usart", "st,stm32-uart"; compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>; reg = <0x40013800 0x400>;

10
dts/arm/st/mp1/stm32mp157.dtsi
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@ -1,5 +1,6 @@
/* /*
* Copyright (c) 2019 STMicroelectronics * Copyright (c) 2019 STMicroelectronics
* Copyright (c) 2019 Centaur Analytics, Inc
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -148,6 +149,15 @@
}; };
}; };
wwdg1: watchdog@4000a000 {
compatible = "st,stm32-window-watchdog";
reg = <0x4000A000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
label = "WWDG_1";
interrupts = <0 7>;
status = "disabled";
};
spi1: spi@44004000 { spi1: spi@44004000 {
compatible = "st,stm32-spi-fifo"; compatible = "st,stm32-spi-fifo";
reg = <0x44004000 0x400>; reg = <0x44004000 0x400>;

10
dts/arm/st/wb/stm32wb.dtsi
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@ -1,5 +1,6 @@
/* /*
* Copyright (c) 2019 Linaro Limited * Copyright (c) 2019 Linaro Limited
* Copyright (c) 2019 Centaur Analytics, Inc
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -112,6 +113,15 @@
}; };
}; };
wwdg: watchdog@40002c00 {
compatible = "st,stm32-window-watchdog";
reg = <0x40002C00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
label = "WWDG";
interrupts = <0 7>;
status = "disabled";
};
usart1: serial@40013800 { usart1: serial@40013800 {
compatible = "st,stm32-usart", "st,stm32-uart"; compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>; reg = <0x40013800 0x400>;

21
dts/bindings/watchdog/st,stm32-window-watchdog.yaml Normal file
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@ -0,0 +1,21 @@
# Copyright (c) 2019 Centaur Analytics, Inc
# SPDX-License-Identifier: Apache-2.0
title: STMicroelectronics STM32 system window watchdog driver
description: >
This is a representation of the STM32 system window watchdog
compatible: "st,stm32-window-watchdog"
include: base.yaml
properties:
reg:
required: true
label:
required: true
clocks:
required: true