diff --git a/dts/arm/st/f0/stm32f0.dtsi b/dts/arm/st/f0/stm32f0.dtsi index 36d35b1ae6f..4115801e5ea 100644 --- a/dts/arm/st/f0/stm32f0.dtsi +++ b/dts/arm/st/f0/stm32f0.dtsi @@ -1,5 +1,6 @@ /* * Copyright (c) 2017 RnDity Sp. z o.o. + * Copyright (c) 2019 Centaur Analytics, Inc * * SPDX-License-Identifier: Apache-2.0 */ @@ -164,6 +165,15 @@ label = "IWDG"; }; + wwdg: watchdog@40002c00 { + compatible = "st,stm32-window-watchdog"; + reg = <0x40002C00 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>; + label = "WWDG"; + interrupts = <0 7>; + status = "disabled"; + }; + timers1: timers@40012c00 { compatible = "st,stm32-timers"; reg = <0x40012c00 0x400>; diff --git a/dts/arm/st/f1/stm32f1.dtsi b/dts/arm/st/f1/stm32f1.dtsi index 215f5a2b59e..ca5dde36af5 100644 --- a/dts/arm/st/f1/stm32f1.dtsi +++ b/dts/arm/st/f1/stm32f1.dtsi @@ -1,5 +1,6 @@ /* * Copyright (c) 2017 Linaro Limited + * Copyright (c) 2019 Centaur Analytics, Inc * * SPDX-License-Identifier: Apache-2.0 */ @@ -162,6 +163,15 @@ status = "disabled"; }; + wwdg: watchdog@40002c00 { + compatible = "st,stm32-window-watchdog"; + reg = <0x40002C00 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>; + label = "WWDG"; + interrupts = <0 7>; + status = "disabled"; + }; + timers1: timers@40012c00 { compatible = "st,stm32-timers"; reg = <0x40012c00 0x400>; diff --git a/dts/arm/st/f2/stm32f2.dtsi b/dts/arm/st/f2/stm32f2.dtsi index a5b1e1bb44d..bdf8bd85f2b 100644 --- a/dts/arm/st/f2/stm32f2.dtsi +++ b/dts/arm/st/f2/stm32f2.dtsi @@ -1,5 +1,6 @@ /* * Copyright (c) 2018 qianfan Zhao + * Copyright (c) 2019 Centaur Analytics, Inc * * SPDX-License-Identifier: Apache-2.0 */ @@ -145,6 +146,15 @@ status = "disabled"; }; + wwdg: watchdog@40002c00 { + compatible = "st,stm32-window-watchdog"; + reg = <0x40002C00 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>; + label = "WWDG"; + interrupts = <0 7>; + status = "disabled"; + }; + usart1: serial@40011000 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40011000 0x400>; diff --git a/dts/arm/st/f3/stm32f3.dtsi b/dts/arm/st/f3/stm32f3.dtsi index 28d49e541f5..995cabad20c 100644 --- a/dts/arm/st/f3/stm32f3.dtsi +++ b/dts/arm/st/f3/stm32f3.dtsi @@ -1,5 +1,6 @@ /* * Copyright (c) 2017 I-SENSE group of ICCS + * Copyright (c) 2019 Centaur Analytics, Inc * * SPDX-License-Identifier: Apache-2.0 */ @@ -111,6 +112,15 @@ status = "disabled"; }; + wwdg: watchdog@40002c00 { + compatible = "st,stm32-window-watchdog"; + reg = <0x40002C00 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>; + label = "WWDG"; + interrupts = <0 7>; + status = "disabled"; + }; + usart1: serial@40013800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40013800 0x400>; diff --git a/dts/arm/st/f4/stm32f4.dtsi b/dts/arm/st/f4/stm32f4.dtsi index 78521c398e5..75993e06c1e 100644 --- a/dts/arm/st/f4/stm32f4.dtsi +++ b/dts/arm/st/f4/stm32f4.dtsi @@ -1,5 +1,6 @@ /* * Copyright (c) 2017 Linaro Limited + * Copyright (c) 2019 Centaur Analytics, Inc * * SPDX-License-Identifier: Apache-2.0 */ @@ -119,6 +120,15 @@ status = "disabled"; }; + wwdg: watchdog@40002c00 { + compatible = "st,stm32-window-watchdog"; + reg = <0x40002C00 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>; + label = "WWDG"; + interrupts = <0 7>; + status = "disabled"; + }; + usart1: serial@40011000 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40011000 0x400>; diff --git a/dts/arm/st/f7/stm32f7.dtsi b/dts/arm/st/f7/stm32f7.dtsi index 80d35a6cbb8..835cedfb80f 100644 --- a/dts/arm/st/f7/stm32f7.dtsi +++ b/dts/arm/st/f7/stm32f7.dtsi @@ -1,5 +1,6 @@ /* * Copyright (c) 2018 Yurii Hamann + * Copyright (c) 2019 Centaur Analytics, Inc * * SPDX-License-Identifier: Apache-2.0 */ @@ -149,6 +150,15 @@ status = "disabled"; }; + wwdg: watchdog@40002c00 { + compatible = "st,stm32-window-watchdog"; + reg = <0x40002C00 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>; + label = "WWDG"; + interrupts = <0 7>; + status = "disabled"; + }; + usart1: serial@40011000 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40011000 0x400>; diff --git a/dts/arm/st/g0/stm32g0.dtsi b/dts/arm/st/g0/stm32g0.dtsi index 30c0e059e28..eeddb18108c 100644 --- a/dts/arm/st/g0/stm32g0.dtsi +++ b/dts/arm/st/g0/stm32g0.dtsi @@ -1,6 +1,7 @@ /* * Copyright (c) 2019 Philippe Retornaz * Copyright (c) 2019 ST Microelectronics + * Copyright (c) 2019 Centaur Analytics, Inc * * SPDX-License-Identifier: Apache-2.0 */ @@ -104,6 +105,15 @@ }; }; + wwdg: watchdog@40002c00 { + compatible = "st,stm32-window-watchdog"; + reg = <0x40002C00 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>; + label = "WWDG"; + interrupts = <0 7>; + status = "disabled"; + }; + usart1: serial@40013800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40013800 0x400>; diff --git a/dts/arm/st/h7/stm32h7.dtsi b/dts/arm/st/h7/stm32h7.dtsi index 66ddf9ebe21..b45e3565476 100644 --- a/dts/arm/st/h7/stm32h7.dtsi +++ b/dts/arm/st/h7/stm32h7.dtsi @@ -1,5 +1,6 @@ /* * Copyright (c) 2019 Linaro Limited + * Copyright (c) 2019 Centaur Analytics, Inc * * SPDX-License-Identifier: Apache-2.0 */ @@ -157,6 +158,15 @@ }; }; + wwdg1: watchdog@50003000 { + compatible = "st,stm32-window-watchdog"; + reg = <0x50003000 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000800>; + interrupts = <0 7>; + status = "disabled"; + label = "WWDG_1"; + }; + usart1: serial@40011000 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40011000 0x400>; diff --git a/dts/arm/st/l0/stm32l0.dtsi b/dts/arm/st/l0/stm32l0.dtsi index 322f12f8558..58913707a5d 100644 --- a/dts/arm/st/l0/stm32l0.dtsi +++ b/dts/arm/st/l0/stm32l0.dtsi @@ -1,5 +1,6 @@ /* * Copyright (c) 2018 Endre Karlson + * Copyright (c) 2019 Centaur Analytics, Inc * * SPDX-License-Identifier: Apache-2.0 */ @@ -110,6 +111,15 @@ status = "disabled"; }; + wwdg: watchdog@40002c00 { + compatible = "st,stm32-window-watchdog"; + reg = <0x40002C00 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>; + label = "WWDG"; + interrupts = <0 7>; + status = "disabled"; + }; + usart1: serial@40013800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40013800 0x400>; diff --git a/dts/arm/st/l1/stm32l1.dtsi b/dts/arm/st/l1/stm32l1.dtsi index ab444490b6e..70e3ef18a08 100644 --- a/dts/arm/st/l1/stm32l1.dtsi +++ b/dts/arm/st/l1/stm32l1.dtsi @@ -1,5 +1,6 @@ /* * Copyright (c) 2019 Linaro Ltd. + * Copyright (c) 2019 Centaur Analytics, Inc * * SPDX-License-Identifier: Apache-2.0 */ @@ -141,6 +142,15 @@ }; }; + wwdg: watchdog@40002c00 { + compatible = "st,stm32-window-watchdog"; + reg = <0x40002C00 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>; + interrupts = <0 7>; + status = "disabled"; + label = "WWDG"; + }; + rcc: rcc@40023800 { compatible = "st,stm32-rcc"; #clock-cells = <2>; diff --git a/dts/arm/st/l4/stm32l4.dtsi b/dts/arm/st/l4/stm32l4.dtsi index a040b1bab94..88443e7fc39 100644 --- a/dts/arm/st/l4/stm32l4.dtsi +++ b/dts/arm/st/l4/stm32l4.dtsi @@ -1,5 +1,6 @@ /* * Copyright (c) 2017 Linaro Limited + * Copyright (c) 2019 Centaur Analytics, Inc * * SPDX-License-Identifier: Apache-2.0 */ @@ -103,6 +104,15 @@ status = "disabled"; }; + wwdg: watchdog@40002c00 { + compatible = "st,stm32-window-watchdog"; + reg = <0x40002C00 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>; + label = "WWDG"; + interrupts = <0 7>; + status = "disabled"; + }; + usart1: serial@40013800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40013800 0x400>; diff --git a/dts/arm/st/mp1/stm32mp157.dtsi b/dts/arm/st/mp1/stm32mp157.dtsi index bd9939d4b15..976e84ed358 100644 --- a/dts/arm/st/mp1/stm32mp157.dtsi +++ b/dts/arm/st/mp1/stm32mp157.dtsi @@ -1,5 +1,6 @@ /* * Copyright (c) 2019 STMicroelectronics + * Copyright (c) 2019 Centaur Analytics, Inc * * SPDX-License-Identifier: Apache-2.0 */ @@ -148,6 +149,15 @@ }; }; + wwdg1: watchdog@4000a000 { + compatible = "st,stm32-window-watchdog"; + reg = <0x4000A000 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>; + label = "WWDG_1"; + interrupts = <0 7>; + status = "disabled"; + }; + spi1: spi@44004000 { compatible = "st,stm32-spi-fifo"; reg = <0x44004000 0x400>; diff --git a/dts/arm/st/wb/stm32wb.dtsi b/dts/arm/st/wb/stm32wb.dtsi index 3ac61e37e10..a54d47cdf40 100644 --- a/dts/arm/st/wb/stm32wb.dtsi +++ b/dts/arm/st/wb/stm32wb.dtsi @@ -1,5 +1,6 @@ /* * Copyright (c) 2019 Linaro Limited + * Copyright (c) 2019 Centaur Analytics, Inc * * SPDX-License-Identifier: Apache-2.0 */ @@ -112,6 +113,15 @@ }; }; + wwdg: watchdog@40002c00 { + compatible = "st,stm32-window-watchdog"; + reg = <0x40002C00 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>; + label = "WWDG"; + interrupts = <0 7>; + status = "disabled"; + }; + usart1: serial@40013800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40013800 0x400>; diff --git a/dts/bindings/watchdog/st,stm32-window-watchdog.yaml b/dts/bindings/watchdog/st,stm32-window-watchdog.yaml new file mode 100644 index 00000000000..60133fff015 --- /dev/null +++ b/dts/bindings/watchdog/st,stm32-window-watchdog.yaml @@ -0,0 +1,21 @@ +# Copyright (c) 2019 Centaur Analytics, Inc +# SPDX-License-Identifier: Apache-2.0 + +title: STMicroelectronics STM32 system window watchdog driver + +description: > + This is a representation of the STM32 system window watchdog + +compatible: "st,stm32-window-watchdog" + +include: base.yaml + +properties: + reg: + required: true + + label: + required: true + + clocks: + required: true