driver: pinctrl: Add support for Renesas RZ/G2L
Add pinctrl support for Renesas RZ/G2L Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com> Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
This commit is contained in:
Tien Nguyen
Benjamin Cabé
parent
433a19ccaf
commit
1d736d36ab
5 changed files with 188 additions and 8 deletions
23
boards/renesas/rzg2l_smarc/rzg2l_smarc-pinctrl.dtsi
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23
boards/renesas/rzg2l_smarc/rzg2l_smarc-pinctrl.dtsi
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@ -0,0 +1,23 @@
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/*
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* Copyright (c) 2025 Renesas Electronics Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzg2-common.h>
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&pinctrl {
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/omit-if-no-ref/ scif0_pins: scif0 {
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scif0-pinmux {
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pinmux = <RZG_PINMUX(PORT_38, 0, 1)>, /* TXD */
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<RZG_PINMUX(PORT_38, 1, 1)>; /* RXD */
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};
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};
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/omit-if-no-ref/ scif2_pins: scif2 {
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scif2-pinmux {
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pinmux = <RZG_PINMUX(PORT_48, 0, 1)>, /* TXD */
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<RZG_PINMUX(PORT_48, 1, 1)>; /* RXD */
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};
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};
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};
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@ -32,6 +32,12 @@
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};
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};
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soc {
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soc {
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pinctrl: pin-controller@41030000 {
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compatible = "renesas,rzg-pinctrl";
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reg = <0x41030000 DT_SIZE_K(64)>;
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reg-names = "pinctrl";
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};
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scif0: serial@4004b800 {
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scif0: serial@4004b800 {
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compatible = "renesas,rz-scif-uart";
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compatible = "renesas,rz-scif-uart";
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channel = <0>;
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channel = <0>;
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@ -1,11 +1,18 @@
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# Copyright (c) 2024 Epam Systems
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# Copyright (c) 2024 Epam Systems
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# Copyright (c) 2024 Renesas Electronics Corporation
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# Copyright (c) 2024-2025 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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# SPDX-License-Identifier: Apache-2.0
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description: |
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description: |
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Below generic example shows of supported pinctrl definitions:
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Renesas RZ/G pin controller
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#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl_rzg3s.h>
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The Renesas RZ/G pin controller is a node responsible for controlling
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pin function selection and pin properties.
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The pre-defined combinations for the RZ/G variants are defined in the below headers
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- pinctrl-rzg-common.h for RZ/G3S
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- pinctrl-rzg2-common.h for RZ/G2L, RZ/G2LC
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#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzg(2)-common.h>
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example_pins: device_pin {
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example_pins: device_pin {
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device-pinmux {
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device-pinmux {
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pinmux = <RZG_PINMUX(PORT_08, 1, 5)>,
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pinmux = <RZG_PINMUX(PORT_08, 1, 5)>,
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@ -65,13 +72,13 @@ child-binding:
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Pinmux configuration node.
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Pinmux configuration node.
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Values are constructed from GPIO port number, pin number, and
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Values are constructed from GPIO port number, pin number, and
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alternate function configuration number using the RZG_PINMUX()
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alternate function configuration number using the RZG_PINMUX()
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helper macro in pinctrl_rzg.h
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helper macro in pinctrl-rzg(2)-common.h.
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pins:
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pins:
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type: array
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type: array
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description: |
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description: |
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Special Purpose pins configuration node.
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Special Purpose pins configuration node.
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Values are define in pinctrl_rzg.h.
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Values are define in pinctrl-rzg(2)-common.h.
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Ex: BSP_IO_XSPI_IO0,BSP_IO_I3C_SCL,...
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Ex: BSP_IO_XSPI_IO0,BSP_IO_I3C_SCL,...
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drive-strength:
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drive-strength:
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138
include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzg2-common.h
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138
include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzg2-common.h
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@ -0,0 +1,138 @@
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/*
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* Copyright (c) 2025 Renesas Electronics Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZG2_COMMON_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZG2_COMMON_H_
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/* Superset list of all possible IO ports. */
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#define PORT_00 0x0000 /* IO port 0 */
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#define PORT_01 0x0100 /* IO port 1 */
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#define PORT_02 0x0200 /* IO port 2 */
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#define PORT_03 0x0300 /* IO port 3 */
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#define PORT_04 0x0400 /* IO port 4 */
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#define PORT_05 0x0500 /* IO port 5 */
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#define PORT_06 0x0600 /* IO port 6 */
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#define PORT_07 0x0700 /* IO port 7 */
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#define PORT_08 0x0800 /* IO port 8 */
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#define PORT_09 0x0900 /* IO port 9 */
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#define PORT_10 0x0A00 /* IO port 10 */
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#define PORT_11 0x0B00 /* IO port 11 */
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#define PORT_12 0x0C00 /* IO port 12 */
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#define PORT_13 0x0D00 /* IO port 13 */
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#define PORT_14 0x0E00 /* IO port 14 */
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#define PORT_15 0x0F00 /* IO port 15 */
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#define PORT_16 0x1000 /* IO port 16 */
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#define PORT_17 0x1100 /* IO port 17 */
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#define PORT_18 0x1200 /* IO port 18 */
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#define PORT_19 0x1300 /* IO port 19 */
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#define PORT_20 0x1400 /* IO port 20 */
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#define PORT_21 0x1500 /* IO port 21 */
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#define PORT_22 0x1600 /* IO port 22 */
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#define PORT_23 0x1700 /* IO port 23 */
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#define PORT_24 0x1800 /* IO port 24 */
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#define PORT_25 0x1900 /* IO port 25 */
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#define PORT_26 0x1A00 /* IO port 26 */
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#define PORT_27 0x1B00 /* IO port 27 */
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#define PORT_28 0x1C00 /* IO port 28 */
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#define PORT_29 0x1D00 /* IO port 29 */
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#define PORT_30 0x1E00 /* IO port 30 */
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#define PORT_31 0x1F00 /* IO port 31 */
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#define PORT_32 0x2000 /* IO port 32 */
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#define PORT_33 0x2100 /* IO port 33 */
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#define PORT_34 0x2200 /* IO port 34 */
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#define PORT_35 0x2300 /* IO port 35 */
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#define PORT_36 0x2400 /* IO port 36 */
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#define PORT_37 0x2500 /* IO port 37 */
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#define PORT_38 0x2600 /* IO port 38 */
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#define PORT_39 0x2700 /* IO port 39 */
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#define PORT_40 0x2800 /* IO port 40 */
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#define PORT_41 0x2900 /* IO port 41 */
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#define PORT_42 0x2A00 /* IO port 42 */
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#define PORT_43 0x2B00 /* IO port 43 */
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#define PORT_44 0x2C00 /* IO port 44 */
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#define PORT_45 0x2D00 /* IO port 45 */
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#define PORT_46 0x2E00 /* IO port 46 */
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#define PORT_47 0x2F00 /* IO port 47 */
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#define PORT_48 0x3000 /* IO port 48 */
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/*
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* Create the value contain port/pin/function information
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*
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* port: port number BSP_IO_PORT_00..BSP_IO_PORT_48
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* pin: pin number
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* func: pin function
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*/
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#define RZG_PINMUX(port, pin, func) (port | pin | (func << 4))
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/* Special purpose port */
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#define BSP_IO_NMI 0xFFFF0100 /* NMI */
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#define BSP_IO_TMS_SWDIO 0xFFFF0200 /* TMS_SWDIO */
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#define BSP_IO_TDO 0xFFFF0300 /* TDO */
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#define BSP_IO_AUDIO_CLK1 0xFFFF0400 /* AUDIO_CLK1 */
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#define BSP_IO_AUDIO_CLK2 0xFFFF0401 /* AUDIO_CLK2 */
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#define BSP_IO_SD0_CLK 0xFFFF0600 /* SD0_CLK */
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#define BSP_IO_SD0_CMD 0xFFFF0601 /* SD0_CMD */
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#define BSP_IO_SD0_RST_N 0xFFFF0602 /* SD0_RST_N */
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#define BSP_IO_SD0_DATA0 0xFFFF0700 /* SD0_DATA0 */
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#define BSP_IO_SD0_DATA1 0xFFFF0701 /* SD0_DATA1 */
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#define BSP_IO_SD0_DATA2 0xFFFF0702 /* SD0_DATA2 */
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#define BSP_IO_SD0_DATA3 0xFFFF0703 /* SD0_DATA3 */
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#define BSP_IO_SD0_DATA4 0xFFFF0704 /* SD0_DATA4 */
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#define BSP_IO_SD0_DATA5 0xFFFF0705 /* SD0_DATA5 */
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#define BSP_IO_SD0_DATA6 0xFFFF0706 /* SD0_DATA6 */
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#define BSP_IO_SD0_DATA7 0xFFFF0707 /* SD0_DATA7 */
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#define BSP_IO_SD1_CLK 0xFFFF0800 /* SD1_CLK */
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#define BSP_IO_SD1_CMD 0xFFFF0801 /* SD1_CMD */
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#define BSP_IO_SD1_DATA0 0xFFFF0900 /* SD1_DATA0 */
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#define BSP_IO_SD1_DATA1 0xFFFF0901 /* SD1_DATA1 */
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#define BSP_IO_SD1_DATA2 0xFFFF0902 /* SD1_DATA2 */
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#define BSP_IO_SD1_DATA3 0xFFFF0903 /* SD1_DATA3 */
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#define BSP_IO_QSPI0_SPCLK 0xFFFF0A00 /* QSPI0_SPCLK */
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#define BSP_IO_QSPI0_IO0 0xFFFF0A01 /* QSPI0_IO0 */
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#define BSP_IO_QSPI0_IO1 0xFFFF0A02 /* QSPI0_IO1 */
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#define BSP_IO_QSPI0_IO2 0xFFFF0A03 /* QSPI0_IO2 */
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#define BSP_IO_QSPI0_IO3 0xFFFF0A04 /* QSPI0_IO3 */
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#define BSP_IO_QSPI0_SSL 0xFFFF0A05 /* QSPI0_SSL */
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#define BSP_IO_QSPI1_SPCLK 0xFFFF0B00 /* QSPI1_SPCLK */
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#define BSP_IO_QSPI1_IO0 0xFFFF0B01 /* QSPI1_IO0 */
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#define BSP_IO_QSPI1_IO1 0xFFFF0B02 /* QSPI1_IO1 */
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#define BSP_IO_QSPI1_IO2 0xFFFF0B03 /* QSPI1_IO2 */
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#define BSP_IO_QSPI1_IO3 0xFFFF0B04 /* QSPI1_IO3 */
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#define BSP_IO_QSPI1_SSL 0xFFFF0B05 /* QSPI1_SSL */
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#define BSP_IO_QSPI_RESET_N 0xFFFF0C00 /* QSPI_RESET_N */
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#define BSP_IO_QSPI_WP_N 0xFFFF0C01 /* QSPI_WP_N */
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#define BSP_IO_QSPI_INT_N 0xFFFF0C02 /* QSPI_INT_N */
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#define BSP_IO_WDTOVF_PERROUT_N 0xFFFF0D00 /* WDTOVF_PERROUT_N */
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#define BSP_IO_RIIC0_SDA 0xFFFF0E00 /* RIIC0_SDA */
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#define BSP_IO_RIIC0_SCL 0xFFFF0E01 /* RIIC0_SCL */
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#define BSP_IO_RIIC1_SDA 0xFFFF0E02 /* RIIC1_SDA */
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#define BSP_IO_RIIC1_SCL 0xFFFF0E03 /* RIIC1_SCL */
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/* FILNUM */
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#define RZG_FILNUM_4_STAGE 0
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#define RZG_FILNUM_8_STAGE 1
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#define RZG_FILNUM_12_STAGE 2
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#define RZG_FILNUM_16_STAGE 3
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/* FILCLKSEL */
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#define RZG_FILCLKSEL_NOT_DIV 0
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#define RZG_FILCLKSEL_DIV_9000 1
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#define RZG_FILCLKSEL_DIV_18000 2
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#define RZG_FILCLKSEL_DIV_36000 3
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#define RZG_FILTER_SET(filnum, filclksel) (((filnum) & 0x3) << 0x2) | (filclksel & 0x3)
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#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZG2_COMMON_H_ */
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@ -61,6 +61,14 @@ typedef struct pinctrl_soc_pin_t {
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#define RZG_FILTER_ON_OFF(node_id) COND_CODE_0(DT_PROP(node_id, renesas_filter), (0), (1))
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#define RZG_FILTER_ON_OFF(node_id) COND_CODE_0(DT_PROP(node_id, renesas_filter), (0), (1))
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#if defined(CONFIG_SOC_SERIES_RZG3S)
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#define RZG_GET_PFC(node_id, state_prop, idx) \
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(RZG_GET_FUNC(DT_PROP_BY_IDX(node_id, state_prop, idx)) - 1)
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#else
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#define RZG_GET_PFC(node_id, state_prop, idx) \
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(RZG_GET_FUNC(DT_PROP_BY_IDX(node_id, state_prop, idx)))
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#endif
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/* Process pinmux cfg */
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/* Process pinmux cfg */
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#define Z_PINCTRL_PINMUX_INIT(node_id, state_prop, idx) \
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#define Z_PINCTRL_PINMUX_INIT(node_id, state_prop, idx) \
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{ \
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{ \
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@ -75,9 +83,7 @@ typedef struct pinctrl_soc_pin_t {
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.filonoff_reg = RZG_FILTER_ON_OFF(node_id), \
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.filonoff_reg = RZG_FILTER_ON_OFF(node_id), \
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.filnum_reg = RZG_GET_FILNUM(node_id), \
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.filnum_reg = RZG_GET_FILNUM(node_id), \
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.filclksel_reg = RZG_GET_FILCLKSEL(node_id), \
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.filclksel_reg = RZG_GET_FILCLKSEL(node_id), \
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.pfc_reg = \
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.pfc_reg = RZG_GET_PFC(node_id, state_prop, idx), \
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(RZG_GET_FUNC(DT_PROP_BY_IDX(node_id, state_prop, idx)) - \
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1), \
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}, \
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}, \
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},
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},
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