1d736d36ab
Add pinctrl support for Renesas RZ/G2L Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com> Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
90 lines
2.1 KiB
Text
90 lines
2.1 KiB
Text
/*
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* Copyright (c) 2025 Renesas Electronics Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv8-m.dtsi>
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#include <mem.h>
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#include <freq.h>
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/ {
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compatible = "renesas,r9a07g044";
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m33";
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reg = <0>;
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clock-frequency = <DT_FREQ_M(200)>;
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#address-cells = <1>;
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#size-cells = <1>;
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mpu: mpu@e000ed90 {
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compatible = "arm,armv8m-mpu";
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reg = <0xe000ed90 0x40>;
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};
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};
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};
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soc {
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pinctrl: pin-controller@41030000 {
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compatible = "renesas,rzg-pinctrl";
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reg = <0x41030000 DT_SIZE_K(64)>;
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reg-names = "pinctrl";
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};
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scif0: serial@4004b800 {
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compatible = "renesas,rz-scif-uart";
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channel = <0>;
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reg = <0x4004b800 DT_SIZE_K(1)>;
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interrupts = <380 1>, <381 1>, <382 1>, <383 1>, <384 1>;
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interrupt-names = "eri", "bri", "rxi", "txi", "tei";
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status = "disabled";
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};
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scif1: serial@4004bc00 {
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compatible = "renesas,rz-scif-uart";
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channel = <1>;
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reg = <0x4004bc00 DT_SIZE_K(1)>;
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interrupts = <385 1>, <386 1>, <387 1>, <388 1>, <389 1>;
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interrupt-names = "eri", "bri", "rxi", "txi", "tei";
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status = "disabled";
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};
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scif2: serial@4004c000 {
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compatible = "renesas,rz-scif-uart";
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channel = <2>;
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reg = <0x4004c000 DT_SIZE_K(1)>;
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interrupts = <390 1>, <391 1>, <392 1>, <393 1>, <394 1>;
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interrupt-names = "eri", "bri", "rxi", "txi", "tei";
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status = "disabled";
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};
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scif3: serial@4004c400 {
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compatible = "renesas,rz-scif-uart";
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channel = <3>;
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reg = <0x4004c400 DT_SIZE_K(1)>;
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interrupts = <395 1>, <396 1>, <397 1>, <398 1>, <399 1>;
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interrupt-names = "eri", "bri", "rxi", "txi", "tei";
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status = "disabled";
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};
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scif4: serial@4004c800 {
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compatible = "renesas,rz-scif-uart";
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channel = <4>;
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reg = <0x4004c800 DT_SIZE_K(1)>;
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interrupts = <400 1>, <401 1>, <402 1>, <403 1>, <404 1>;
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interrupt-names = "eri", "bri", "rxi", "txi", "tei";
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status = "disabled";
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <7>;
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};
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