dts: intel_s1000: add pinctrl to device tree
Add pinctrl node to Intel S1000 SoC device tree for I/O MUX selection Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
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3 changed files with 36 additions and 0 deletions
26
dts/bindings/pinctrl/intel,s1000-pinmux.yaml
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26
dts/bindings/pinctrl/intel,s1000-pinmux.yaml
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@ -0,0 +1,26 @@
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---
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# SPDX-License-Identifier: Apache-2.0
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title: Intel S1000 Pinmux
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version: 0.1
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description: >
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This is a representation of the Intel S1000 SoC's pinmux node
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properties:
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compatible:
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type: string
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category: required
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description: compatible strings
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constraint: "intel,s1000-pinmux"
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generation: define
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reg:
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type: int
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description: mmio register space
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generation: define
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category: required
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"#cells":
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- pin
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- function
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...
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@ -97,6 +97,11 @@
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#gpio-cells = <2>;
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#gpio-cells = <2>;
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};
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};
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pinmux: pinmux@81C30 {
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compatible = "intel,s1000-pinmux";
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reg = <0x00081C30 0xC>;
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};
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uart0: uart@80800 {
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uart0: uart@80800 {
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compatible = "ns16550";
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compatible = "ns16550";
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reg = <0x80800 0x400>;
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reg = <0x80800 0x400>;
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@ -77,4 +77,9 @@
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#define CONFIG_GPIO_DW_0_NAME \
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#define CONFIG_GPIO_DW_0_NAME \
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DT_SNPS_DESIGNWARE_GPIO_80C00_LABEL
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DT_SNPS_DESIGNWARE_GPIO_80C00_LABEL
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#define DT_PINMUX_BASE_ADDR \
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DT_INTEL_S1000_PINMUX_81C30_BASE_ADDRESS
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#define DT_PINMUX_CTRL_REG_COUNT \
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(DT_INTEL_S1000_PINMUX_81C30_SIZE / 4)
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/* End of SoC Level DTS fixup file */
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/* End of SoC Level DTS fixup file */
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